TWI636547B - Semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

A semiconductor memory device includes a substrate, a plurality of first isolation structures, and a plurality of second isolation structures. The substrate includes a peripheral region and an array region. The first isolation structure is located in the substrate of the peripheral region. The second isolation structure is located in the substrate of the array region. The material of the first isolation structure is different from the material of the second isolation structure. The width of each of the first isolation structures is greater than the width of each of the second isolation structures.

Description

Semiconductor memory element and method of manufacturing same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor memory device and a method of fabricating the same.

With the advancement of semiconductor technology, in order to reduce the cost, simplify the process steps and save the wafer area, it has become a trend to integrate the elements of the memory cell array and the peripheral circuit area on the same wafer. As the size of components continues to shrink, isolation between components and components becomes quite important in order to prevent short circuits between adjacent components.

In general, flowable dielectric materials are often used as materials for the isolation structure. However, when the heat treatment is performed to remove the solvent in the flowable dielectric material, the substrate or the isolation structure in the peripheral circuit region is severely affected due to the stress or shrinkage of the flowable dielectric material. Dislocation problems, and even cracks or cracks. If there is a crack or crack in the substrate or the isolation structure, the isolation capability of the isolation structure is deteriorated, which causes problems such as leakage current of the element or deterioration of reliability of the element.

The invention provides a semiconductor memory device and a manufacturing method thereof, which can avoid misalignment or cracking of a substrate or an isolation structure in a peripheral circuit region, thereby reducing leakage current of the component and improving reliability of the component.

The present invention provides a semiconductor memory device including a substrate, a plurality of first isolation structures, and a plurality of second isolation structures. The substrate includes a peripheral region and an array region. The first isolation structure is located in the substrate of the peripheral region. The second isolation structure is located in the substrate of the array region. The material of the first isolation structure is different from the material of the second isolation structure. The width of each of the first isolation structures is greater than the width of each of the second isolation structures.

The present invention provides a method of fabricating a semiconductor memory device, the steps of which are as follows. A substrate is provided that includes a peripheral region and an array region. A plurality of first stacked structures are formed on the substrate of the peripheral region. A plurality of first trenches are respectively formed between the first stacked structures. The first trench extends from the top surface of the first stacked structure into the substrate. A plurality of second stacked structures are formed on the substrate of the array region. A plurality of second trenches are respectively formed between the second stacked structures. The second trench extends from the top surface of the second stacked structure into the substrate. The width of the second trench is smaller than the width of the first trench. The first isolation material is simultaneously filled into the first trench and the second trench. A mask pattern is formed on the substrate of the array region. The mask pattern exposes a top surface of the first isolation material in the first trench. The mask pattern is used as a mask to remove at least a portion of the first isolation material in the first trench. A second isolation material is formed in the first trench. Heat treatment is performed.

Based on the above, the present invention fills in the week by simultaneously inserting a flowable dielectric material The first trench of the edge region and the second trench of the array region allow the flowable dielectric material to fill the second trench having a high aspect ratio. Next, at least a portion of the flowable dielectric material in the first trench is removed. Thereafter, a chemical vapor deposited oxide is formed in the first trench. When the subsequent heat treatment is performed to remove the solvent of the flowable dielectric material, since the area between the flowable dielectric material and the substrate in the first trench has been lowered, the substrate or the isolation structure of the peripheral region is less likely to be misaligned. With cracks. In this way, the isolation structure of the peripheral region and the array region of the present invention has better isolation capability, thereby reducing leakage current of the component, increasing the breakdown voltage of the component, and improving the reliability of the component.

The above described features and advantages of the invention will be apparent from the following description.

10‧‧‧First ditches

12‧‧‧Second ditches

100‧‧‧Base

100T‧‧‧top top

102‧‧‧First gate dielectric layer

104‧‧‧First Gate

106‧‧‧hard mask layer

108‧‧‧Dielectric materials

108a, 108b‧‧‧ dielectric layer

110, 110a‧‧‧ first stack structure

110T, 114T, 114T', 210T, 214T‧‧‧ top

112, 114, 114a, 214‧‧‧ first insulation material

114b‧‧‧lower structure

118a‧‧‧Superstructure

122‧‧‧First isolation structure

116‧‧‧ mask pattern

118‧‧‧Second insulation material

120‧‧‧ heat treatment

210, 210a‧‧‧ second stack structure

202‧‧‧Second gate dielectric layer

204‧‧‧second gate

206‧‧‧hard mask layer

222‧‧‧Second isolation structure

AR‧‧‧Array area

PR‧‧‧ surrounding area

S002, S004, S006, S008, S010, S012, S014, S016, S102, S104, S106, S108, S110, S112, S114, S116‧‧

D1, D2‧‧ depth

D3‧‧‧ distance

H1, H2‧‧‧ height

W1, W1', W2, W2'‧‧‧ width

1 is a flow chart of a method of fabricating a semiconductor memory device in accordance with a first embodiment of the present invention.

2A through 2H are schematic cross-sectional views showing a method of fabricating a semiconductor memory device in accordance with a first embodiment of the present invention.

3 is a flow chart of a method of fabricating a semiconductor memory device in accordance with a second embodiment of the present invention.

The invention will be more fully described with reference to the drawings of the embodiments. However, the invention may be embodied in a variety of different forms and should not be limited to the embodiments described herein. The thickness of layers and regions in the drawings will be exaggerated for clarity. The same or similar reference numerals are used for the same or similar elements and will not be described again in the following paragraphs.

1 is a flow chart of a method of fabricating a semiconductor memory device in accordance with a first embodiment of the present invention. 2A through 2H are schematic cross-sectional views showing a method of fabricating a semiconductor memory device in accordance with a first embodiment of the present invention.

Referring to FIG. 1 and FIG. 2A, first, step S002 is performed to provide the substrate 100. In one embodiment, the substrate 100 can be, for example, a semiconductor substrate, a semiconductor compound substrate, or a semiconductor substrate (Semiconductor Over Insulator (SOI)). The semiconductor is, for example, an atom of the IVA group, such as ruthenium or osmium. The semiconductor compound is, for example, a semiconductor compound formed of atoms of Group IVA, such as tantalum carbide or germanium telluride, or a semiconductor compound formed of a group IIIA atom and a group VA atom, such as gallium arsenide.

In the present embodiment, the substrate 100 includes a peripheral region PR and an array region AR. The peripheral region PR may be, for example, a peripheral circuit region having a MOS device therein. The array area AR may be, for example, a memory cell array region having a memory element therein. In other embodiments, the array area AR may be a dense area of components whose number of elements per unit area is larger than the number of elements in the unit area of the peripheral area PR.

Next, in step S004, a plurality of first stacked structures 110 are formed on the substrate 100 of the peripheral region PR, and a plurality of second stacked structures 210 are formed on the substrate 100 of the array region AR. In detail, the first stacked structure 110 includes the self-substrate 100 The top facing up includes the first gate dielectric layer 102, the first gate 104, and the hard mask layer 106. In an embodiment, the material of the first gate dielectric layer 102 may be, for example, hafnium oxide, tantalum nitride or a combination thereof, and the formation method thereof may be formed by chemical vapor deposition. The first gate 104 material may be, for example, doped polysilicon, undoped polysilicon or a combination thereof, and the formation method thereof may be formed by chemical vapor deposition. The material of the hard mask layer 106 may be, for example, hafnium oxide, tantalum nitride or a combination thereof, and the formation method thereof may be formed by chemical vapor deposition. In this embodiment, the first gate dielectric layer 102 and the first gate 104 may constitute a gate structure of a MOS device, and the substrate 100 on both sides of the gate structure has a source and a drain (not Painted).

In addition, the second stacked structure 210 includes a second gate dielectric layer 202, a second gate 204, and a hard mask layer 206 sequentially from the top surface of the substrate 100. The material and formation method of the second gate dielectric layer 202, the second gate 204, and the hard mask layer 206 are similar to the materials and formation methods of the first gate dielectric layer 102, the first gate 104, and the hard mask layer 106. This will not be repeated here. In the present embodiment, the second gate dielectric layer 202 can be used as a tunneling dielectric layer of the memory element; the second gate 204 can be used as a floating gate of the memory element. In an embodiment, the thickness of the second gate dielectric layer 202 is less than the thickness of the first gate dielectric layer 102. The thickness of the second gate dielectric layer 202 may be between 5 nm and 10 nm; the thickness of the first gate dielectric layer 102 may be between 5 nm and 70 nm.

Then, in step S006, a plurality of first trenches 10 are respectively formed between the first stacked structures 110, and a plurality of second trenches 12 are respectively formed between the second stacked structures 210. In detail, the method for forming the first trench 10 and the second trench 12 can be A mask pattern (not shown) is formed on the top surfaces of the first stack structure 110 and the second stack structure 210 to expose a position or an area where the first trench 10 and the second trench 12 are to be formed. Removing a portion of the hard mask layer 106, 206, a portion of the first gate 104, a portion of the second gate 204, a portion of the first gate dielectric layer 102, a portion of the second gate dielectric layer 202, and a portion of the substrate 100 such that the first The trench 10 extends from the top surface of the first stacked structure 110 into the substrate 100, and the second trench 12 extends from the top surface of the second stacked structure 210 into the substrate 100 (as shown in FIG. 2A). That is, the first trench 10 and the second trench 12 can be formed simultaneously, and the bottom surfaces of the two can be substantially coplanar.

After the first trench 10 and the second trench 12 are formed, a dielectric material 108 is formed on the substrate 100. As shown in FIG. 2A, dielectric material 108 conformally covers the surface of first trench 10, the surface of second trench 12, and the top surface of hard mask layers 106, 206. In an embodiment, the dielectric material 108 may be ruthenium oxide, and the formation method thereof may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), or a combination thereof.

It is to be noted that the width W2 of the second trench 12 located in the array area AR is smaller than the width W1 of the first trench 10 of the peripheral area PR. In addition, the aspect ratio of the second trench 12 located in the array region AR is greater than the aspect ratio of the first trench 10 of the peripheral region PR. In an embodiment, the width W1 of the first trench 10 may be between 0.2 micrometers and 8 micrometers; and the width W2 of the second trench 12 may be between 0.01 micrometers and 0.03 micrometers. In an embodiment, the aspect ratio (depth D1/width W1) of the first trench 10 may be between 0.04 and 2; the aspect ratio (depth D2/width W2) of the second trench 12 may be between 10 and Between 35.

Referring to FIG. 1 and FIG. 2B, step S008 is performed to apply the first isolation material. 112 is simultaneously filled into the first trench 10 and the second trench 12. The first isolation material 112 not only fills the first trench 10 and the second trench 12 but also covers the top surfaces of the first stacked structure 110 and the second stacked structure 210. In the present embodiment, the first isolation material 112 may be a flowable dielectric material such as a spin-on dielectric material. The flowable dielectric material has a better filling ability, which can be filled into the second trench 12 having a high aspect ratio without forming a hole, so that the second isolation structure 222 is formed later (see FIG. 2H). Shown) has better isolation capabilities.

In one embodiment, the method of forming the first isolation material 112 includes spin-on dielectric (SOD), flowable chemical vapor deposition (FCVD), or a combination thereof. For example, in a spin-on dielectric method, a flowable dielectric material (for example, polysilazane (PSZ)) may be spin-coated on a substrate 100 such that the flowable dielectric material is filled in. The first trench 10 and the second trench 12 are formed without forming holes.

Referring to FIG. 2B and FIG. 2C , a planarization process is performed to remove the first isolation material 112 , the dielectric material 108 , and the hard mask layers 106 , 206 on the top surfaces of the first stacked structure 110 and the second stacked structure 210 . In an embodiment, the planarization process may be a chemical mechanical polishing process (CMP) or an etch back process. After the planarization process, the first isolation material remaining in the first trench 10 can be regarded as the first isolation material 114, and the dielectric layer 108a is located on the first isolation material 114 and the substrate 100 (or the first stacked structure 110a). between. The first isolation material remaining in the second trench 12 can be considered as the first isolation material 214, and the dielectric layer 108b is located between the first isolation material 214 and the substrate 100 (or the second stacked structure 210a). In this case, as shown in Figure 2C As shown, the top surface 214T of the first isolation material 214 in the second trench 12 is substantially coplanar with the top surface 210T of the second stacked structure 210a. On the other hand, since the top surface 110T of the first stacked structure 110a is higher than the top surface 210T of the second stacked structure 210a, the top surface of the first isolation material 114 between the first stacked structure 110a and the second stacked structure 210a 114T is a slope. The height of the slope decreases from the first stack structure 110a toward the second stack structure 210a.

Referring to FIG. 1 and FIG. 2D, step S010 is performed to form a mask pattern 116 on the substrate 100 of the array area AR. The mask pattern 116 covers the first isolation material 214 in the second trench 12 of the array region AR and exposes the top surface 114T of the first isolation material 114 in the first trench 10 of the peripheral region PR. In an embodiment, the mask pattern 116 may be a photoresist type material, and the forming method thereof may be, for example, a lithography process.

Referring to FIG. 1 and FIG. 2D-2E, step S012 is performed to remove a portion of the first isolation material 114 in the first trench 10 with the mask pattern 116 as a mask. In an embodiment, the method of removing a portion of the first isolation material 114 in the first trench 10 includes a dry etch process, a wet etch process, or a combination thereof. In detail, the dry etching method includes using a reaction gas having a fluorinated hydrocarbon compound mixed with nitrogen and oxygen. The fluorohydrocarbon compound can be represented as CxFy (x is 4-6, y is 6-8) or CxHyFz (x is 1-2, y is 1-3, z is 1-3). The wet etching method includes an etchant using buffered hydrofluoric acid (BHF), diluted hydrofluoric acid (DHF), or a combination thereof. The reactive gas and the etchant have high etch selectivity to the first isolation material 114 and the first gate 104.

It is worth noting that the first isolation material 114 in the first trench 10 is removed. After a portion, the distance D3 between the top surface 114T' of the remaining first isolation material 114a and the highest top surface 100T of the substrate 100 (ie, the interface between the substrate 100 and the first gate dielectric layer 102) is at least greater than 500 Å. . This step reduces the area between the first isolation material 114a (i.e., the flowable dielectric material) in the first trench 10 and the substrate 100. In this way, the present embodiment can avoid misalignment in the substrate 100 or the first isolation structure 122 (shown in FIG. 2H) in the peripheral region PR due to stress or shrinkage of the flowable dielectric material during subsequent heat treatment. Or crack problem. In an embodiment, the distance D3 between the top surface 114T' of the remaining first isolation material 114a and the highest top surface 100T of the substrate 100 may be between 500 Å and 3000 Å. In an alternate embodiment, the first isolation material 114 in the first trench 10 can also be completely removed.

Referring to FIG. 1 and FIG. 2F, step S014 is performed to form a second isolation material 118 in the first trench 10. The second isolation material 118 not only fills the space on the first isolation material 114a, but also covers the top surfaces of the first stacked structure 110a and the second stacked structure 210a. In an embodiment, the second isolation material 118 may be a chemical vapor deposition oxide, and the formation method thereof may be, for example, high density plasma chemical vapor deposition (HDP CVD), high aspect ratio filling process (e-HARP). ) or a combination thereof. Since the density and the 矽-oxygen bond strength of the second isolation material 118 are greater than the density and the 矽-oxygen bond strength of the first isolation material 114a, 214 (ie, the flowable dielectric material), the second isolation Material 118 fills most of the space in first trench 10 without creating misalignment or cracking problems after subsequent heat treatment.

Referring to FIG. 1 and FIG. 2F-2G, step S016 is performed to perform heat treatment 120 to remove the solvent in the first isolation material 114a, 214 (ie, the fluid dielectric material) to cure the flowability. Electrical material. In an embodiment, the heat treatment 120 can be a furnace tube heat treatment or a rapid heat treatment. Taking the heat treatment of the furnace tube as an example, it can be carried out at a temperature of 300 ° C to 500 ° C for 30 minutes to 60 minutes under a H ₂ O atmosphere. It is then carried out at a temperature of 700 ° C to 900 ° C for 30 minutes to 60 minutes under N ₂ ambient gas.

It is to be noted that the area between the cured first isolation material 114b and the substrate 100 is smaller than the space of the entire first trench 10. After the heat treatment 120, the stress of the cured first isolating material 114b is also reduced. Therefore, misalignment or cracking of the substrate 100 or the cured first insulating material 114b in the peripheral region PR can be avoided, thereby reducing the leakage current of the device. Increase the component's breakdown voltage and increase component reliability. In addition, a flowable dielectric material having a better filling ability is filled into the second trench 12 having a high aspect ratio, which does not form a hole, so that the cured first insulating material 222 (ie, the second The isolation structure 222) has better isolation capabilities.

Referring to FIG. 2G and FIG. 2H, after performing the heat treatment 120, a planarization process is further included to remove the second isolation material 118 on the top surface of the first stacked structure 110a and the second stacked structure 210a. In an embodiment, the planarization process may be a chemical mechanical polishing process or an etch back process. After the planarization process, the second isolation material 118a remaining in the first trench 10 can be regarded as the upper structure 118a of the first isolation structure 122; and the cured first isolation material 114b can be regarded as the lower portion of the first isolation structure 122. Structure 114b. The lower structure 114b and the upper structure 118a on the lower structure 114b may constitute the first isolation structure 122. In an embodiment, the lower structure 114b of the first isolation structure 122 is the same material as the second isolation structure 222 and At the same time, the upper structure 118a of the first isolation structure 122 is different from the material of the second isolation structure 222.

In addition, after the planarization process, the manufacturing method further includes sequentially forming an interlayer dielectric layer and a control gate (not shown) on the second stacked structure 210a of the array region AR to form a plurality of memory components. . In one embodiment, the memory element comprises a flash memory, such as a reverse (NAND) flash memory.

As shown in FIG. 2H, the semiconductor memory device of the present embodiment includes a substrate 100, a plurality of first stacked structures 110a, a plurality of second stacked structures 210a, a plurality of first isolation structures 122, and a plurality of second isolation structures 222. The substrate 100 includes a peripheral region PR and an array region AR. The first stack structure 110a is located on the substrate 100 of the peripheral region PR. The second stack structure 210a is located on the substrate 100 of the array area AR. The first isolation structure 122 is located between the first stacked structures 110a and extends from the top surface of the first stacked structure 110a into the substrate 100. The second isolation structure 222 is located between the second stacked structures 210a, which extends from the top surface of the second stacked structure 210a into the substrate 100.

It is to be noted that the width W1' of the first isolation structure 122 is greater than the width W2' of the second isolation structure 222. In addition, the aspect ratio of the second isolation structure 222 located in the array area AR is greater than the aspect ratio of the first isolation structure 122 of the peripheral area PR. In one embodiment, the width W1' of the first isolation structure 122 may be between 0.2 microns and 8 microns; the width W2' of the second isolation structure 222 may be between 0.01 microns and 0.03 microns. In an embodiment, the aspect ratio (height H1/width W1') of the first isolation structure 122 may be between 0.04 and 2; the aspect ratio (height H2/width W2') of the second isolation structure 222 may be Between 10 and 35.

3 is a flow chart of a method of fabricating a semiconductor memory device in accordance with a second embodiment of the present invention.

Referring to FIG. 3, basically, a method of fabricating a semiconductor memory device according to a second embodiment of the present invention is similar to a method of fabricating a semiconductor memory device according to a second embodiment of the present invention. That is, steps S102, S104, S106, S108, and S110 are the same as steps S002, S004, S006, S008, and S010. The difference between the two is that in step S112, the first isolation material in the first trench is completely removed by using the mask pattern as a mask, so that no first isolation material remains in the first trench. Thereafter, step S114 is performed to form a second isolation material in the first trench. That is, the second insulation material completely fills the first trench. Then, step S116 is performed to perform heat treatment to remove the solvent in the first insulating material (ie, the fluidizable dielectric material) in the second trench to cure the flowable dielectric material.

In summary, the present invention allows the flowable dielectric material to be filled with a high aspect ratio by simultaneously filling the flowable dielectric material into the first trench of the peripheral region and the second trench of the array region. Two ditches. Next, at least a portion of the flowable dielectric material in the first trench is removed. Thereafter, a chemical vapor deposited oxide is formed in the first trench. When the subsequent heat treatment is performed to remove the solvent of the flowable dielectric material, since the area between the flowable dielectric material and the substrate in the first trench has been lowered, the substrate or the isolation structure of the peripheral region is less likely to be misaligned. With cracks. In this way, the isolation structure of the peripheral region and the array region of the present invention has better isolation capability, thereby reducing leakage current of the component, increasing the breakdown voltage of the component, and improving the reliability of the component.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

Claims (9)

A semiconductor memory device comprising: a substrate including a peripheral region and an array region; a plurality of first isolation structures in the substrate of the peripheral region; and a plurality of second isolation structures in the array region In the substrate, wherein each of the first isolation structures comprises a lower structure and an upper structure on the lower structure, a density of the lower structure, a 矽-oxygen bond strength and a density of the second isolation structure, The 矽-oxygen bond strength is the same, the density of the upper structure, the 矽-oxygen bond strength is different from the density of the second isolation structure, the 矽-oxygen bond strength, and the lower structure The top surface has a distance from the highest top surface of the substrate, and a width of each of the first isolation structures is greater than a width of each of the second isolation structures. The semiconductor memory device of claim 1, wherein each of the first isolation structures has a width of between 0.2 micrometers and 8 micrometers, and each of the second isolation structures has a width of between 0.01 micrometers and 0.03 micrometers. between. The semiconductor memory device of claim 1, wherein each of the first isolation structures has an aspect ratio of between 0.04 and 2, and each of the second isolation structures has an aspect ratio of 10 to 35 between. The semiconductor memory device of claim 1, wherein the distance between the top surface of the lower structure and the highest top surface of the substrate is at least greater than 500 Å. A method of fabricating a semiconductor memory device, including Providing a substrate including a peripheral region and an array region; forming a plurality of first stacked structures on the substrate of the peripheral region; forming a plurality of first trenches between the first stacked structures, the first a trench extending from the top surface of the first stacked structure into the substrate; a plurality of second stacked structures formed on the substrate of the array region; and a plurality of layers formed between the second stacked structures a second trench extending from a top surface of the second stack structure into the substrate, wherein a width of the second trench is smaller than a width of the first trench; and the first isolation material is simultaneously filled Forming a mask pattern on the substrate of the array region, the mask pattern exposing a top of the first isolation material in the first trench Removing the at least one portion of the first isolation material in the first trench with the mask pattern as a mask; forming a second isolation material in the first trench, wherein the second isolation Density, 矽-oxygen bond strength and strength of materials The first insulating material has different densities, 矽-oxygen bonding strengths; and heat treatment. The method of manufacturing a semiconductor memory device according to claim 5, wherein the step of removing the at least a portion of the first spacer material in the first trench by using the mask pattern as a mask The method further includes: completely removing the first isolation material in the first trench. The method of fabricating a semiconductor memory device according to claim 5, wherein after removing the at least a portion of the first spacer material in the first trench, the remaining portion of the first spacer material The distance between the top surface and the highest top surface of the substrate is at least greater than 500 Å. The method of fabricating a semiconductor memory device according to claim 5, wherein the first isolation material comprises a flowable dielectric material, and the method for forming the same comprises spin coating dielectric method, flowable chemical vapor deposition Law or a combination thereof. The method for fabricating a semiconductor memory device according to claim 5, wherein the second isolation material comprises a chemical vapor deposited oxide, and the method for forming the same comprises high-density plasma chemical vapor deposition, high aspect ratio filling. Ditch process or a combination thereof.