CN114005789A - 一种屏蔽栅沟槽mosfet的制作方法 - Google Patents

一种屏蔽栅沟槽mosfet的制作方法 Download PDF

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CN114005789A
CN114005789A CN202111267936.7A CN202111267936A CN114005789A CN 114005789 A CN114005789 A CN 114005789A CN 202111267936 A CN202111267936 A CN 202111267936A CN 114005789 A CN114005789 A CN 114005789A
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颜宇
颜妮娜
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Shenzhen Zhongrong Hezhong Technical Service Co ltd
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Abstract

本发明公开了一种屏蔽栅沟槽MOSFET的制作方法,包括在外延层对应元胞区的区域形成第二导电类型的多个第一掺杂区及在外延层对应屏蔽栅连线区的区域形成第二导电类型的第二掺杂区;在外延层的表层之中形成第二导电类型的第三掺杂区,并在外延层对应第一掺杂区的位置形成沟槽,所述沟槽延伸至第一掺杂区的部分区域;在沟槽中淀积多晶硅,并在第三掺杂区之中形成第一导电类型的第四掺杂区,本发明采用第一掺杂区作为屏蔽栅,替代了传统方法中的多晶硅屏蔽栅,因此不需要采用深沟槽工艺,也不需要在狭窄的沟槽之中制作多晶硅层间介质,从而避开了工艺方面难以控制的深沟槽工艺、多晶硅层间介质工艺的质量不稳定和可靠性问题。

Description

一种屏蔽栅沟槽MOSFET的制作方法
技术领域
本发明涉及半导体技术领域,尤其涉及一种屏蔽栅沟槽MOSFET的制作方法。
背景技术
MOSFET芯片是一种分立器件,属于半导体功率器件范畴,与集成电路同属于半导体芯片领域,集成电路是通过工艺方法将成千上万个晶体管整合在同一个芯片中,MOSFET则是由成千上万个相同结构的元胞并列组成的单个晶体管。
MOSFET的关键动态参数包括寄生电容、开关时间、栅极寄生电阻等,其中寄生电容包括栅源寄生电容Cgs、栅漏寄生电容Cgd,漏源寄生电容Cds,从应用角度来看,将MOSFET的寄生电容归纳为输入电容Ciss=Cgs+Cgd,输出电容Coss=Cds+Cdg和反向传输电容Crss=Cdg,其中反向传输电容Crss也叫做米勒电容,输入电容和米勒电容在MOSFET的开关损耗中起主导作用。芯片面积越大,芯片的导通电阻就越小,但寄生电容的面积也就越大,输入电容和米勒电容随之也就越大;在保证既定导通电阻的前提下,最大程度的减小MOSFET的输入电容和米勒电容,是芯片工程师的职责所在。
现有的屏蔽栅沟槽MOSFET制造方法,为了减小MOSFET的输入电容和米勒电容,都需要制作深沟槽,然后在沟槽之中制作两层多晶硅,其中第二层多晶硅为MOSFET的多晶硅栅,第一层多晶硅为屏蔽栅,掩埋在多晶硅栅的下方,屏蔽栅并不作为一个独立的端口引出,而是在芯片内部采用金属连线与源区(源极)相连,屏蔽栅的上方、侧面、下方都被介质层包围,其中位于屏蔽栅上方、多晶硅栅下方的介质层,称之为“多晶硅层间介质”,多晶硅层间介质作为屏蔽栅和多晶硅栅之间的隔离层,防止两者之间漏电。
现实工艺中,制作深沟槽和多晶硅层间介质都有较大的难度,对设备和工艺的依赖度很大,容易出现工艺波动和可靠性问题。
发明内容
本发明提供了屏蔽栅沟槽MOSFET的制作方法,旨在解决现有的为了减小MOSFET的输入电容和米勒电容而无法避免制作深沟槽的问题。
根据本申请实施例,提供了一种屏蔽栅沟槽MOSFET的制作方法,其特征在于,包括以下步骤:在第一导电类型的衬底的表面生长第一导电类型的外延层;在外延层对应元胞区的区域形成第二导电类型的多个第一掺杂区及在外延层对应屏蔽栅连线区的区域形成第二导电类型的第二掺杂区;在外延层的表层之中形成第二导电类型的第三掺杂区,并在外延层对应第一掺杂区的位置形成沟槽,所述沟槽延伸至第一掺杂区的部分区域;在沟槽侧壁及外延层顶部生长氧化层,并激活第一掺杂区、第二掺杂区及第三掺杂区中的掺杂物;在沟槽中淀积多晶硅,并去除沟槽之外的多晶硅,并在第三掺杂区之中形成第一导电类型的第四掺杂区;在氧化层和多晶硅上淀积介质层,并在介质层之中形成第一接触孔、第二接触孔及第三接触孔,并在第一接触孔、第二接触孔及第三接触孔内淀积金属形成第一金属连线,第二金属连线和第三金属连线;所述第一接触孔穿过介质层进入到沟槽之中的多晶硅,所述第二接触孔依次穿过介质层、氧化层进入到第三掺杂区,所述第三接触孔依次穿过介质层、氧化层、第四掺杂区进入第三掺杂区。
优选地,所述外延层的厚度为4-15微米;形成所述第一掺杂区、第二掺杂区的离子注入工艺为多次离子注入,每次离子注入的能量和剂量不同,且所述第一掺杂区、第二掺杂区分布于外延层的设定区域的从表面至预设深度的纵深区域,所述预设深度为外延层的厚度的2/4-3/4。
优选地,形成的所述第一掺杂区及所述第二掺杂区在注入过程中,采用多次能量和剂量递变的离子注入工艺形成第一掺杂区和第二掺杂区。
优选地,所述沟槽的深度为1-2微米,且所述沟槽的宽度大于所述第一掺杂区的宽度。
优选地,所述第三掺杂区的掺杂浓度大于所述第一掺杂区、第二掺杂区的掺杂浓度;所述第三掺杂区的深度为0.6-1.2微米,所述第三掺杂区的下表面与所述第一掺杂区、所述第二掺杂区的顶部高度形成重叠。
优选地,采用高温氧化工艺,在沟槽的侧壁生长氧化层时,在同一个高温氧化工艺下,同步激活第一掺杂区、第二掺杂区及第三掺杂区中的掺杂物;在同一个高温氧化工艺下,第一掺杂区、第二掺杂区、第三掺杂区中的掺杂物发生热扩散;所述高温氧化工艺的温度为950-1100摄氏度,工艺时间为10-60分钟。
优选地,所述第四掺杂区的深度为所述第三掺杂区的深度的1/9-1/3。
优选地,所述第一掺杂区与所述第二掺杂区连接。
与现有技术相比,本发明提供的屏蔽栅沟槽MOSFET的制作方法具有以下有益效果:
1、采用本案之方法制作的屏蔽栅沟槽MOSFET,其第一掺杂区3.1通过第二金属连线11.2、第三金属连线11.3实现与源极同电位,当MOSFET的漏、源之间出现高电压时,第一掺杂区3.1与漏端的外延层2组成的PN结反偏,PN结的耗尽层横向展开,以至于相邻PN结的耗尽层横向连通,根据电荷平衡原理,纵向耐压因此被提升,即提高了MOSFET的漏源击穿电压,或在实现既定击穿电压的情况下可实现更小的单位面积导通电阻。另一方面,采用本发明制造的MOSFET,多晶硅栅的下方主要是第一掺杂区3.1(与源极相连),从而减小了多晶硅栅与漏端之间的MOS电容的面积,即减小了米勒电容。
2、本发明采用第一掺杂区3.1作为MOSFET的屏蔽栅,替代了传统方法中的多晶硅屏蔽栅,第一掺杂区3.1与漏端的外延层2组成大面积的PN结,即增大了漏源寄生电容Cds,在MOSFET反向承受脉冲信号时比传统的屏蔽栅MOSFET有更大的能量吸收能力,从而提高了器件的雪崩电流和浪涌能力。
3、本发明采用第一掺杂区3.1作为MOSFET的屏蔽栅,替代了传统方法中的多晶硅屏蔽栅,因此本发明不需要采用深沟槽工艺、也不需要在狭窄的沟槽之中制作多晶硅层间介质,从而避开了工艺方面难以控制的深沟槽工艺、多晶硅层间介质工艺的质量不稳定和可靠性问题。
4、本发明先形成屏蔽栅和体区,然后形成沟槽:在元胞区,采用沟槽刻蚀工艺将体区分割于各个元胞之中(即分割于相邻沟槽之间的区域),以及采用沟槽刻蚀工艺将元胞区表层的第一掺杂区3.1刻蚀掉,并且始终保证元胞区的沟槽5完全覆盖第一掺杂区3.1(W2>W1),从而实现了导电通道的连续、避免元胞区的第一掺杂区3.1与第三掺杂区4连成一体导致MOSFET无法开启;在屏蔽栅连线区,第二掺杂区3.2与第三掺杂区4连成一体并从表面通过第二接触孔9.2、第二金属连线11.2引出,而在芯片内部第一掺杂区3.1与第二掺杂区3.2是一体的,因此简单而巧妙的实现了屏蔽栅的电性连接。
5、本发明形成的第一掺杂区3.1和第二掺杂区3.2,由能量、剂量递变的多次注入工艺形成,即从表面至预设深度的掺杂浓度是递减的,众所周知,当MOSFET反向承压时,从表面至预设深度的电势是递增的,本发明采用从表面至预设深度的掺杂浓度递减的第一掺杂区3.1和第二掺杂区3.2,能更好的实现各深度位置的电荷平衡,从而提高MOSFET的击穿电压。
6、本发明先形成屏蔽栅和体区,然后形成沟槽和多晶硅栅,且利用高温氧化生长栅氧化层的热预算实现对屏蔽栅、体区掺杂物的激活和微量热扩散,整个工艺过程没有额外的高温退火工艺,从而最大程度的减小了热预算,即最大程度的减少了衬底中的掺杂物质向外延层中的扩散,提高了MOSFET的击穿电压。
附图说明
为了更清楚地说明本发明实施例技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本发明第一实施例提供的屏蔽栅沟槽MOSFET的制作方法的流程图。
图2是在衬底表面生长外延层并形成第一掺杂区及第二掺杂区的结构示意图。
图3是形成第三掺杂区及沟槽的结构示意图。
图4是生长氧化层及淀积多晶硅的结构示意图。
图5是形成第四掺杂区的结构示意图。
图6是形成接触孔的结构示意图。
图7是形成金属连线的结构示意图。
图8是形成接触孔后芯片结构的俯视图。
标号说明:
1、衬底;2、外延层;3.1、第一掺杂区、3.2、第二掺杂区;4、第三掺杂区;5、沟槽;6、氧化层;7、多晶硅;8、第四掺杂区;9.1、第一接触孔;9.2、第二接触孔;9.3、第三接触孔;10、介质层;11.1、第一金属连线;11.2、第二金属连线;11.3、第三金属连线。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
还应当理解,在此本发明说明书中所使用的术语仅仅是出于描述特定实施例的目的而并不意在限制本发明。如在本发明说明书和所附权利要求书中所使用的那样,除非上下文清楚地指明其它情况,否则单数形式的“一”、“一个”及“该”意在包括复数形式。
还应当进一步理解,在本发明说明书和所附权利要求书中使用的术语“和/或”是指相关联列出的项中的一个或多个的任何组合以及所有可能组合,并且包括这些组合。
请结合图1,本发明第一实施例公开了一种屏蔽栅沟槽MOSFET的制作方法,该制作方法具体包括以下步骤:
步骤S1:在第一导电类型的衬底1的表面生长第一导电类型的外延层2。
步骤S2:在外延层2对应元胞区的区域形成第二导电类型的多个第一掺杂区3.1及在外延层2对应屏蔽栅连线区的区域形成第二导电类型的第二掺杂区3.2。具体详见图2。
步骤S3:在外延层2的表层之中形成第二导电类型的第三掺杂区4,并在外延层2对应第一掺杂区3.1的位置形成沟槽5,所述沟槽5延伸至第一掺杂区3.1的部分区域。具体详见图3。
步骤S4:在沟槽5侧壁及外延层2顶部生长氧化层6,并激活第一掺杂区3.1、第二掺杂区3.2及第三掺杂区4中的掺杂物。具体详见图4。
步骤S5:在沟槽5中淀积多晶硅7,并去除沟槽5之外的多晶硅7,并在第三掺杂区4之中形成第一导电类型的第四掺杂区8。具体详见图4-图5。
步骤S6:在氧化层6和多晶硅7上淀积介质层10,并在介质层10之中形成第一接触孔9.1、第二接触孔9.2及第三接触孔9.3,并在第一接触孔9.1、第二接触孔9.2及第三接触孔9.3内淀积金属形成第一金属连线11.1,第二金属连线11.2和第三金属连线11.3。具体详见图6-图7。
所述第一接触孔9.1穿过介质层10进入到沟槽5之中的多晶硅7,所述第二接触孔9.2依次穿过介质层10、氧化层6进入到第三掺杂区4,所述第三接触孔9.3依次穿过介质层10、氧化层6、第四掺杂区8进入第三掺杂区4。
可以理解,在步骤S2中,采用光刻、离子注入工艺形成第一掺杂区3.1及第二掺杂区3.2,第一掺杂区3.1位于MOSFET的元胞区区域中,第二掺杂区3.2位于MOSFET的屏蔽栅连线区的区域中,第一掺杂区3.1的数量为多个,本实施例中,第一掺杂区3.1的数量为2个,且第一掺杂区3.1与第二掺杂区3.2的导电类型相同,例如,当MOSFET为N型MOSFET时,所述第一导电类型为N型,所述第二导电类型为P型,反之也可。
可以理解,在步骤S2中,形成的所述第一掺杂区3.1及所述第二掺杂区3.2在注入过程中,采用多次能量和剂量递变的离子注入工艺形成第一掺杂区和第二掺杂区。具体地,离子注入的次数为2次及以上次数,每次离子注入的能量和剂量不同,当注入能量较大时,注入剂量较小,当注入能量较小时,注入剂量较大,即,由若干次能量和剂量递变的离子注入工艺形成第一掺杂区3.1和第二掺杂区3.2。
可以理解,在步骤S2中,所述外延层2的厚度为4-15微米,所述第一掺杂区3.1、第二掺杂区3.2分布于外延层2的设定区域的从表面至预设深度的纵深区域,所述预设深度为外延层的厚度的2/4-3/4。可选地,作为一种实施例,所述第一掺杂区3.1、第二掺杂区3.2的顶部距离外延层2的上表面0.5-1微米。
可以理解,在步骤S3中,所述第三掺杂区4的掺杂浓度大于所述第一掺杂区3.1、第二掺杂区3.2的掺杂浓度。所述第三掺杂区4的深度为0.6-1.2微米,所述第三掺杂区4的下表面与所述第一掺杂区3.1、所述第二掺杂区3.2的顶部高度形成重叠。
可以理解,在步骤S3中,采用离子注入工艺,在外延层2的表层之中形成第二导电类型的第三掺杂区4,使得第三掺杂区4覆盖部分第一掺杂区3.1及部分第二掺杂区3.2,继续在外延层2的区域形成沟槽5,所述沟槽5与第一掺杂区3.1的位置与数量一一对应,且沟槽5穿过第三掺杂区4与第一掺杂区3.1的部分区域重合,呈叠加状。具体地,所述沟槽5的深度为1-2微米,且所述沟槽5的宽度(如图3中所示的W2尺寸)大于所述第一掺杂区3.1的宽度(如图3中所示的W1尺寸)。第三掺杂区4即为MOSFET的体区。
可以理解,在步骤S4中,采用高温氧化工艺,该高温氧化工艺的温度为950-1100摄氏度,工艺时间为10-60分钟,在沟槽5的侧壁生长氧化层6时,在同一个高温氧化工艺下,同步激活第一掺杂区3.1、第二掺杂区3.2及第三掺杂区4中的掺杂物,同时地,在同一个高温氧化工艺下,第一掺杂区3.1、第二掺杂区3.2及第三掺杂区4中的掺杂物发生热扩散,而热扩散后的第一掺杂区3.1的宽度仍然小于沟槽5的宽度。
可以理解,激活第一掺杂区3.1、第二掺杂区3.2及第三掺杂区4中的掺杂物,使得第一掺杂区3.1、第二掺杂区3.2及第三掺杂区4中的掺杂物,表现出N型或者P型的电特性,而在激活之前,这些掺杂物没有电性表现。
可以理解,在步骤S5中,第四掺杂区8即为MOSFET的源区。
可以理解,在步骤S6中,第一接触孔9.1的数量和位置与第一掺杂区3.1一一对应,且每个第一接触孔9.1穿过介质层10进入到沟槽5内的多晶硅7中,再填充金属形成第一金属连线11.1。而第二接触孔9.2则对应第二掺杂区3.2开设,其穿过介质层10、氧化层6进入到第三掺杂区4中,填充金属形成第二金属连线11.2。第三接触孔9.3依次穿过介质层10、氧化层6、第四掺杂区8进入第三掺杂区4,填充金属形成第三金属连线11.3。
可以理解,在步骤S6中,第二金属连线11.2与第三金属连线11.3采用金属互连,即实现屏蔽栅与源极互连。
至此,MOSFET芯片的主体结构都已经完成,后续关于MOSFET的钝化层和背面处理的工艺过程,对于本领域的技术人员来说属于常规做法,在此不做赘述。其中,MOSFET的背面即衬底1连接MOSFET的漏极,衬底1和外延层2为MOSFET的漏端。
请结合图7和图8,在MOSFET的元胞区(也即第一掺杂区3.1的区域),第四掺杂区8作为MOSFET的源区,第三掺杂区4作为MOSFET的体区,相邻沟槽5之间包含有源区、体区、第三接触孔9.3,所述第三接触孔9.3穿透源区至体区之中,使得源区与体区同电位。元胞区的每一个沟槽5之中填充有多晶硅7作为MOSFET的多晶硅栅,每一个沟槽5的底部覆盖一个第一掺杂区3.1,第一掺杂区3.1作为MOSFET的屏蔽栅,多晶硅7(多晶硅栅)与第一掺杂区3.1(屏蔽栅)之间的氧化层6为二者的隔离层。
而参阅图8可知,在俯视角度下,第二掺杂区3.2和第一掺杂区3.1连接,也即第二掺杂区3.2和第一掺杂区3.1是一体的,元胞区的第一掺杂区3.1因为被覆盖在多晶硅7(多晶硅栅)的下方而无法打线引出,只能在第二掺杂区3.2的区域打孔引出,即,第二掺杂区3.2作为MOSFET的屏蔽栅连线区。在MOSFET的屏蔽栅连线区,第二掺杂区3.2是通过其表层的第三掺杂区4之中的第二接触孔9.2引出的,因为第二掺杂区3.2和第三掺杂区4为同类型的掺杂区(第二导电类型),因此二者同电位,位于第三掺杂区4之中的第二接触孔9.2即实现了第二掺杂区3.2的电信号引出,也即实现了第一掺杂区3.1即屏蔽栅的电信号引出。在图8中,两个虚线框为沟槽5。
本发明制造方法中,第一掺杂区3.1实现屏蔽栅效果的机理是这样的:第一掺杂区3.1通过第二金属连线11.2、第三金属连线11.3实现与源极同电位,当MOSFET的漏、源之间出现高电压时,第一掺杂区3.1与漏端的外延层2组成的PN结反偏,PN结的耗尽层横向展开,以至于相邻PN结的耗尽层横向连通。
在本发明实施例中,第一掺杂区3.1为多个(图示为2个),多个第一掺杂区3.1等间距排列,第一掺杂区3.1对应MOSFET的元胞区,第二掺杂区3.2对应MOSFET的屏蔽栅连线区,氧化层6为MOSFET的栅氧化层,第三掺杂区4为MOSFET的体区,沟槽5之中保留的多晶硅7为MOSFET的多晶硅栅,第四掺杂区8为MOSFET的源区,衬底1连接MOSFET的漏极,衬底1和外延层2为MOSFET的漏端。
与现有技术相比,本发明提供的屏蔽栅沟槽MOSFET的制作方法具有以下有益效果:
1、采用本案之方法制作的屏蔽栅沟槽MOSFET,其第一掺杂区3.1通过第二金属连线11.2、第三金属连线11.3实现与源极同电位,当MOSFET的漏、源之间出现高电压时,第一掺杂区3.1与漏端的外延层2组成的PN结反偏,PN结的耗尽层横向展开,以至于相邻PN结的耗尽层横向连通,根据电荷平衡原理,纵向耐压因此被提升,即提高了MOSFET的漏源击穿电压,或在实现既定击穿电压的情况下可实现更小的单位面积导通电阻。另一方面,采用本发明制造的MOSFET,多晶硅栅的下方主要是第一掺杂区3.1(与源极相连),从而减小了多晶硅栅与漏端之间的MOS电容的面积,即减小了米勒电容。
2、本发明采用第一掺杂区3.1作为MOSFET的屏蔽栅,替代了传统方法中的多晶硅屏蔽栅,第一掺杂区3.1与漏端的外延层2组成大面积的PN结,即增大了漏源寄生电容Cds,在MOSFET反向承受脉冲信号时比传统的屏蔽栅MOSFET有更大的能量吸收能力,从而提高了器件的雪崩电流和浪涌能力。
3、本发明采用第一掺杂区3.1作为MOSFET的屏蔽栅,替代了传统方法中的多晶硅屏蔽栅,因此本发明不需要采用深沟槽工艺,也不需要在狭窄的沟槽之中制作多晶硅层间介质,从而避开了工艺方面难以控制的深沟槽工艺、多晶硅层间介质工艺的质量不稳定和可靠性问题。
4、本发明先形成屏蔽栅和体区,然后形成沟槽:在元胞区,采用沟槽刻蚀工艺将体区分割于各个元胞之中(即分割于相邻沟槽之间的区域),以及采用沟槽刻蚀工艺将元胞区表层的第一掺杂区3.1刻蚀掉,并且始终保证元胞区的沟槽5完全覆盖第一掺杂区3.1(W2>W1),从而实现了导电通道的连续、避免元胞区的第一掺杂区3.1与第三掺杂区4连成一体导致MOSFET无法开启;在屏蔽栅连线区,第二掺杂区3.2与第三掺杂区4连成一体并从表面通过第二接触孔9.2、第二金属连线11.2引出,而在芯片内部第一掺杂区3.1与第二掺杂区3.2是一体的,因此简单而巧妙的实现了屏蔽栅的电性连接。
5、本发明形成的第一掺杂区3.1和第二掺杂区3.2,由能量、剂量递变的多次注入工艺形成,即从表面至预设深度的掺杂浓度是递减的,众所周知,当MOSFET反向承压时,从表面至预设深度的电势是递增的,本发明采用从表面至预设深度的掺杂浓度递减的第一掺杂区3.1和第二掺杂区3.2,能更好的实现各深度位置的电荷平衡,从而提高MOSFET的击穿电压。
6、本发明先形成屏蔽栅和体区,然后形成沟槽和多晶硅栅,且利用高温氧化生长栅氧化层的热预算实现对屏蔽栅、体区掺杂物的激活和微量热扩散,整个工艺过程没有额外的高温退火工艺,从而最大程度的减小了热预算,即最大程度的减少了衬底中的掺杂物质向外延层中的扩散,提高了MOSFET的击穿电压。
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到各种等效的修改或替换,这些修改或替换都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应以权利要求的保护范围为准。

Claims (8)

1.一种屏蔽栅沟槽MOSFET的制作方法,其特征在于,包括以下步骤:
在第一导电类型的衬底的表面生长第一导电类型的外延层;
在外延层对应元胞区的区域形成第二导电类型的多个第一掺杂区及在外延层对应屏蔽栅连线区的区域形成第二导电类型的第二掺杂区;
在外延层的表层之中形成第二导电类型的第三掺杂区,并在外延层对应第一掺杂区的位置形成沟槽,所述沟槽延伸至第一掺杂区的部分区域;
在沟槽侧壁及外延层顶部生长氧化层,并激活第一掺杂区、第二掺杂区及第三掺杂区中的掺杂物;
在沟槽中淀积多晶硅,并去除沟槽之外的多晶硅,并在第三掺杂区之中形成第一导电类型的第四掺杂区;
在氧化层和多晶硅上淀积介质层,并在介质层之中形成第一接触孔、第二接触孔及第三接触孔,并在第一接触孔、第二接触孔及第三接触孔内淀积金属形成第一金属连线,第二金属连线和第三金属连线;
所述第一接触孔穿过介质层进入到沟槽之中的多晶硅,所述第二接触孔依次穿过介质层、氧化层进入到第三掺杂区,所述第三接触孔依次穿过介质层、氧化层、第四掺杂区进入第三掺杂区。
2.根据权利要求1所述的屏蔽栅沟槽MOSFET的制作方法,其特征在于:所述外延层的厚度为4-15微米;
形成所述第一掺杂区、第二掺杂区的离子注入工艺为多次离子注入,每次离子注入的能量和剂量不同,且所述第一掺杂区、第二掺杂区分布于外延层的设定区域的从表面至预设深度的纵深区域,所述预设深度为外延层的厚度的2/4-3/4。
3.根据权利要求2所述的屏蔽栅沟槽MOSFET的制作方法,其特征在于:形成的所述第一掺杂区及所述第二掺杂区在注入过程中,采用多次能量和剂量递变的离子注入工艺形成第一掺杂区和第二掺杂区。
4.根据权利要求1所述的屏蔽栅沟槽MOSFET的制作方法,其特征在于:所述沟槽的深度为1-2微米,且所述沟槽的宽度大于所述第一掺杂区的宽度。
5.根据权利要求1所述的屏蔽栅沟槽MOSFET的制作方法,其特征在于:所述第三掺杂区的掺杂浓度大于所述第一掺杂区、第二掺杂区的掺杂浓度;
所述第三掺杂区的深度为0.6-1.2微米,所述第三掺杂区的下表面与所述第一掺杂区、所述第二掺杂区的顶部高度形成重叠。
6.根据权利要求1所述的屏蔽栅沟槽MOSFET的制作方法,其特征在于:采用高温氧化工艺,在沟槽的侧壁生长氧化层时,在同一个高温氧化工艺下,同步激活第一掺杂区、第二掺杂区及第三掺杂区中的掺杂物;
在同一个高温氧化工艺下,第一掺杂区、第二掺杂区、第三掺杂区中的掺杂物发生热扩散;
所述高温氧化工艺的温度为950-1100摄氏度,工艺时间为10-60分钟。
7.根据权利要求1所述的屏蔽栅沟槽MOSFET的制作方法,其特征在于:所述第四掺杂区的深度为所述第三掺杂区的深度的1/9-1/3。
8.根据权利要求1所述的屏蔽栅沟槽MOSFET的制作方法,其特征在于:所述第一掺杂区与所述第二掺杂区连接。
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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CN117525157B (zh) * 2024-01-08 2024-03-22 通威微电子有限公司 一种双沟道沟槽器件及其制作方法

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