CN114003285A

CN114003285A - Instruction execution method, computing device and storage medium

Info

Publication number: CN114003285A
Application number: CN202111289483.8A
Authority: CN
Inventors: 钟俊; 柏鑫; 江峰; 李明宇; 汪业盛
Original assignee: Wuhan Deepin Technology Co ltd
Current assignee: Wuhan Deepin Technology Co ltd
Priority date: 2021-11-02
Filing date: 2021-11-02
Publication date: 2022-02-01

Abstract

The invention discloses an instruction execution method, a computing device and a storage medium. The method comprises the following steps: submitting a first store instruction applied to store data in an internal memory to a processor; building a data storage section in an internal memory; generating a second storage address for storing data according to the data storage section; generating a second storage instruction according to the second storage address, wherein the second storage instruction is suitable for storing the data to be stored by the first storage instruction, and the processor does not generate a data storage exception message when executing the second storage instruction; storing, by the processor, data in a data storage section of the internal memory executing a second store instruction; generating a second reading instruction according to the first reading instruction; and reading data from the data storage section of the internal memory by executing the second reading instruction by the processor. The invention can prevent the atomicity of data access from losing, thereby avoiding the problem of abnormal operation of some special application programs.

Description

Instruction execution method, computing device and storage medium

Technical Field

The present invention relates to the field of computer instruction execution, and in particular, to an instruction execution method, a computing device, and a storage medium.

Background

With the continuous development of computer technology, more and more applications are developed. Accordingly, more and more data are applied, and the data structure is more and more complex. Therefore, the access performance of the system to the complex data structure in the memory is more and more important, and the running speed of the key application program is directly influenced. When the method is applied to accessing and storing the stored data, the processor does not support special accessing and storing instructions for the data, and the error report condition occurs, so that the processor cannot directly process the accessing and storing instruction operation data.

For this reason, in the prior art, in order to access these storage data, a change data access instruction is adopted, so that the instruction for accessing these data by the application becomes a normal instruction, and the processor can perform the access of the data. One of the schemes is to convert an original interface-crossing memory access instruction into two interface memory access instructions, and complete data can be successfully stored or read by executing the two interface memory access instructions.

This approach, however, translates one memory access into multiple memory accesses, thus substantially changing the memory access model of the application. For some special application scenarios, the atomicity of one memory access is destroyed by multiple memory accesses, and if the application program depends on the atomicity of the memory access, in this case, an error or an error occurs in data due to the destruction of the atomicity, and if the data is serious, the application program may be abnormally operated.

For this reason, a new instruction execution method is required.

Disclosure of Invention

To this end, the present invention provides an instruction execution method in an attempt to solve or at least alleviate the above-presented problems.

According to an aspect of the present invention, there is provided an instruction execution method adapted to be executed in a computing device, the computing device including a processor, an internal memory, and running one or more applications, a storage area of the internal memory being mapped to a storage space, and the applications reading and writing data in the internal memory with storage addresses in the storage space, the method including the steps of: submitting a first store instruction applied to store data in an internal memory to a processor; when the processor cannot normally execute the first storage instruction due to the first storage address of the data stored in the first storage instruction and generates a data storage exception message, constructing a data storage section in the internal memory; generating a second storage address for storing data according to the data storage section; generating a second storage instruction according to the second storage address, wherein the second storage instruction is suitable for storing the data to be stored by the first storage instruction, and the processor does not generate a data storage exception message when executing the second storage instruction; storing, by the processor, data in a data storage section of the internal memory executing a second store instruction; generating a third storage instruction according to the first storage instruction, wherein the third storage instruction is suitable for storing the second storage address, and the processor does not generate a data exception message when executing the third storage instruction; executing, by the processor, a third store instruction to store a second store address at the first store address to generate a second read instruction; when a first reading instruction for reading data in the internal memory is received, and the processor cannot normally execute the first reading instruction due to a first reading address of the data read by the first reading instruction, generating a second reading instruction according to the first reading instruction and a second storage address; and reading data from the data storage section of the internal memory by executing the second reading instruction by the processor.

Optionally, in the method according to the present invention, generating the second storage address for storing data according to the data storage section includes: a second memory address is allocated in the data storage section to store the data.

Optionally, in the method according to the present invention, generating the second store instruction according to the second store address includes: and replacing the first storage address in the first storage instruction with a second storage address to obtain a second storage instruction.

Optionally, in the method according to the present invention, executing the second storing instruction by the memory to store the data in the internal memory includes the steps of: obtaining a second storage address of the storage data according to the second storage instruction; and storing the data to be stored in the second storage address.

Optionally, in the method according to the present invention, generating the third store instruction according to the first store instruction includes: generating a first half-segment storage instruction and a second half-segment storage instruction according to a first storage address of the first storage instruction, wherein the first half-segment storage instruction and the second half-segment storage instruction are respectively suitable for storing data according to a first half-segment address and a half-segment address; and taking the first half storage instruction and the second half storage instruction as third storage instructions.

Optionally, in the method according to the present invention, executing, by the processor, a third store instruction to store a second memory address at the first memory address comprises the steps of: executing, by the processor, a first half of the store instruction of the third store instruction, storing the second store address in the first half of the address.

Optionally, in the method according to the present invention, generating the second read instruction according to the first read instruction and the second memory address includes: generating a first half section reading instruction and a second half section reading instruction according to the storage address of the second reading instruction, wherein the first half section reading instruction and the second half section reading instruction are respectively suitable for reading data according to the first half section address and the second half section address; executing a first half section reading instruction by the processor, reading a first storage address to obtain a second storage address; taking the second storage address as a second reading address; and generating a second read instruction according to the second read address.

Optionally, in the method according to the present invention, generating the second read instruction according to the second read address includes: and replacing the first read address in the first read instruction with a second read address to obtain a second read instruction.

Optionally, in the method according to the present invention, reading, by the processor, data from the data storage section of the internal memory according to the second read instruction includes the steps of: obtaining a second reading address of the reading data according to the second reading instruction; and reading the data needing to be read from the second reading address.

Optionally, in a method according to the invention, the first store instruction comprises a no-to-bound store instruction, and the second store instruction and the third store instruction comprise a to-bound store instruction.

Optionally, in the method according to the present invention, the first read instruction comprises an unbounded read instruction, and the second read instruction comprises an unbounded read instruction.

According to another aspect of the present invention, there is provided a computing device comprising: one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for performing an instruction execution method according to the present invention.

According to yet another aspect of the invention, there is provided a computer readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computing device, cause the computing device to perform a method in an instruction execution method according to the invention.

The instruction execution method in the invention is suitable for being executed in a computing device, the computing device comprises a processor, an internal memory and one or more applications, and the method comprises the following steps: submitting a first storage instruction of storage data applied in an internal memory to a processor, and constructing a data storage section in the internal memory when the processor cannot normally execute the first storage instruction due to the storage address of the data stored in the first storage instruction and generates a data storage exception message; generating a second storage address for storing data according to the data storage section; generating a second storage instruction according to the second storage address, wherein the second storage instruction is suitable for storing the data to be stored by the first storage instruction, and the processor does not generate a data storage exception message when executing the second storage instruction; in order to avoid that the thread of other cores of the processor executes a data reading instruction while storing data, incomplete data is read from a position where data storage is not completed, an application operation is made to be wrong, and therefore a new address is selected to store data. And then executing a second storage instruction by the processor to store data in the data storage section of the internal memory, when receiving a first reading instruction for reading the data in the internal memory and the processor cannot normally execute the first reading instruction due to a first reading address of the data read by the first reading instruction, generating the second reading instruction according to the first reading instruction and the second storage address, and executing the second reading instruction by the processor to read the data from the data storage section of the internal memory. The invention can avoid reading data from the first reading address when the data storage is not finished; the data reading from the second reading address can restrict the memory access model of the application program to be changed so as to cause the edge effect, so that the atomicity of the data access is not lost, the problem of abnormal operation of some special application programs caused by the edge effect is avoided, and the stability of the application program and the compatibility of the whole system are improved.

Drawings

To the accomplishment of the foregoing and related ends, certain illustrative aspects are described herein in connection with the following description and the annexed drawings, which are indicative of various ways in which the principles disclosed herein may be practiced, and all aspects and equivalents thereof are intended to be within the scope of the claimed subject matter. The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description when read in conjunction with the accompanying drawings. Throughout this disclosure, like reference numerals generally refer to like parts or elements.

FIG. 1 illustrates a schematic diagram of a processor and internal memory deployed in a computing device, according to an exemplary embodiment of the invention;

FIG. 2 illustrates a block diagram of a computing device 200, according to an exemplary embodiment of the invention;

FIG. 3 illustrates a flow diagram of an instruction execution method 300 in accordance with an exemplary embodiment of the present invention;

FIG. 4 illustrates a schematic diagram of generating a third store instruction in accordance with an exemplary embodiment of the present invention; and

FIG. 5 illustrates a diagram of breaking instruction atomicity, according to an exemplary embodiment of the invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like reference numerals generally refer to like parts or elements.

FIG. 1 shows a schematic diagram of a processor and internal memory deployed in a computing device according to an example embodiment of the present invention. As shown in FIG. 1, a processor 204 and internal memory 140 are included in the computing device 200. An operating system 220 is also installed in the computing device 200, with applications 110 running on the operating system 220. The invention is not limited as to the particular type of operating system 220. The number of applications shown in fig. 1 is merely exemplary. There is no limit to the number or type of applications running on operating system 220. The internal memory 140 is adapted to store operating system 220 and application 110 operating data, and the processor 204 is adapted to process the operating data.

The specific structure of the computing device 200 in fig. 1 is illustrated in detail by fig. 2. FIG. 2 illustrates a block diagram of a computing device 200, according to an exemplary embodiment of the invention. As shown in FIG. 2, in a basic configuration 202, a computing device 200 typically includes a system memory 206 and one or more processors 204. A memory bus 208 may be used for communication between the processor 204 and the system memory 206.

Depending on the desired configuration, the processor 204 may be any type of processing, including but not limited to: a microprocessor (μ P), a microcontroller (μ C), a Digital Signal Processor (DSP), or any combination thereof. The processor 204 may include one or more levels of cache, such as a level one cache 210 and a level two cache 212, a processor core 214, and registers 216. Example processor cores 214 may include Arithmetic Logic Units (ALUs), Floating Point Units (FPUs), digital signal processing cores (DSP cores), or any combination thereof. The example memory controller 218 may be used with the processor 204, or in some implementations the memory controller 218 may be an internal part of the processor 204.

Depending on the desired configuration, system memory 206 may be any type of memory, including but not limited to: volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.), or any combination thereof. System memory 206 may include an operating system 220, one or more programs 222, and program data 228. In some embodiments, the program 222 may be arranged to execute the instructions 223 of the method 300 according to the invention on an operating system by one or more processors 204 using the program data 228.

Computing device 200 may also include a storage interface bus 234. The storage interface bus 234 enables communication from the storage devices 232 (e.g., removable storage 236 and non-removable storage 238) to the basic configuration 202 via the bus/interface controller 230. Operating system 220, programs 222, and at least a portion of data 224 can be stored on removable storage 236 and/or non-removable storage 238, and loaded into system memory 206 via storage interface bus 234 and executed by one or more processors 204 when computing device 200 is powered on or programs 222 are to be executed.

Computing device 200 may also include an interface bus 240 that facilitates communication from various interface devices (e.g., output devices 242, peripheral interfaces 244, and communication devices 246) to the basic configuration 202 via the bus/interface controller 230. The example output device 242 includes a graphics processing unit 248 and an audio processing unit 250. They may be configured to facilitate communication with various external devices, such as a display or speakers, via one or more a/V ports 252. Example peripheral interfaces 244 can include a serial interface controller 254 and a parallel interface controller 256, which can be configured to facilitate communications with external devices such as input devices (e.g., keyboard, mouse, pen, voice input device, touch input device) or other peripherals (e.g., printer, scanner, etc.) via one or more I/O ports 258. An example communication device 246 may include a network controller 260, which may be arranged to communicate with one or more other computing devices 262 over a network communication link via one or more communication ports 264.

A network communication link may be one example of a communication medium. Communication media may typically be embodied by computer readable instructions, data structures, program modules, and may include any information delivery media, such as carrier waves or other transport mechanisms, in a modulated data signal. A "modulated data signal" may be a signal that has one or more of its data set or its changes made in such a manner as to encode information in the signal. By way of non-limiting example, communication media may include wired media such as a wired network or private-wired network, and various wireless media such as acoustic, Radio Frequency (RF), microwave, Infrared (IR), or other wireless media. The term computer readable media as used herein may include both storage media and communication media.

In the computing device 200 according to the present invention, the program 222 comprises a plurality of program instructions that instruct the instruction execution method 300 to instruct the processor 204 to execute some steps of the instruction execution method 300 in the computing device 200 according to the present invention, so that some parts of the computing device 200 execute the instructions by executing the instruction execution method 300.

Computing device 200 may be implemented as a server, e.g., file server 240, database 250, a server, an application server, etc., which may be a device such as a Personal Digital Assistant (PDA), a wireless web-browsing device, an application-specific device, or a hybrid device that include any of the above functions. May be implemented as a personal computer including both desktop and notebook computer configurations, and in some embodiments computing device 200 is configured to perform instruction execution method 300.

FIG. 3 illustrates a flow diagram of an instruction execution method 300 according to an exemplary embodiment of the invention. The method 300 of executing instructions in the present invention is suitable for execution in a computing device and is further suitable for execution by the operating system 220 shown in FIG. 1. As shown in FIG. 3, the instruction execution method 300 begins at step S310 by committing a first store instruction of the application 110 to the processor 204 that stores data in the internal memory 140. When the application 110 needs to store data in the internal memory 140, a first store instruction to store data needs to be submitted to the processor 204 for execution via the operating system 220. The storage area of the internal memory 140 is mapped to a storage space, and the application 110 stores data in the internal memory 140 at a storage address in the storage space.

Subsequently, step S320 is executed, and when the processor 204 cannot normally execute the first store instruction due to the store address of the data stored by the first store instruction, a data storage section is built in the internal memory.

According to an embodiment of the present invention, when the memory address is not aligned in the internal memory 140, the processor 204 cannot execute the special operation instruction, and generates a data memory exception message. The first store instruction comprises a no-pair store instruction. When the data to be read by the application 110 is stored in the internal memory 140 without being bound, the first operation instruction is a no-bound memory access instruction, and the data storage exception message is a no-bound memory storage exception. The non-alignment means that the initial position of the data stored in the memory is not aligned with the natural boundary of the data of the type stored in the memory sequentially. For example, a 32-bit register, when storing data normally, the register stores a complete 32-bit data, and the first address of the data storage is the first address of the register. However, when the memory is not in the range, the calculator only stores a part of the 32-bit data, the first address of the 32-bit data is offset from the first address of the register, and the first address of the data is at a certain address in the middle of the register. Another portion of the 32-bit data is placed in the next register in a sequential manner. Or a 32-bit register, the processor 204 supports reading 16-bit data at a time, and when the first address of the 16-bit data is in the middle of the 32-bit register, i.e. a 16-bit data cross-store is generated, the processor 204 cannot read the data normally. The processor 204 cannot completely fetch the data from the separately stored 16-bit data according to one instruction, and therefore the processor 204 throws an exception. The non-aligned memory storage exception refers to that the processor 204 throws an exception by directly storing the non-aligned data on the processor 204 which does not support direct storage of the non-aligned data.

FIG. 4 illustrates a schematic diagram of generating a third store instruction in accordance with an exemplary embodiment of the present invention. As shown in fig. 4, when the boundary storage instruction is not converted, the instruction decomposition calculation sequence is executed first, and the first half storage instruction and the second half storage instruction are generated according to the storage address of the first storage instruction, and are respectively adapted to store data according to the first half address and the half address, and finally, the first half storage instruction and the second half storage instruction are used as the second storage instruction. The first half store instruction and the second half store instruction comprise a pair store instruction.

In the above instruction conversion process, since the memory access model of the application 110 is changed, one memory operation is broken into a plurality of operations, which causes an edge effect, and particularly, causes a change in the atomicity of the memory access. When the correctness of the running logic of the application 110 depends on the assumption of atomicity, the application 110 may be abnormally run due to the lack of atomicity.

FIG. 5 illustrates a diagram of breaking instruction atomicity, according to an exemplary embodiment of the invention. As shown in FIG. 5, since the first half access instruction and the second half access instruction are two independent operations, atomicity does not exist, a view gap exists between them, and other views can be inserted. If a thread with other processing cores in its view performs a memory access write operation, the integrity of the data may be destroyed, possibly causing the application 110 to run abnormally.

Therefore, in the invention, the data storage section is constructed in the internal memory, the position of the data storage section in the internal memory is different from the first storage address, and a blank section which does not store data is selected from the internal memory as the data storage section.

Subsequently, step S330 is executed to generate a second storage address for storing data according to the data storage section. Specifically, a second memory address for storing data is allocated in the data storage section. Because the address of the data stored in the operation is not changed, other addresses of the written data are not mixed with the first storage address, and the second storage address corresponding to the first storage address is unique. When it is necessary to write data again in the first memory address, data can be directly written in the second memory address.

Subsequently, step S340 is executed to generate a second storage instruction according to the second storage address, where the second storage instruction is suitable for storing the data to be stored by the first storage instruction, and the processor does not generate a data storage exception message when executing the second storage instruction. Specifically, when the second storage instruction is generated according to the second storage address, the first storage address in the first storage instruction is replaced by the second storage address to obtain the second storage instruction, so that data is stored in the second storage address according to the second storage instruction.

Subsequently, step S350 is executed, the processor executes a second storage instruction to store data in the data storage section of the internal memory, specifically, a second storage address of the storage data is obtained according to the second storage instruction, and the data to be stored is stored in the second storage address. The second store instruction comprises a log store instruction. The second storage address allocated in the internal memory is a bound address, and when the processor stores data according to the second storage instruction, the data can be stored in the bound address at one time without destroying atomicity in the data storage process. Because the processor stores the data in the boundary address at one time, the situation that the data is not completely stored and the data reading is abnormal can not be met when the data is read.

In the data storage process, data calculation is not needed according to the storage address, the calculation resource of the processor is saved, the second storage address is stored, data calculation is not needed when the data is read again, and the data access and storage speed can be improved.

Subsequently, step S360 is executed to generate a third store instruction according to the first store instruction, where the third store instruction is suitable for storing the second store address, and the processor does not generate a data exception message when executing the third store instruction. Specifically, when the third storage instruction is generated, a first half storage instruction and a second half storage instruction are generated according to a first storage address of the first storage instruction, and the first half storage instruction and the second half storage instruction are respectively suitable for storing data according to a first half address and a half address; and taking the first half storage instruction and the second half storage instruction as third storage instructions. The third storage instruction comprises a boundary storage instruction, and the first half storage instruction and the second half storage instruction are boundary storage instructions.

Subsequently, step S370 is executed, the processor executes the third storage instruction to store the second storage address at the first storage address so as to generate a second read instruction; specifically, the first half of the third store instruction is executed by the processor, and the second store address is stored in the first half of the address.

Subsequently, step S380 is executed, when the first read instruction for reading data in the internal memory is received, and the processor cannot normally execute the first read instruction due to the first read address of the data read by the first read instruction, a second read instruction is generated according to the first read instruction and the second storage address. According to one embodiment of the invention, the first read instruction comprises an unbounded read instruction and the second read instruction comprises a unbounded read instruction. The processor throws a data read exception message when executing the first read instruction. When the first read instruction is a non-boundary read instruction, the data read exception message is a non-boundary memory read exception. After the second reading instruction is generated according to the first reading instruction, the processor does not generate data reading abnormal information when executing the second reading instruction.

When a second reading instruction is generated according to the first reading instruction, a first half section reading instruction and a second half section reading instruction are generated according to a storage address of the second reading instruction, the first half section reading instruction and the second half section reading instruction are respectively suitable for reading data according to a first half section address and a second half section address, and a processor cannot generate data reading abnormal messages when executing the first half section reading instruction and the second half section reading instruction. And then executing a first half reading instruction by the processor to read the stored second storage address from the first half address. And then, taking the second storage address as a second reading address, and generating a second reading instruction according to the second reading address. And when a second read instruction is generated according to the second read address, replacing the first read address in the first read instruction with the second read address to obtain the second read instruction.

Subsequently, step S390 is executed, where the processor executes a second read instruction to read data from the data storage section of the internal memory, specifically, a second read address of the read data is obtained according to the second read instruction, and then the data to be read is read from the second read address.

In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that the invention as claimed requires more features than are expressly recited in each claim.

Those skilled in the art will appreciate that the modules or units or groups of devices in the examples disclosed herein may be arranged in a device as described in this embodiment, or alternatively may be located in one or more devices different from the devices in this example. The modules in the foregoing examples may be combined into one module or may be further divided into multiple sub-modules.

Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. Modules or units or groups in embodiments may be combined into one module or unit or group and may furthermore be divided into sub-modules or sub-units or sub-groups. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments.

Furthermore, some of the described embodiments are described herein as a method or combination of method elements that can be performed by a processor of a computer system or by other means of performing the described functions. A processor having the necessary instructions for carrying out the method or method elements thus forms a means for carrying out the method or method elements. Further, the elements of the apparatus embodiments described herein are examples of the following apparatus: the apparatus is used to implement the functions performed by the elements for the purpose of carrying out the invention.

The various techniques described herein may be implemented in connection with hardware or software or, alternatively, with a combination of both. Thus, the methods and apparatus of the present invention, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other machine-readable storage medium, wherein, when the program is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention.

In the case of program code execution on programmable computers, the computing device will generally include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device. Wherein the memory is configured to store program code; the processor is configured to execute the instruction execution method of the present invention according to instructions in the program code stored in the memory.

By way of example, and not limitation, computer readable media may comprise computer storage media and communication media. Computer-readable media includes both computer storage media and communication media. Computer storage media store information such as computer readable instructions, data structures, program modules or other data. Communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. Combinations of any of the above are also included within the scope of computer readable media.

As used herein, unless otherwise specified the use of the ordinal adjectives "first", "second", "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this description, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as described herein. Furthermore, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter. Accordingly, many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the appended claims. The present invention has been disclosed in an illustrative rather than a restrictive sense, and the scope of the present invention is defined by the appended claims.

Claims

1. An instruction execution method adapted to be executed in a computing device, the computing device including a processor, an internal memory, and running one or more applications, a storage area of the internal memory being mapped to a storage space, and the applications reading and writing data in the internal memory at storage addresses in the storage space, the method comprising the steps of:

submitting a first store instruction of the application to the processor that stores data in the internal memory;

when the processor cannot normally execute a first storage instruction due to a first storage address of data stored by the first storage instruction and generates a data storage exception message, constructing a data storage section in the internal memory;

generating a second storage address for storing data according to the data storage section;

generating a second storage instruction according to the second storage address, wherein the second storage instruction is suitable for storing the data to be stored by the first storage instruction, and the processor does not generate a data storage exception message when executing the second storage instruction;

executing, by the processor, the second store instruction to store data in a data storage section of the internal memory;

generating a third store instruction according to the first store instruction, wherein the third store instruction is suitable for storing the second store address, and the processor does not generate a data exception message when executing the third store instruction;

storing, by the processor executing the third store instruction, the second store address at the first store address to generate a second read instruction;

when a first reading instruction for reading data in the internal memory is received, and the processor cannot normally execute the first reading instruction due to a first reading address of the data read by the first reading instruction, generating a second reading instruction according to the first reading instruction and a second storage address;

executing, by the processor, the second read instruction to read data from a data storage section of the internal memory.

2. The method of claim 1, wherein said generating a second memory address for storing data from said data storage segment comprises the steps of:

a second memory address is allocated in the data storage segment to store data.

3. The method of claim 2, wherein said generating a second store instruction from said second store address comprises the steps of:

and replacing the first storage address in the first storage instruction with a second storage address to obtain a second storage instruction.

4. The method of claim 3, wherein said executing said second store instruction by said memory to store data in said internal memory comprises the steps of:

obtaining a second storage address of the storage data according to the second storage instruction;

and storing the data to be stored in the second storage address.

5. The method of claim 4, wherein said generating a third store instruction from said first store instruction comprises the steps of:

generating a first half-segment storage instruction and a second half-segment storage instruction according to a first storage address of the first storage instruction, wherein the first half-segment storage instruction and the second half-segment storage instruction are respectively suitable for storing data according to a first half-segment address and a half-segment address;

and taking the first half storage instruction and the second half storage instruction as a third storage instruction.

6. The method of claim 5, wherein said storing the second memory address at the first memory address by the processor executing the third store instruction comprises:

executing, by the processor, a first half store instruction of the third store instruction, the second store address being stored in a first half address.

7. The method of claim 6, wherein said generating a second read instruction based on said first read instruction and a second memory address comprises the steps of:

generating a first half section reading instruction and a second half section reading instruction according to the storage address of the second reading instruction, wherein the first half section reading instruction and the second half section reading instruction are respectively suitable for reading data according to a first half section address and a second half section address;

executing the first half section reading instruction by the processor to obtain a stored second storage address from a first half section address;

taking the second storage address as a second read address;

and generating a second read instruction according to the second read address.

8. The method of claim 7, wherein said generating a second read instruction from said second read address comprises:

and replacing the first read address in the first read instruction with a second read address to obtain a second read instruction.

9. The method of claim 8, wherein the reading, by the processor, data from the data storage section of the internal memory according to the second read instruction comprises the steps of:

obtaining a second reading address of the reading data according to the second reading instruction;

and reading the data needing to be read from the second reading address.

10. The method of any of claims 1-9, wherein the first store instruction comprises a no-pair store instruction, and the second and third store instructions comprise pair store instructions.

11. The method of any of claims 1-10, wherein the first read instruction comprises a no bound read instruction and the second read instruction comprises a bound read instruction.

12. A computing device, comprising:

one or more processors;

a memory; and

one or more apparatuses comprising instructions for performing the method of any of claims 1-11.

13. A computer readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computing device, cause the computing device to perform the method of any of claims 1-11.