CN114003289A - Application program running method, computing device and storage medium - Google Patents
Application program running method, computing device and storage medium Download PDFInfo
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- CN114003289A CN114003289A CN202111287804.0A CN202111287804A CN114003289A CN 114003289 A CN114003289 A CN 114003289A CN 202111287804 A CN202111287804 A CN 202111287804A CN 114003289 A CN114003289 A CN 114003289A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
Abstract
The invention discloses an application program running method, a computing device and a storage medium, and the method comprises the following steps: acquiring a first instruction stream of an application, wherein the first instruction stream comprises a first memory access instruction, and when a processor executes the first memory access instruction, a data memory access exception message is generated because a storage address of the first memory access instruction cannot normally execute the first memory access instruction; acquiring a second memory access instruction from an instruction storage section of the internal memory, wherein the second memory access instruction is suitable for storing or reading data to be stored or read by the first memory access instruction, and the processor cannot generate data memory access exception information when executing the second memory access instruction; replacing a first memory access instruction in the first instruction stream of the application according to the obtained second memory access instruction to obtain a second instruction stream; and submitting the second instruction stream to the processor, and executing the second instruction stream through the processor to run the application. The invention saves the time for exception handling every time and improves the running efficiency of the application.
Description
Technical Field
The present invention relates to the field of operating systems, and in particular, to an application program running method, a computing device, and a storage medium.
Background
With the continuous development of computer technology, more and more application programs are developed. Accordingly, more and more data are applied, and the data structure is more and more complex. Therefore, the access performance of the system to the complex data structure in the memory is more and more important, and the running speed of the key application program is directly influenced. When the data is accessed, the processor does not support special access instructions for the data, and an error report condition occurs, so that the processor cannot directly process the access instructions to read the data.
In the prior art, in order to enable an application to read data normally, a method of changing a data storage mode is adopted, so that an instruction for accessing the data by the application is changed into a normal instruction, and a processor can read the data.
For this reason, a new application program running method is required.
Disclosure of Invention
To this end, the present invention provides an application program running method in an attempt to solve or at least alleviate the above-existing problems.
According to an aspect of the present invention, there is provided an application program running method, adapted to be executed in a computing device, the computing device including an internal memory and an external memory and running one or more applications, a storage area of the internal memory being mapped to a storage space, and the applications reading and writing data in the internal memory with storage addresses in the storage space, the method including the steps of: acquiring a first instruction stream of an application, wherein the first instruction stream comprises a first memory access instruction, and when a processor executes the first memory access instruction, a data memory access exception message is generated because a storage address of the first memory access instruction cannot normally execute the first memory access instruction; acquiring a second memory access instruction from an instruction storage section of the internal memory, wherein the second memory access instruction is suitable for storing or reading data to be stored or read by the first memory access instruction, and the processor cannot generate data memory access exception information when executing the second memory access instruction; replacing a first memory access instruction in the first instruction stream of the application according to the obtained second memory access instruction to obtain a second instruction stream; and submitting the second instruction stream to the processor, and executing the second instruction stream through the processor to run the application.
Optionally, in the method according to the present invention, the computing device further includes an external memory, and the external memory stores the application file, and the method further includes the steps of: generating an executable file of the application program according to the application file; loading an executable file of an application program into an internal memory; the application is run according to an executable file stored in the internal memory.
Optionally, in the method according to the present invention, the executable file includes a code section, and running the application according to the executable file stored in the internal memory includes the steps of: a first instruction stream of the application is obtained from the code section.
Optionally, in the method according to the present invention, further comprising: when the second access instruction is not stored in the internal memory, submitting a first instruction stream of the application to the processor, wherein the first instruction stream comprises a first access instruction suitable for accessing data in the internal memory; when the processor cannot normally execute the first access instruction due to the storage address of the first access instruction, generating a second access instruction according to data access exception information generated by the processor, and executing the second access instruction by the processor to store or read data in an internal memory; and when the code section of the executable file is loaded, the second access instruction is loaded to the internal memory from the instruction storage section.
Optionally, in the method according to the present invention, replacing, according to the obtained second access instruction, the first access instruction in the first instruction stream of the application, and obtaining the second instruction stream includes: judging whether a second memory access instruction which is not read exists in the instruction storage section; and if the second memory access instruction which is not read exists, reading the second memory access instruction to replace the first memory access instruction in the first instruction stream of the application.
Optionally, in the method according to the present invention, the first memory access instruction includes an unbounded memory access instruction, and the data memory access exception message includes an unbounded data access exception message.
Optionally, in the method according to the present invention, the second access instruction comprises an interface access instruction.
Optionally, in the method according to the present invention, generating the second memory access instruction according to the data memory access exception message generated by the processor includes: generating a first half-segment storage instruction and a second half-segment storage instruction according to the storage address of the first storage instruction, wherein the first half-segment storage instruction and the second half-segment storage instruction are respectively suitable for storing data according to a first half-segment address and a second half-segment address; and taking the first half storage instruction and the second half storage instruction as second storage instructions.
Optionally, in the method according to the present invention, generating the second memory access instruction according to the data memory access exception message generated by the processor includes: calculating a storage address and an offset according to a first target address of a first memory access instruction; generating a second target address according to the storage address and the offset; a second store instruction is generated based on the second target address.
According to another aspect of the present invention, there is provided a computing device comprising: one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for performing an application execution method according to the present invention.
According to a further aspect of the present invention, there is provided a computer readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computing device, cause the computing device to perform a method in an application execution method according to the present invention.
The application program running method in the invention is suitable for being executed in a computing device, the computing device comprises a processor and an internal memory, and runs one or more applications, the storage area of the internal memory is mapped into a storage space, and the applications read and write data in the internal memory by using storage addresses in the storage space, the method comprises the following steps: the method comprises the steps that a first instruction stream of an application is obtained firstly, wherein the first instruction stream comprises a first access instruction, and when a processor executes the first access instruction, the first access instruction cannot be normally executed due to the storage address of the first access instruction, so that data access exception information is generated; then, a second memory access instruction is obtained from an instruction storage section of the internal memory, the second memory access instruction is suitable for storing or reading data to be stored or read by the first memory access instruction, and the processor cannot generate data memory access exception information when executing the second memory access instruction; and then replacing the first memory access instruction in the first instruction stream of the application according to the acquired second memory access instruction to obtain a second instruction stream. Finally, the second instruction stream is submitted to the processor for execution of the application. According to the invention, the second access instruction which does not generate the data access abnormal message is acquired from the internal memory, and the first storage instruction in the instruction stream is replaced, so that the second instruction stream which does not generate the data access abnormal message and can be normally executed by the processor can be obtained, the time for performing the abnormal processing each time is saved, and the operation efficiency of the application is improved.
Drawings
To the accomplishment of the foregoing and related ends, certain illustrative aspects are described herein in connection with the following description and the annexed drawings, which are indicative of various ways in which the principles disclosed herein may be practiced, and all aspects and equivalents thereof are intended to be within the scope of the claimed subject matter. The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description when read in conjunction with the accompanying drawings. Throughout this disclosure, like reference numerals generally refer to like parts or elements.
FIG. 1 illustrates a schematic structure of an external memory and an internal memory according to an exemplary embodiment of the present invention;
FIG. 2 illustrates a block diagram of a computing device 200, according to an exemplary embodiment of the invention;
FIG. 3 illustrates a flowchart of an application execution method 300 according to an exemplary embodiment of the present invention; and
FIG. 4 illustrates a diagram of inserting a second access instruction into a code segment according to an exemplary embodiment of the invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like reference numerals generally refer to like parts or elements.
Fig. 1 illustrates a schematic structure of an external memory and an internal memory according to an exemplary embodiment of the present invention. As shown in FIG. 1, computing device 200 includes internal memory 230 and external memory 210, and runs operating system 220. The present invention is not limited as to the type of operating system 220. One or more applications (not shown) run on the operating system 220. The external memory 210 stores therein an application file 211. The manner in which the application files 211 are stored in the external memory 210 shown in fig. 1 is merely exemplary, and the number of application files stored in the external memory 210 is not limited by the present invention.
The application files 211 can be implemented as application files of any application program, and the invention does not limit the types of the application programs and the types of the application files. According to an embodiment of the present invention, the application file 211 is suitable for being compiled, assembled, linked, etc. by the operating system 220 to obtain an executable file of the application program, and finally loaded into the internal memory 230.
The internal memory 230 allocates a storage space for the executable file when storing the executable file of the application program. The storage space allocated by the internal storage 230 includes a plurality of different memory segments, and the executable file is stored in the internal storage 230 in the form of memory segments. The internal memory 230 divides the memory space into memory sections including a heap section, a stack section, a code section, an initialized data section, and an uninitialized data section. The memory segments are partitioned by the operating system in the internal storage 230 when creating the process. Wherein the code section is adapted to store instructions of the application program.
The specific structure of the computing device 200 in fig. 1 is shown in fig. 2. FIG. 2 illustrates a block diagram of a computing device 200, according to an exemplary embodiment of the invention. As shown in FIG. 2, in a basic configuration 202, a computing device 200 typically includes a system memory 206 and one or more processors 204. A memory bus 208 may be used for communication between the processor 204 and the system memory 206.
Depending on the desired configuration, the processor 204 may be any type of processing, including but not limited to: a microprocessor (μ P), a microcontroller (μ C), a Digital Signal Processor (DSP), or any combination thereof. The processor 204 may include one or more levels of cache, such as a level one cache 210 and a level two cache 212, a processor core 214, and registers 216. Example processor cores 214 may include Arithmetic Logic Units (ALUs), Floating Point Units (FPUs), digital signal processing cores (DSP cores), or any combination thereof. The example memory controller 218 may be used with the processor 204, or in some implementations the memory controller 218 may be an internal part of the processor 204.
Depending on the desired configuration, system memory 206 may be any type of memory, including but not limited to: volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.), or any combination thereof. System memory 206 may include an operating system 220, one or more programs 222, and program data 228. In some embodiments, the program 222 may be arranged to execute the instructions 223 of the method 300 according to the invention on an operating system by one or more processors 204 using the program data 228.
A network communication link may be one example of a communication medium. Communication media may typically be embodied by computer readable instructions, data structures, program modules, and may include any information delivery media, such as carrier waves or other transport mechanisms, in a modulated data signal. A "modulated data signal" may be a signal that has one or more of its data set or its changes made in such a manner as to encode information in the signal. By way of non-limiting example, communication media may include wired media such as a wired network or private-wired network, and various wireless media such as acoustic, Radio Frequency (RF), microwave, Infrared (IR), or other wireless media. The term computer readable media as used herein may include both storage media and communication media.
In a computing device 200 according to the present invention, the program 222 comprises a plurality of program instructions of the application execution method 300 that can instruct the processor 204 to perform some of the steps of the application execution method 300 executed in the computing device 200 of the present invention so that some of the parts in the computing device 200 execute the application by performing the application execution method 300 of the present invention.
Fig. 3 shows a flow diagram of an application execution method 300 according to an exemplary embodiment of the present invention. The application execution method 300 in the present invention is suitable for execution in a computing device and is further suitable for execution in the computing device 100 as shown in fig. 1. The computing device includes a processor (not shown in the figure) and an internal memory 230, and runs one or more applications, a storage area of the internal memory 230 is mapped to a storage space, and the applications read and write data in the internal memory 230 with storage addresses in the storage space. As shown in fig. 3, the instruction executing method 300 starts at step S310, obtaining a first instruction stream of an application, where the first instruction stream includes a first memory access instruction, and when the processor executes the first memory access instruction, generating a data memory access exception message because a storage address of the first memory access instruction cannot normally execute the first memory access instruction. The first access instruction comprises a first access instruction and a first store instruction adapted to read and store data in the internal memory 230, respectively. The first memory access instruction comprises an interface-independent memory access instruction. The first access instruction comprises a no-pair access instruction and the first store instruction comprises a no-pair store instruction. The data access exception message comprises a data access exception message and a data storage exception message. When the first access instruction is a first access instruction, the data access exception message is a data access exception message; and when the first memory access instruction is a first storage instruction, the data memory access exception message is a data memory exception message.
According to an embodiment of the present invention, the computing device further includes an external storage 210, the external storage 210 stores an application file 211, and a first instruction stream of the application is obtained through the following steps:
first, an executable file of an application program is generated from the application file 211. The application files 211 stored in the external memory 210 cannot be preprocessed and cannot be directly loaded into the internal memory 230. According to an embodiment of the present invention, the application file 211 needs to be compiled, assembled and linked by the operating system 130 to obtain an executable file of the application program. The present invention is not limited to the steps or methods of the operating system 130 pre-processing the application files 211.
Then, the executable file of the application program is loaded into the internal memory 230. Specifically, storage information stored in the internal memory 230 by the application is determined according to an executable file of the application, and the storage information includes section information of the heap section, the stack section, the code section, the initialized data section, and the uninitialized data section allocated in the internal memory 230. The first storage information is determined according to file information of the application executable file, and the section information is divided in the internal memory 230 according to the first storage information.
When the storage information stored in the internal memory 230 of the application program is determined based on the executable file of the application program, the section size and the alignment information of each section allocated in the internal memory 230 are determined based on the executable file. Specifically, the size of each section is determined according to the amount of data in the executable file; the application alignment stored in the internal memory 230 of the executable file is then determined as alignment information according to the fetch of the processor. The alignment information indicates from which alignment boundary the start address of each data segment should start (e.g., 2, 4, 8, 32 byte alignment, etc.), and determines the start position of each data segment, particularly the way the processor fetches the instructions. The segment size and alignment information then generates segment information for the data segment, the segment information including the segment size and alignment information.
Then, storage information is generated from the segment information, and the segment information of each data segment is used as the storage information. Each data section includes a heap section, a stack section, a code section, an initialized data section, and an uninitialized data section.
The application is then run according to the executable file stored in the internal memory 230. And when the application is run, obtaining a first instruction stream of the application according to the code section.
Subsequently, step S320 is executed to obtain a second access instruction from the instruction storage section of the internal memory 230, where the second access instruction is suitable for storing or reading the data to be stored or read by the first access instruction, and the processor does not generate a data access exception message when executing the second access instruction. The second access instruction comprises a second access instruction and a second store instruction, respectively, adapted to read or store data in the internal memory 230. The second memory access instruction comprises an interface memory access instruction. The second access instruction comprises a paradise access instruction and the second store instruction comprises a paradise store instruction.
According to an embodiment of the invention, when the second access instruction is not stored in the internal memory 230, a first instruction stream of the application is submitted to the processor, the first instruction stream comprising the first access instruction adapted to access data in the internal memory 230. The internal memory 230 stores the second access instruction, that is, when the application is operated for the first time, the first access instruction is not converted into the second access instruction. When the application is executed for the first time, a first instruction stream of the application is obtained according to the code section.
And when the processor cannot normally execute the first memory access instruction due to the storage address of the first memory access instruction, generating a second memory access instruction according to the data memory access exception message generated by the processor. When the first access instruction is a first access instruction, converting the first access instruction into a second access instruction; and when the first memory access instruction is a first storage instruction, converting the first memory access instruction into a second memory access instruction.
When data is stored in the internal memory 230 in a special case, the processor 150 cannot execute the special operation instruction, and generates a data access exception message. According to an embodiment of the present invention, when the data to be read by the application 110 is stored in the internal storage 230 without a boundary, the first operation instruction is a boundary-free memory access instruction, and the data access exception message is a boundary-free memory access exception. The non-alignment means that the initial position of the data stored in the memory is not aligned with the natural boundary of the data of the type stored in the memory sequentially. For example, a 32-bit register, when storing data normally, the register stores a complete 32-bit data, and the first address of the data storage is the first address of the register. However, when the memory is not in the range, the calculator only stores a part of the 32-bit data, the first address of the 32-bit data is offset from the first address of the register, and the first address of the data is at a certain address in the middle of the register. Another portion of the 32-bit data is placed in the next register in a sequential manner. The non-boundary memory access exception means that on the processor 150 which does not support direct access to non-boundary data, direct access to non-boundary data will cause the processor 150 to throw an exception. The processor 150 cannot completely fetch the 32-bit data stored in the memory according to one instruction, and therefore the processor 150 throws an exception and issues a data access exception message.
According to an embodiment of the present invention, when the second memory access instruction is generated according to the data memory access exception message generated by the processor, the address and the offset may be specifically calculated according to the first target address of the first memory access instruction, the second target address is generated according to the address and the offset, and finally the second memory instruction is generated according to the second target address.
According to one embodiment of the invention, the first memory access instruction is load Ra.32, disp1(Rb1.32), and the first memory access instruction is an instruction for loading a 32-bit integer with a first target address of Rb1+ disp1 into the register Ra. Where Rb1 represents the first address of register Rb and disp1 is the offset of a 32-bit integer at the first address of register Rb.
In order to fetch 32-bit data divided in two consecutive registers, it is necessary to double the number of bits of the first operation instruction, i.e., to operate every two consecutive 32-bit registers in the internal memory 230 as a whole. For example: the 0 th 32-bit register and the 1 st 32-bit register are treated as one 64-bit register to operate, and the subsequent registers are analogized in turn.
When calculating the second target address of the second memory access instruction, the address of the original register Rb, i.e., the memory address, is calculated according to the merging condition. The original register Rb is the ith register, when i is an odd number, the original register Rb and the next register are merged to be a whole to obtain the merged register Rb, and the address Rb1 of the original register Rb is still the address Rb2 of the merged register Rb. When i is an even number, the original register Rb and the previous register are merged to be regarded as a whole to obtain a merged register Rb, and the storage address of the original register Rb plus the operation bit number, namely Rb1+32, is used as the address Rb2 of the merged register Rb.
When calculating the offset amount of the second operation instruction, the offset amount is calculated using the following equation:
disp2＝(Rb1+disp1)-(Rb1+disp1)％64
the second target address Rb2+ disp2 is generated according to the memory address and the offset.
And then generating a second access instruction according to a second target address: load ra.64, disp2(rb2.32), the second access instruction represents reading a 32-bit integer with the second target address Rb2+ disp2 from a register aligned with 64 bits into the register Ra. The second access instruction is then executed by the processor to store or read data in the internal memory 230, and the processor executing the second access instruction does not throw a data access exception.
According to an embodiment of the present invention, when the second access instruction is generated according to the data access exception message generated by the processor, a first half storage instruction and a second half storage instruction may be further generated according to a storage address of the first storage instruction, where the first half storage instruction and the second half storage instruction are respectively adapted to store data according to the first half address and the half address, and then the first half storage instruction and the second half storage instruction are used as the second storage instruction. When data is read, executing a first half section reading instruction through a processor, and reading the stored first half section data according to a first half section address; executing the second half section instruction through the processor, and reading the stored second half section data according to the second half section address; and then combining the first half data read from the first half address with the second half data read from the second half address to obtain data. When the first half section data and the second half section data are combined and sorted, the obtained first half section data and the obtained second half section data are subjected to logic bit operations such as shifting, AND and/or and the like according to the data structures of the first half section data and the second half section data, and required data are intercepted from data obtained by the interface access instruction and aligned.
Finally, an instruction storage section is provided in the code section of the executable file of the application, the second access instruction is stored in the instruction storage section so as to run the application, and when the code section of the executable file is loaded, the second access instruction is loaded from the instruction storage section to the internal memory 230. FIG. 4 illustrates a diagram of inserting a second access instruction into a code segment according to an exemplary embodiment of the invention.
As shown in fig. 4, an instruction storage section is inserted into the code section 413 to obtain a code section 423, and the code section 423 includes an instruction storage section 424 for storing the second access instruction.
Currently, after an application is compiled into a binary, there is no way to change its behavior unless its source code is modified and recompiled. However, in some application scenarios, we cannot modify the source code of the application, and other technical means are needed to change the behavior of the application. Although the instruction sequence of the application program can be modified during running, since the binary file of the application program itself is not modified, the instruction sequence needs to be modified again to ensure that the newly added function is unchanged during the next running of the application program.
Moreover, when the application is run each time, the non-boundary access exception generated by the application instruction stream needs to be processed, and the non-boundary access instruction is converted into a boundary access instruction, so that the computer resource is consumed. Therefore, the invention makes the instruction sequence dynamically modified during operation persistent, and the next time the application program operates again, the instruction code does not need to be modified again, thereby reducing the overall overhead of the system.
Subsequently, step S330 is executed, and the first access instruction in the first instruction stream of the application is replaced according to the obtained second access instruction, so as to obtain a second instruction stream. And replacing the corresponding first memory access instruction in the first instruction stream every time one second memory access instruction is acquired.
According to an embodiment of the invention, after each time of replacement, whether an unread second access instruction exists in the instruction storage section is judged, and if the unread second access instruction exists, the second access instruction is read to replace the first access instruction in the first instruction stream of the application. Therefore, all the first memory access instructions of the applied first instruction stream are replaced, and after all the first memory access instructions are replaced by the second memory access instructions, a second instruction stream comprising a plurality of second memory access instructions is obtained.
Finally, step S340 is executed to submit the second instruction stream to the processor, and execute the second instruction stream through the processor to run the application. The processor executing the second instruction flow does not generate data access exception.
The application program running method in the invention is suitable for being executed in a computing device, the computing device comprises a processor and an internal memory, and runs one or more applications, the storage area of the internal memory is mapped into a storage space, and the applications read and write data in the internal memory by using storage addresses in the storage space, the method comprises the following steps: the method comprises the steps that a first instruction stream of an application is obtained firstly, wherein the first instruction stream comprises a first access instruction, and when a processor executes the first access instruction, the first access instruction cannot be normally executed due to the storage address of the first access instruction, so that data access exception information is generated; then, a second memory access instruction is obtained from an instruction storage section of the internal memory, the second memory access instruction is suitable for storing or reading data to be stored or read by the first memory access instruction, and the processor cannot generate data memory access exception information when executing the second memory access instruction; and then replacing the first memory access instruction in the first instruction stream of the application according to the acquired second memory access instruction to obtain a second instruction stream. Finally, the second instruction stream is submitted to the processor for execution of the application. According to the invention, the second access instruction which does not generate the data access abnormal message is acquired from the internal memory, and the first storage instruction in the instruction stream is replaced, so that the second instruction stream which does not generate the data access abnormal message and can be normally executed by the processor can be obtained, the time for performing the abnormal processing each time is saved, and the operation efficiency of the application is improved.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that the invention as claimed requires more features than are expressly recited in each claim.
Those skilled in the art will appreciate that the modules or units or groups of devices in the examples disclosed herein may be arranged in a device as described in this embodiment, or alternatively may be located in one or more devices different from the devices in this example. The modules in the foregoing examples may be combined into one module or may be further divided into multiple sub-modules.
Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. Modules or units or groups in embodiments may be combined into one module or unit or group and may furthermore be divided into sub-modules or sub-units or sub-groups. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments.
Furthermore, some of the described embodiments are described herein as a method or combination of method elements that can be performed by a processor of a computer system or by other means of performing the described functions. A processor having the necessary instructions for carrying out the method or method elements thus forms a means for carrying out the method or method elements. Further, the elements of the apparatus embodiments described herein are examples of the following apparatus: the apparatus is used to implement the functions performed by the elements for the purpose of carrying out the invention.
The various techniques described herein may be implemented in connection with hardware or software or, alternatively, with a combination of both. Thus, the methods and apparatus of the present invention, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other machine-readable storage medium, wherein, when the program is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention.
In the case of program code execution on programmable computers, the computing device will generally include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device. Wherein the memory is configured to store program code; the processor is configured to execute the application execution method of the present invention according to instructions in the program code stored in the memory.
By way of example, and not limitation, computer readable media may comprise computer storage media and communication media. Computer-readable media includes both computer storage media and communication media. Computer storage media store information such as computer readable instructions, data structures, program modules or other data. Communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. Combinations of any of the above are also included within the scope of computer readable media.
As used herein, unless otherwise specified the use of the ordinal adjectives "first", "second", "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.
While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this description, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as described herein. Furthermore, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter. Accordingly, many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the appended claims. The present invention has been disclosed in an illustrative rather than a restrictive sense, and the scope of the present invention is defined by the appended claims.
Claims (11)
1. An application program running method, adapted to be executed in a computing device, the computing device including a processor and an internal memory and running one or more applications, a storage area of the internal memory being mapped to a storage space, and the applications reading and writing data in the internal memory at storage addresses in the storage space, the method comprising the steps of:
acquiring a first instruction stream of the application, wherein the first instruction stream comprises a first memory access instruction, and when the processor executes the first memory access instruction, because a storage address of the first memory access instruction cannot normally execute the first memory access instruction, generating a data memory access exception message;
acquiring a second memory access instruction from an instruction storage section of the internal memory, wherein the second memory access instruction is suitable for storing or reading data to be stored or read by the first memory access instruction, and the processor cannot generate data memory access exception information when executing the second memory access instruction;
replacing a first memory access instruction in the first instruction stream of the application according to the obtained second memory access instruction to obtain a second instruction stream;
and submitting the second instruction stream to the processor, and executing the second instruction stream through the processor to run the application.
2. The method of claim 1, wherein the computing device further comprises an external memory, the external memory having application files stored therein, the method further comprising the steps of:
generating an executable file of an application program according to the application file;
loading an executable file of the application program into the internal memory;
and running the application according to the executable file stored in the internal memory.
3. The method of claim 2, wherein the executable file comprises a code section, and the running the application according to the executable file stored in the internal memory comprises the steps of:
obtaining a first instruction stream of the application according to the code section.
4. The method of any one of claims 1-3, wherein the method further comprises:
when the internal memory does not store a second memory access instruction, submitting a first instruction stream of the application to the processor, wherein the first instruction stream comprises a first memory access instruction suitable for accessing data in the internal memory;
when the processor can not normally execute the first access instruction due to the storage address of the first access instruction, generating a second access instruction according to the data access exception message generated by the processor,
executing, by the processor, the second access instruction to store or read data in the internal memory;
setting an instruction storage section in a code section of an executable file of the application, storing the second memory access instruction in the instruction storage section so as to run the application, and loading the second memory access instruction to the internal memory from the instruction storage section when the code section of the executable file is loaded.
5. The method as claimed in claim 4, wherein said replacing a first memory access instruction in a first instruction stream of the application according to the obtained second memory access instruction to obtain a second instruction stream comprises:
judging whether a second memory access instruction which is not read exists in the instruction storage section;
and if the second memory access instruction which is not read exists, reading the second memory access instruction to replace the first memory access instruction in the first instruction stream of the application.
6. The method of any one of claims 1-5, wherein the first memory access instruction comprises a do not interface memory access instruction, and the data memory access exception message comprises a do not interface data access exception message.
7. The method of claim 6, wherein the second memory access instruction comprises an interface memory access instruction.
8. The method as claimed in claim 7, wherein said generating a second access instruction according to a data access exception message generated by said processor comprises the steps of:
generating a first half-segment storage instruction and a second half-segment storage instruction according to the storage address of the first storage instruction, wherein the first half-segment storage instruction and the second half-segment storage instruction are respectively suitable for storing data according to a first half-segment address and a half-segment address;
and taking the first half storage instruction and the second half storage instruction as second storage instructions.
9. The method as claimed in claim 7, wherein said generating a second access instruction according to a data access exception message generated by said processor comprises the steps of:
calculating a storage address and an offset according to a first target address of the first memory access instruction;
generating a second target address according to the storage address and the offset;
and generating a second storage instruction according to the second target address.
10. A computing device, comprising:
one or more processors;
a memory; and
one or more apparatuses comprising instructions for performing the method of any of claims 1-9.
11. A computer readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computing device, cause the computing device to perform the method of any of claims 1-9.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113821273A (en) * | 2021-09-23 | 2021-12-21 | 武汉深之度科技有限公司 | Application program running method, computing device and storage medium |
| CN117193861A (en) * | 2023-11-07 | 2023-12-08 | 芯来智融半导体科技(上海)有限公司 | Instruction processing method, apparatus, computer device and storage medium |
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2021
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113821273A (en) * | 2021-09-23 | 2021-12-21 | 武汉深之度科技有限公司 | Application program running method, computing device and storage medium |
| CN113821273B (en) * | 2021-09-23 | 2023-10-13 | 武汉深之度科技有限公司 | Application program running method, computing device and storage medium |
| CN117193861A (en) * | 2023-11-07 | 2023-12-08 | 芯来智融半导体科技(上海)有限公司 | Instruction processing method, apparatus, computer device and storage medium |
| CN117193861B (en) * | 2023-11-07 | 2024-03-15 | 芯来智融半导体科技(上海)有限公司 | Instruction processing method, apparatus, computer device and storage medium |
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