CN113849345A

CN113849345A - Instruction execution method and device, computing equipment and storage medium

Info

Publication number: CN113849345A
Application number: CN202111117063.1A
Authority: CN
Inventors: 钟俊
Original assignee: Wuhan Deepin Technology Co ltd
Current assignee: Wuhan Deepin Technology Co ltd
Priority date: 2021-09-23
Filing date: 2021-09-23
Publication date: 2021-12-28

Abstract

The invention discloses an instruction execution method, an instruction execution device, a computing device and a storage medium, and the method comprises the following steps: submitting a first operation instruction of an application accessing data in an internal memory to a processor; when the processor generates a data access exception message, generating a first data block according to the data access exception message; determining an instruction replacement strategy of the data abnormal access message according to the first data block; generating a second operation instruction according to the instruction replacement policy, wherein the second operation instruction is suitable for accessing the data to be accessed by the first operation instruction, and the processor does not generate a data access exception message when executing the second operation instruction; and replacing the first operation instruction with the generated second operation instruction, and submitting the second operation instruction to the processor to access the data in the internal memory. The invention can convert the non-boundary access instruction into the butt joint access instruction when the data storage is not boundary-boundary and the processor cannot normally execute the non-boundary access instruction, so that the processor can normally read the data.

Description

Instruction execution method and device, computing equipment and storage medium

Technical Field

The present invention relates to the field of operating systems, and in particular, to an instruction execution method, an instruction execution apparatus, a computing device, and a storage medium.

Background

With the continuous development of computer technology, more and more applications are developed. Accordingly, more and more data are applied, and the data structure is more and more complex. Therefore, the access performance of the system to the complex data structure in the memory is more and more important, and the running speed of the key application program is directly influenced. When the data is accessed, the processor does not support special access instructions for the data, and an error report condition occurs, so that the processor cannot directly process the access instructions to read the data.

Therefore, in the prior art, in order to enable an application to read data normally, a method of changing a data storage mode is adopted, so that an instruction for accessing the data by the application becomes a normal instruction, and a processor can perform data reading.

To this end, a new instruction execution method and apparatus are needed.

Disclosure of Invention

To this end, the present invention provides an instruction execution method in an attempt to solve or at least alleviate the above-presented problems.

According to an aspect of the present invention, there is provided an instruction execution method adapted to be executed in a computing device, the computing device including a processor and an internal memory and running one or more applications, a storage area of the internal memory being mapped to a storage space, and the applications accessing data in the internal memory at storage addresses in the storage space, the method including the steps of: submitting a first operation instruction of an application accessing data in an internal memory to a processor; when the processor generates a data access exception message due to the storage address of the data accessed by the first operation instruction, generating a first data block according to the data access exception message; determining an instruction replacement strategy of the data abnormal access message according to the first data block; generating a second operation instruction according to the instruction replacement policy, wherein the second operation instruction is suitable for accessing the data to be accessed by the first operation instruction, and the processor does not generate a data access exception message when executing the second operation instruction; and replacing the first operation instruction with the generated second operation instruction, and submitting the second operation instruction to the processor to access the data in the internal memory.

Optionally, in the method according to the present invention, the data access exception message includes an instruction address and an exception type of the first operation instruction, and generating the first data block according to the data access exception message includes: a first data block is generated according to the instruction address and the exception type.

Optionally, in a method according to the present invention, an instruction replacement policy table is stored in the computing device, and determining an instruction replacement policy of the data exception access message according to the first data block includes: and inquiring the instruction replacement policy table according to the exception type in the first data block, and determining the instruction replacement policy.

Optionally, in the method according to the present invention, further comprising the step of: and generating a second data block according to the first data block and the instruction replacement strategy.

Optionally, in the method according to the present invention, when the first operation instruction is a no access to bound instruction, the exception type is a no access to bound exception, and the generating of the second operation instruction by the instruction replacement policy includes: replacing the first target address of the first operation instruction with a second target address according to an instruction replacement policy in the second data block; and generating a second operation instruction according to the second target address.

Optionally, in the method according to the present invention, the instruction replacement policy is to replace the non-bound access instruction with a bound access instruction, and the second operation instruction is a bound access instruction.

Optionally, in the method according to the present invention, replacing the first target address of the first operation instruction with the second target address according to the instruction replacement policy in the second data block includes the steps of: calculating a storage address and an offset according to the first target address; and generating a second target address according to the storage address and the offset.

Optionally, in the method according to the present invention, replacing the first operation instruction with the generated second operation instruction includes the steps of: pulling the instruction stream where the first operation instruction is located; and replacing the first operation instruction in the instruction stream with the second operation instruction according to the instruction address in the second data block.

According to another aspect of the present invention, there is provided an instruction execution apparatus, the apparatus residing in a computing device, the computing device including a processor and an internal memory and running one or more applications, a storage area of the internal memory being mapped to a storage space, and the applications accessing data in the internal memory at storage addresses in the storage space, the apparatus comprising: the exception capture module is suitable for generating a first data block according to a data access exception message when a first operation instruction for accessing data in the internal memory by an application is submitted to the processor and the processor generates the data access exception message due to a storage address of the data accessed by the first operation instruction; the replacement policy module is suitable for determining an instruction replacement policy of the data exception access message according to the first data block; the instruction generating module is suitable for generating a second operation instruction according to the instruction replacement policy, the second operation instruction is suitable for accessing the data to be accessed by the first operation instruction, and the processor does not generate data access exception information when executing the second operation instruction; and the instruction replacing module is suitable for replacing the first operation instruction with the generated second operation instruction and submitting the second operation instruction to the processor so as to access the data in the internal memory.

According to yet another aspect of the present invention, there is provided a computing device comprising: one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for performing an instruction execution method according to the present invention.

According to a further aspect of the invention, there is provided a computer readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computing device, cause the computing device to perform a method in an instruction execution method according to the invention.

The instruction execution method in the invention is suitable for being executed in a computing device, the computing device comprises a processor and an internal memory and runs one or more applications, a storage area of the internal memory is mapped into a storage space, and the applications access data in the internal memory by storage addresses in the storage space, and the method comprises the following steps: the method comprises the steps that a first operation instruction for accessing data in an internal memory by an application is submitted to a processor, and when the processor generates a data access abnormal message due to a storage address of the data accessed by the first operation instruction, a first data block is generated according to the data access abnormal message, so that the condition that the operation instruction for executing the application by the processor is abnormal is captured, and the executed abnormal instruction is processed in time. And determining an instruction replacement policy of data abnormal access according to the first data block, and generating a second operation instruction according to the instruction replacement policy, so that the first operation instruction which cannot be normally executed by the processor is converted into the second operation instruction, the second operation instruction is suitable for accessing data to be accessed by the first operation instruction, and the processor does not generate a data access abnormal message when executing the second operation instruction. And finally, replacing the first operation instruction with the generated second operation instruction, so that the processor executes the second operation instruction and successfully accesses the data in the internal memory.

And further, when the first operation instruction is a no-boundary access instruction, the exception type is no-boundary access exception, when a second operation instruction is generated according to the instruction replacement policy, a first target address of the first operation instruction is replaced by a second target address, and the second operation instruction is generated according to the second target address. The instruction replacement strategy is to replace the non-boundary access instruction with a boundary access instruction, and the second operation instruction is a boundary access instruction. According to the steps, when the data storage is not in the boundary alignment and the processor cannot normally execute the non-boundary-alignment access instruction, the non-boundary-alignment access instruction is converted into the docking access instruction, so that the processor can normally read the data.

Drawings

To the accomplishment of the foregoing and related ends, certain illustrative aspects are described herein in connection with the following description and the annexed drawings, which are indicative of various ways in which the principles disclosed herein may be practiced, and all aspects and equivalents thereof are intended to be within the scope of the claimed subject matter. The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description when read in conjunction with the accompanying drawings. Throughout this disclosure, like reference numerals generally refer to like parts or elements.

FIG. 1 is a block diagram of an instruction execution apparatus according to an exemplary embodiment of the present invention;

FIG. 2 illustrates a block diagram of a computing device 200, according to an exemplary embodiment of the invention; and

FIG. 3 illustrates a flow diagram of an instruction execution method 300 according to an exemplary embodiment of the invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like reference numerals generally refer to like parts or elements.

Fig. 1 is a schematic structural diagram of an instruction execution apparatus according to an exemplary embodiment of the present invention. As shown in fig. 1, instruction execution apparatus 140 resides in a computing device (not shown) that includes a processor 150, an internal memory 160, and an operating system 120. One or more applications may be installed on operating system 120. The applications 110 shown in FIG. 1 are exemplary only, and the present invention is not limited to the type or number of applications installed by the operating system 120.

As shown in fig. 1, the processor 150 and the internal memory 160 are implemented as hardware layers of a computing device. The hardware layer has an operating system 120 running thereon, and the operating system 120 is implemented as a system layer of the computing device, which runs in a kernel state (kernel space). Operating system 120 includes kernel 130. Instruction execution device 140 resides in core 130. All modules of instruction execution device 140 operate in kernel mode.

The application 110 running on the operating system 120 runs in a user state (user space). When the application 110 needs to read data in the internal memory 160, a first operation instruction for reading the data needs to be submitted to the processor 150 via the kernel 130 of the operating system 120 for execution. The memory area of the internal memory is mapped to a memory space, and the application 110 accesses data in the internal memory at a memory address in the memory space.

As shown in FIG. 1, processor 150 includes instruction fetch unit 151, decode unit 152, execution unit 153, and memory unit 154. The instruction fetching component 151 is responsible for receiving a first operation instruction of the application 110 that accesses data in the internal memory 160. The decoding unit 152 compiles the first operation instruction to obtain a compiled first operation instruction, the execution unit 153 executes the compiled first operation instruction, and the access unit 154 sends out a data access exception message when the first operation instruction cannot be executed.

The instruction execution apparatus 140 includes an exception capture module 141, a policy replacement module 142, an instruction generation module 143, and an instruction replacement module 144. The exception capture module 141 is capable of capturing a data access exception message generated by the processor 150 and generating a first data block based on the data access exception message.

The exception capture module 141 generates a first data block based on the instruction address and the exception type. The first data block comprises an instruction address and an exception type, and the instruction address and the exception type are packaged to facilitate processing of data access exception messages.

The replacement policy module 142 stores therein an instruction replacement policy table, which is written in advance by a developer and stored in the replacement policy module 142. The permutation policy table includes an exception type and a permutation policy. Each exception type corresponds to a replacement policy. The replacement policy module 142 queries the instruction replacement policy table according to the exception type in the first data block, and determines an instruction replacement policy of the data exception access message. The replacement policy includes whether to replace the instruction and what kind of replacement to do. The exception type of the permutation strategy table comprises a no-access-to-bound exception, and the corresponding permutation strategy is to replace a no-access-to-bound instruction with an access-to-bound instruction. Replacing a not to world access instruction as a to world access instruction specifies that the instruction is to be replaced and that the not to world access instruction is to be replaced as a to world access instruction.

The replacement policy module 142 also generates a second data block according to the first data block and the instruction replacement policy. The instruction generating module 143 generates the second operation instruction according to the instruction replacement policy in the second data block. The second operation instruction is suitable for accessing the data to be accessed by the first operation instruction, and the processor does not generate a data access exception message when executing the second operation instruction.

When the instruction generating module 143 replaces the first target address of the first operation instruction with the second target address according to the instruction replacement policy, the instruction replacement policy is to replace the non-boundary access instruction with a boundary access instruction, and the second operation instruction is a boundary access instruction. The second operation instruction is logically equivalent to the first operation instruction.

The instruction replacement module 140 replaces the first operation instruction with the generated second operation instruction, and submits the second operation instruction to the processor 150 according to the second operation instruction, so that the application 110 accesses the internal memory data. When the instruction replacement module 140 replaces the first operation instruction with the generated second operation instruction, the first operation instruction in the instruction stream is replaced with the second operation instruction according to the instruction address in the second data block. The instruction address is an address of the first operation instruction in the instruction stream, and after the first operation instruction is replaced by a second operation instruction in the form of a pair instruction according to the instruction address, the processor 150 can read data according to the second operation instruction.

The instruction execution apparatus 140 of fig. 1 resides in a computing device. FIG. 2 illustrates a block diagram of a computing device 200, according to an exemplary embodiment of the invention. As shown in FIG. 2, in a basic configuration 202, a computing device 200 typically includes a system memory 206 and one or more processors 204. A memory bus 208 may be used for communication between the processor 204 and the system memory 206.

Depending on the desired configuration, the processor 204 may be any type of processing, including but not limited to: a microprocessor (μ P), a microcontroller (μ C), a Digital Signal Processor (DSP), or any combination thereof. The processor 204 may include one or more levels of cache, such as a level one cache 210 and a level two cache 212, a processor core 214, and registers 216. Example processor cores 214 may include Arithmetic Logic Units (ALUs), Floating Point Units (FPUs), digital signal processing cores (DSP cores), or any combination thereof. The example memory controller 218 may be used with the processor 204, or in some implementations the memory controller 218 may be an internal part of the processor 204.

Depending on the desired configuration, system memory 206 may be any type of memory, including but not limited to: volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.), or any combination thereof. System memory 206 may include an operating system 220, one or more programs 222, and program data 228. In some embodiments, the program 222 may be arranged to execute the instructions 223 of the method 300 according to the invention on an operating system by one or more processors 204 using the program data 228.

Computing device 200 may also include a storage interface bus 234. The storage interface bus 234 enables communication from the storage devices 232 (e.g., removable storage 236 and non-removable storage 238) to the basic configuration 202 via the bus/interface controller 230. Operating system 220, programs 222, and at least a portion of data 224 can be stored on removable storage 236 and/or non-removable storage 238, and loaded into system memory 206 via storage interface bus 234 and executed by one or more processors 204 when computing device 200 is powered on or programs 222 are to be executed.

Computing device 200 may also include an interface bus 240 that facilitates communication from various interface devices (e.g., output devices 242, peripheral interfaces 244, and communication devices 246) to the basic configuration 202 via the bus/interface controller 230. The example output device 242 includes a graphics processing unit 248 and an audio processing unit 250. They may be configured to facilitate communication with various external devices, such as a display or speakers, via one or more a/V ports 252. Example peripheral interfaces 244 can include a serial interface controller 254 and a parallel interface controller 256, which can be configured to facilitate communications with external devices such as input devices (e.g., keyboard, mouse, pen, voice input device, touch input device) or other peripherals (e.g., printer, scanner, etc.) via one or more I/O ports 258. An example communication device 246 may include a network controller 260, which may be arranged to communicate with one or more other computing devices 262 over a network communication link via one or more communication ports 264.

A network communication link may be one example of a communication medium. Communication media may typically be embodied by computer readable instructions, data structures, program modules, and may include any information delivery media, such as carrier waves or other transport mechanisms, in a modulated data signal. A "modulated data signal" may be a signal that has one or more of its data set or its changes made in such a manner as to encode information in the signal. By way of non-limiting example, communication media may include wired media such as a wired network or private-wired network, and various wireless media such as acoustic, Radio Frequency (RF), microwave, Infrared (IR), or other wireless media. The term computer readable media as used herein may include both storage media and communication media.

In the computing device 200 according to the present invention, the program 222 comprises a plurality of program instructions that instruct the execution method 300 to instruct the processor 204 to perform some steps of the instruction execution method 300 executed in the computing device 200 according to the present invention, so that some parts of the computing device 200 implement the data processing by executing the instruction execution method 300 according to the present invention.

Computing device 200 may be implemented as a server, e.g., file server 240, database 250, a server, an application server, etc., which may be a device such as a Personal Digital Assistant (PDA), a wireless web-browsing device, an application-specific device, or a hybrid device that include any of the above functions. May be implemented as a personal computer including both desktop and notebook computer configurations, and in some embodiments computing device 200 is configured to perform instruction execution method 300.

FIG. 3 illustrates a flow diagram of an instruction execution method 300 according to an exemplary embodiment of the invention. The instruction execution method 300 of the present invention is suitable for execution in a computing device and is further suitable for execution in the core 130 shown in FIG. 1. As shown in fig. 3, the instruction execution method 300 begins with step S310, submitting a first operation instruction of the application 110 accessing data of the internal memory to the processor 150. When the application 110 needs to read data in the internal memory 160, a first operation instruction for reading the data needs to be submitted to the processor 150 via the kernel 130 of the operating system 120 for execution. The memory area of the internal memory is mapped to a memory space, and the application 110 accesses data in the internal memory at a memory address in the memory space.

When data is stored in the internal memory 160 in a special case, the processor 150 cannot execute the special operation instruction, and generates a data access exception message. According to an embodiment of the present invention, when the data to be read by the application 110 is stored in the internal storage 160 without a boundary, the first operation instruction is a boundary-free memory access instruction, and the data access exception message is a boundary-free memory access exception. The non-alignment means that the initial position of the data stored in the memory is not aligned with the natural boundary of the data of the type stored in the memory sequentially. For example, a 32-bit register, when storing data normally, the register stores a complete 32-bit data, and the first address of the data storage is the first address of the register. However, when the memory is not in the range, the calculator only stores a part of the 32-bit data, the first address of the 32-bit data is offset from the first address of the register, and the first address of the data is at a certain address in the middle of the register. Another portion of the 32-bit data is placed in the next register in a sequential manner. The non-boundary memory access exception means that on the processor 150 which does not support direct access to non-boundary data, direct access to non-boundary data will cause the processor 150 to throw an exception. The processor 150 cannot completely fetch the 32-bit data that is deposited in accordance with one instruction, and therefore the processor 150 throws an exception.

Processor 150 includes instruction fetch unit 151, decode unit 152, execution unit 153, and memory unit 154. The instruction fetching component 151 is responsible for receiving a first operation instruction of the application 110 that accesses data in the internal memory 160. The decoding unit 152 compiles the first operation instruction to obtain a compiled first operation instruction, the execution unit 153 executes the compiled first operation instruction, and the access unit 154 sends out a data access exception message when the first operation instruction cannot be executed.

The data access exception message includes an instruction address of the first operation instruction and an exception type. The application 110 generates a series of operational instructions during operation that are assembled to form an instruction stream. The first operation instruction is an operation instruction in the instruction stream of the application 110, and the instruction address of the first operation instruction is the position of the first operation instruction in the instruction stream. The exception type is which exception the processor 150 belongs to when it cannot normally execute the first operation instruction. According to one embodiment of the invention, the exception type includes a no access to world exception. And when the first operation instruction is a no-access-to-boundary instruction, the corresponding exception type is a no-access-to-boundary exception.

Subsequently, step S320 is executed, and when the processor 150 generates a data access exception message due to the storage address of the data accessed by the first operation instruction, a first data block is generated according to the data access exception message. The first data block includes an instruction address and an exception type, captures a data access exception message generated by the processor 150, and packages the instruction address and the exception type when generating the first data block according to the data access exception message, so as to facilitate processing of the data access exception message.

Subsequently, step S330 is executed to determine an instruction replacement policy of the data exception access message according to the first data block. The computing device also stores an instruction replacement policy table, and the instruction replacement policy table is written in advance by a developer and stored in the computing device. The permutation policy table includes an exception type and a permutation policy. Each exception type corresponds to a replacement policy. And inquiring the instruction replacement policy table according to the exception type in the first data block, determining the instruction replacement policy of the data exception access message, and generating a second data block according to the first data block and the instruction replacement policy. The replacement policy includes whether to replace the instruction and what kind of replacement to do. The exception type of the permutation strategy table comprises a no-access-to-bound exception, and the corresponding permutation strategy is to replace a no-access-to-bound instruction with an access-to-bound instruction. Replacing a not to world access instruction as a to world access instruction specifies that the instruction is to be replaced and that the not to world access instruction is to be replaced as a to world access instruction.

Subsequently, step S340 is executed to generate a second operation instruction according to the instruction replacement policy, where the second operation instruction is suitable for accessing the data to be accessed by the first operation instruction, and the processor does not generate a data access exception message when executing the second operation instruction. And when a second operation instruction is generated according to the instruction replacement strategy, calculating a storage address and an offset according to the first target address, and generating a second target address according to the storage address and the offset. According to one embodiment of the invention, when the first operation instruction is a no-boundary access instruction and the exception type is a no-boundary access exception, the first target address of the first operation instruction is replaced by the second target address according to the instruction replacement policy when the second operation instruction is generated, and the second operation instruction is generated according to the second target address. The first target address and the second target address are both addresses in the memory space of data that the application 110 wants to read. But the addresses where the data is stored in the first target address form are not aligned and the addresses where the data is stored in the second target address form are aligned.

When the first target address of the first operation instruction is replaced by the second target address according to the instruction replacement strategy, the instruction replacement strategy is to replace the non-boundary access instruction by a boundary access instruction, and the second operation instruction is a boundary access instruction. The second operation instruction is logically equivalent to the first operation instruction.

And when the first target address of the first operation instruction is replaced by the second target address, calculating a storage address and an offset according to the first target address, and generating the second target address according to the storage address and the offset.

According to one embodiment of the invention, the first operation instruction is load ra.32, disp1(rb1.32), and the first operation instruction is an instruction to load a 32-bit integer with a first target address Rb1+ disp1 into the register Ra. Where Rb1 represents the first address of register Rb and disp1 is the offset of a 32-bit integer at the first address of register Rb.

In order to fetch 32-bit data divided in two consecutive registers, it is necessary to double the number of bits of the first operation instruction, i.e., to operate every two consecutive 32-bit registers in the internal memory 160 as a whole. For example: the 0 th 32-bit register and the 1 st 32-bit register are treated as one 64-bit register to operate, and the subsequent registers are analogized in turn.

When calculating the storage address of the second operation instruction, the address of the original register Rb is calculated according to the merge condition. The original register Rb is the ith register, when i is an odd number, the original register Rb and the next register are merged to be a whole to obtain the merged register Rb, and the address Rb1 of the original register Rb is still the address Rb2 of the merged register Rb. When i is an even number, the original register Rb and the previous register are merged to be regarded as a whole to obtain a merged register Rb, and the address of the original register Rb is added with the operation digit, namely Rb1+32 is used as the address Rb2 of the merged register Rb.

When calculating the offset amount of the second operation instruction, the offset amount is calculated using the following equation:

disp2＝(Rb1+disp1)-(Rb1+disp1)％64

the second target address Rb2+ disp2 is generated according to the memory address and the offset.

And generating a second operation instruction according to the second target address: load ra.64, disp2(rb2.32), and the second operation instruction indicates reading a 32-bit integer having a second target address Rb2+ disp2 from a register aligned with 64 bits into the register Ra.

Finally, step S350 is executed to replace the first operation instruction with the generated second operation instruction, and submit the second operation instruction to the processor 150 to access the data in the internal memory. And when the first operation instruction is replaced by the generated second operation instruction, replacing the first operation instruction in the instruction stream by the second operation instruction according to the instruction address in the second data block. The instruction address is an address of the first operation instruction in the instruction stream, and after the first operation instruction is replaced by a second operation instruction in the form of a pair instruction according to the instruction address, the processor 150 can read data according to the second operation instruction.

Subsequently, the processor 150 processes the instruction stream again, the instruction fetching unit 151 receives the second operation instruction, the decoding unit 152 compiles the second operation instruction to obtain a compiled second operation instruction, the execution unit 153 executes the compiled second operation instruction, and the access unit 154 returns the read data to the application 110 via the kernel 130.

A8, the method of A7, wherein replacing the first operation instruction with the generated second operation instruction comprises the steps of:

pulling the instruction stream where the first operation instruction is located;

and replacing the first operation instruction in the instruction stream with a second operation instruction according to the instruction address in the second data block.

In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that the invention as claimed requires more features than are expressly recited in each claim.

Those skilled in the art will appreciate that the modules or units or groups of devices in the examples disclosed herein may be arranged in a device as described in this embodiment, or alternatively may be located in one or more devices different from the devices in this example. The modules in the foregoing examples may be combined into one module or may be further divided into multiple sub-modules.

Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. Modules or units or groups in embodiments may be combined into one module or unit or group and may furthermore be divided into sub-modules or sub-units or sub-groups. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments.

Furthermore, some of the described embodiments are described herein as a method or combination of method elements that can be performed by a processor of a computer system or by other means of performing the described functions. A processor having the necessary instructions for carrying out the method or method elements thus forms a means for carrying out the method or method elements. Further, the elements of the apparatus embodiments described herein are examples of the following apparatus: the apparatus is used to implement the functions performed by the elements for the purpose of carrying out the invention.

The various techniques described herein may be implemented in connection with hardware or software or, alternatively, with a combination of both. Thus, the methods and apparatus of the present invention, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other machine-readable storage medium, wherein, when the program is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention.

In the case of program code execution on programmable computers, the computing device will generally include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device. Wherein the memory is configured to store program code; the processor is configured to execute the method for determining the apparatus shutdown state of the present invention according to instructions in the program code stored in the memory.

By way of example, and not limitation, computer readable media may comprise computer storage media and communication media. Computer-readable media includes both computer storage media and communication media. Computer storage media store information such as computer readable instructions, data structures, program modules or other data. Communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. Combinations of any of the above are also included within the scope of computer readable media.

As used herein, unless otherwise specified the use of the ordinal adjectives "first", "second", "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this description, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as described herein. Furthermore, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter. Accordingly, many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the appended claims. The present invention has been disclosed in an illustrative rather than a restrictive sense, and the scope of the present invention is defined by the appended claims.

Claims

1. An instruction execution method adapted to be executed in a computing device comprising a processor and an internal memory and running one or more applications, a storage area of the internal memory being mapped to a storage space, and the applications accessing data in the internal memory at storage addresses in the storage space, the method comprising the steps of:

submitting to the processor a first operation instruction for the application to access data in the internal memory;

when the processor generates a data access exception message due to the storage address of the data accessed by the first operation instruction, generating a first data block according to the data access exception message;

determining an instruction replacement strategy of the data exception access message according to the first data block;

generating a second operation instruction according to the instruction replacement policy, wherein the second operation instruction is suitable for accessing the data to be accessed by the first operation instruction, and the processor does not generate a data access exception message when executing the second operation instruction; and

replacing the first operation instruction with the generated second operation instruction, and submitting the second operation instruction to the processor to access the data in the internal memory.

2. The method of claim 1, wherein the data access exception message includes an instruction address and an exception type of a first operation instruction, the generating a first data block from the data access exception message comprising the steps of:

and generating the first data block according to the instruction address and the exception type.

3. The method of claim 2, wherein the computing device has stored therein an instruction permutation policy table, the determining the instruction permutation policy for the data exception access message from the first data block comprising the steps of:

and querying the instruction replacement policy table according to the exception type in the first data block, and determining the instruction replacement policy.

4. The method of any one of claims 1-3, further comprising the step of:

and generating a second data block according to the first data block and the instruction replacement strategy.

5. The method of claim 4, wherein when the first operation instruction is a do not access to bounds instruction, the exception type is a do not access to bounds exception, and the generating a second operation instruction according to an instruction replacement policy comprises:

replacing a first target address of the first operation instruction with a second target address according to an instruction replacement policy in the second data block;

and generating a second operation instruction according to the second target address.

6. The method of claim 5, wherein the instruction replacement policy is to replace a not to world access instruction with a to world access instruction, the second operation instruction being a to world access instruction.

7. The method of claim 6, wherein said permuting the first target address of the first operation instruction to the second target address according to the instruction permutation policy in the second data block comprises the steps of:

calculating a storage address and an offset according to the first target address;

and generating a second target address according to the storage address and the offset.

8. An instruction execution apparatus, the apparatus residing in a computing device, the computing device including a processor and an internal memory and running one or more applications, a storage area of the internal memory being mapped to a storage space, and the applications accessing data in the internal memory at storage addresses in the storage space, the apparatus comprising:

an exception capture module adapted to generate a first data block from a data access exception message when a first operation instruction for the application to access data in the internal memory is submitted to the processor, the processor generating the data access exception message due to a storage address of the data accessed by the first operation instruction;

a replacement policy module adapted to determine an instruction replacement policy for the data exception access message from the first data block;

the instruction generating module is suitable for generating a second operation instruction according to the instruction replacement policy, the second operation instruction is suitable for accessing the data to be accessed by the first operation instruction, and the processor does not generate a data access exception message when executing the second operation instruction; and

and the instruction replacing module is suitable for replacing the first operation instruction with the generated second operation instruction and submitting the second operation instruction to the processor so as to access the data in the internal memory.

9. A computing device, comprising:

one or more processors;

a memory; and

one or more apparatuses comprising instructions for performing the method of any of claims 1-7.

10. A computer readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computing device, cause the computing device to perform the method of any of claims 1-7.