CN114003284A

CN114003284A - Instruction execution method based on read-write lock, computing device and storage medium

Info

Publication number: CN114003284A
Application number: CN202111289057.4A
Authority: CN
Inventors: 钟俊; 柏鑫; 江峰; 李明宇; 罗攀登
Original assignee: Wuhan Deepin Technology Co ltd
Current assignee: Wuhan Deepin Technology Co ltd
Priority date: 2021-11-02
Filing date: 2021-11-02
Publication date: 2022-02-01

Abstract

The invention discloses an instruction execution method based on a read-write lock, a computing device and a storage medium. The method comprises the following steps: submitting a first store instruction applied to store data in an internal memory to a processor; when the processor can not normally execute the first storage instruction, generating a second storage instruction according to the data storage exception message; acquiring a write lock, and locking the process of executing the storage instruction; storing, by the processor, data in the internal memory executing a second store instruction; when a first reading instruction for reading data in an internal memory is received, acquiring a reading lock; if the write lock is occupied and the read lock cannot be acquired, acquiring the read lock again; if the read lock is acquired, locking the process of executing the read instruction; data is read from the internal memory by the processor executing a first read instruction. The invention can prevent the atomicity of data access from losing, thereby avoiding the problem of abnormal operation of some special application programs.

Description

Instruction execution method based on read-write lock, computing device and storage medium

Technical Field

The present invention relates to the field of computer instruction execution, and in particular, to an instruction execution method based on a read/write lock, a computing device, and a storage medium.

Background

With the continuous development of computer technology, more and more applications are developed. Accordingly, more and more data are applied, and the data structure is more and more complex. Therefore, the access performance of the system to the complex data structure in the memory is more and more important, and the running speed of the key application program is directly influenced. When the method is applied to accessing and storing the stored data, the processor does not support special accessing and storing instructions for the data, and the error report condition occurs, so that the processor cannot directly process the accessing and storing instruction operation data.

For this reason, in the prior art, in order to access these storage data, a change data access instruction is adopted, so that the instruction for accessing these data by the application becomes a normal instruction, and the processor can perform the access of the data. One of the schemes is to convert an original interface-crossing memory access instruction into two interface memory access instructions, and complete data can be successfully stored or read by executing the two interface memory access instructions.

This approach, however, translates one memory access into multiple memory accesses, thus substantially changing the memory access model of the application. For some special application scenarios, the atomicity of one memory access is destroyed by multiple memory accesses, and if the application program depends on the atomicity of the memory access, in this case, an error or an error occurs in data due to the destruction of the atomicity, and if the data is serious, the application program may be abnormally operated.

For this reason, a new instruction execution method based on read-write lock is needed.

Disclosure of Invention

To this end, the present invention provides a read-write lock based instruction execution method in an attempt to solve or at least alleviate the above-presented problems.

According to an aspect of the present invention, there is provided a method for executing an instruction based on a read-write lock, the method being suitable for being executed in a computing device, the computing device including a processor, an internal memory, and running one or more applications, a storage area of the internal memory being mapped to a storage space, and the applications reading and writing data in the internal memory with storage addresses in the storage space, the method including the steps of: submitting a first store instruction applied to store data in an internal memory to a processor; when the processor cannot normally execute the first storage instruction due to the storage address of the data stored in the first storage instruction, generating a second storage instruction according to the data storage exception message generated by the processor, wherein the second storage instruction is suitable for storing the data to be stored in the first storage instruction, and the processor cannot generate the data storage exception message when executing the second storage instruction; acquiring a write lock, and locking the process of executing the storage instruction; storing, by the processor, data in the internal memory executing a second store instruction; when a first reading instruction for reading data in an internal memory is received, a read lock, a write lock and a read lock are mutually exclusive, and when locking is carried out according to the write lock or the read lock, the data cannot be stored and read at the same address; if the write lock is occupied and the read lock cannot be acquired, acquiring the read lock again; if the read lock is acquired, locking the process of executing the read instruction; data is read from the internal memory by the processor executing a first read instruction.

Optionally, in the method according to the present invention, generating the second storage instruction according to the data storage exception message generated by the processor includes the steps of: generating a first half-segment storage instruction and a second half-segment storage instruction according to the storage address of the first storage instruction, wherein the first half-segment storage instruction and the second half-segment storage instruction are respectively suitable for storing data according to a first half-segment address and a second half-segment address; and taking the first half storage instruction and the second half storage instruction as second storage instructions.

Optionally, in the method according to the present invention, further comprising the step of: if the read lock is occupied and the write lock cannot be acquired, acquiring the write lock again; and if the write lock is acquired, storing the data through a second storage instruction.

Optionally, in the method according to the present invention, executing the second storing instruction by the memory to store the data in the internal memory includes the steps of: generating first half data and second half data according to the data; executing a first half segment storage instruction through a processor, and storing first half segment data according to a first half segment address; and executing the second half storage instruction through the processor, and storing the second half data according to the second half address.

Optionally, in the method according to the present invention, further comprising the step of: and after the data is stored in the internal memory through the processor, releasing the write lock so that other threads of the processor can acquire the read lock and read the data.

Optionally, in the method according to the present invention, the first read instruction includes a first half read instruction and a second half read instruction, and reading data by the first read instruction includes: executing a first half section reading instruction through a processor, and reading stored first half section data according to a first half section address; executing a second half-segment reading instruction through the processor, and reading stored second half-segment data according to a second half-segment address; and combining the first half data read from the first half address with the second half data read from the second half address to obtain data.

Optionally, in the method according to the present invention, further comprising the step of: and releasing the read lock after the processor finishes reading the data in the internal memory so that other threads of the processor can acquire the write lock and store the data.

Optionally, in the method according to the present invention, further comprising the step of: if a second reading instruction is received, submitting the second reading instruction to the processor; when the processor cannot normally execute the second reading instruction due to the address of the data read by the second reading instruction, the first reading instruction is generated according to the data access exception message generated by the processor, the first reading instruction is suitable for reading the data to be read by the second reading instruction, and the processor cannot generate the data reading exception message when executing the first reading instruction.

Optionally, in the method according to the present invention, generating the first read instruction according to the data access exception message generated by the processor includes the steps of: generating a first half section reading instruction and a second half section reading instruction according to the storage address of the second reading instruction, wherein the first half section reading instruction and the second half section reading instruction are respectively suitable for reading data according to the first half section address and the second half section address; and taking the first half read instruction and the second half read instruction as the first read instruction.

Optionally, in the method according to the present invention, the first store instruction comprises a no-pair store instruction, and the first half store instruction and the second half store instruction comprise a pair store instruction.

Optionally, in the method according to the present invention, the second read instruction comprises a no read to bounds instruction, and the first half read instruction and the second half read instruction comprise a read to bounds instruction.

According to another aspect of the present invention, there is provided a computing device comprising: one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for performing a read-write lock based instruction execution method according to the present invention.

According to yet another aspect of the present invention, there is provided a computer readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computing device, cause the computing device to perform a method in a read-write lock based instruction execution method according to the present invention.

The instruction execution method based on the read-write lock is suitable for being executed in a computing device, the computing device comprises a processor and an internal memory, and one or more applications run on the computing device, and the instruction execution method comprises the following steps: the method comprises the steps of submitting a first storage instruction of storage data applied in an internal memory to a processor, and generating a second storage instruction according to a data storage exception message generated by the processor when the processor cannot normally execute the first storage instruction due to a storage address of the data stored by the first storage instruction, wherein the second storage instruction is suitable for storing the data to be stored by the first storage instruction, and the processor cannot generate the data storage exception message when executing the second storage instruction. In order to avoid that the threads of other cores of the processor execute data reading instructions while storing data, read incomplete data from a position where data storage is not completed yet and cause an application to run wrongly, a write lock needs to be acquired first, and the process of executing the storage instructions needs to be locked. The processor then executes a second store instruction to store the data in the internal memory. When a first reading instruction for reading data in an internal memory is received, a reading lock, a writing lock and a reading lock are mutually exclusive, and when locking is carried out according to the writing lock or the reading lock, the data cannot be stored and read at the same address. And if the write lock is occupied and the read lock cannot be acquired, acquiring the read lock again. The write lock is occupied and cannot acquire the read lock, which indicates that the current storage position is storing data, and at the moment, the read data can damage the integrity of the data, and the wrong data is read, so that the data cannot be read. And if the read lock is acquired, locking the process of executing the read instruction, and executing the first read instruction through the processor to read data from the internal memory. If the write lock is acquired, the data is read through the first read instruction, the data storage is finished at the moment, and the data can be read normally. The invention can restrict the memory access model of the application program from being changed to further cause the edge effect, so that the atomicity of data access and memory is not lost, thereby avoiding the problem of abnormal operation of some special application programs caused by the edge effect, and further improving the stability of the application program and the compatibility of the whole system.

Drawings

To the accomplishment of the foregoing and related ends, certain illustrative aspects are described herein in connection with the following description and the annexed drawings, which are indicative of various ways in which the principles disclosed herein may be practiced, and all aspects and equivalents thereof are intended to be within the scope of the claimed subject matter. The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description when read in conjunction with the accompanying drawings. Throughout this disclosure, like reference numerals generally refer to like parts or elements.

FIG. 1 illustrates a schematic diagram of a processor and internal memory deployed in a computing device, according to an exemplary embodiment of the invention;

FIG. 2 illustrates a block diagram of a computing device 200, according to an exemplary embodiment of the invention;

FIG. 3 illustrates a flowchart of a method 300 for instruction execution based on a read-write lock, according to an exemplary embodiment of the invention;

FIG. 4 illustrates a schematic diagram of generating a second store instruction in accordance with an exemplary embodiment of the present invention; and

FIG. 5 illustrates a diagram of breaking instruction atomicity, according to an exemplary embodiment of the invention.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like reference numerals generally refer to like parts or elements.

FIG. 1 shows a schematic diagram of a processor and internal memory deployed in a computing device according to an example embodiment of the present invention. As shown in FIG. 1, a processor 204 and internal memory 140 are included in the computing device 200. An operating system 220 is also installed in the computing device 200, with applications 110 running on the operating system 220. The invention is not limited as to the particular type of operating system 220. The number of applications shown in fig. 1 is merely exemplary. There is no limit to the number or type of applications running on operating system 220. The internal memory 140 is adapted to store operating system 220 and application 110 operating data, and the processor 204 is adapted to process the operating data.

The specific structure of the computing device 200 in fig. 1 is illustrated in detail by fig. 2. FIG. 2 illustrates a block diagram of a computing device 200, according to an exemplary embodiment of the invention. As shown in FIG. 2, in a basic configuration 202, a computing device 200 typically includes a system memory 206 and one or more processors 204. A memory bus 208 may be used for communication between the processor 204 and the system memory 206.

Depending on the desired configuration, the processor 204 may be any type of processing, including but not limited to: a microprocessor (μ P), a microcontroller (μ C), a Digital Signal Processor (DSP), or any combination thereof. The processor 204 may include one or more levels of cache, such as a level one cache 210 and a level two cache 212, a processor core 214, and registers 216. Example processor cores 214 may include Arithmetic Logic Units (ALUs), Floating Point Units (FPUs), digital signal processing cores (DSP cores), or any combination thereof. The example memory controller 218 may be used with the processor 204, or in some implementations the memory controller 218 may be an internal part of the processor 204.

Depending on the desired configuration, system memory 206 may be any type of memory, including but not limited to: volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, etc.), or any combination thereof. System memory 206 may include an operating system 220, one or more programs 222, and program data 228. In some embodiments, the program 222 may be arranged to execute the instructions 223 of the method 300 according to the invention on an operating system by one or more processors 204 using the program data 228.

Computing device 200 may also include a storage interface bus 234. The storage interface bus 234 enables communication from the storage devices 232 (e.g., removable storage 236 and non-removable storage 238) to the basic configuration 202 via the bus/interface controller 230. Operating system 220, programs 222, and at least a portion of data 224 can be stored on removable storage 236 and/or non-removable storage 238, and loaded into system memory 206 via storage interface bus 234 and executed by one or more processors 204 when computing device 200 is powered on or programs 222 are to be executed.

Computing device 200 may also include an interface bus 240 that facilitates communication from various interface devices (e.g., output devices 242, peripheral interfaces 244, and communication devices 246) to the basic configuration 202 via the bus/interface controller 230. The example output device 242 includes a graphics processing unit 248 and an audio processing unit 250. They may be configured to facilitate communication with various external devices, such as a display or speakers, via one or more a/V ports 252. Example peripheral interfaces 244 can include a serial interface controller 254 and a parallel interface controller 256, which can be configured to facilitate communications with external devices such as input devices (e.g., keyboard, mouse, pen, voice input device, touch input device) or other peripherals (e.g., printer, scanner, etc.) via one or more I/O ports 258. An example communication device 246 may include a network controller 260, which may be arranged to communicate with one or more other computing devices 262 over a network communication link via one or more communication ports 264.

A network communication link may be one example of a communication medium. Communication media may typically be embodied by computer readable instructions, data structures, program modules, and may include any information delivery media, such as carrier waves or other transport mechanisms, in a modulated data signal. A "modulated data signal" may be a signal that has one or more of its data set or its changes made in such a manner as to encode information in the signal. By way of non-limiting example, communication media may include wired media such as a wired network or private-wired network, and various wireless media such as acoustic, Radio Frequency (RF), microwave, Infrared (IR), or other wireless media. The term computer readable media as used herein may include both storage media and communication media.

In the computing device 200 according to the present invention, the program 222 includes a plurality of program instructions of the read-write lock based instruction execution method 300, which may instruct the processor 204 to execute some steps of the read-write lock based instruction execution method 300 executed in the computing device 200 according to the present invention, so that some parts of the computing device 200 execute instructions by executing the read-write lock based instruction execution method 300.

Computing device 200 may be implemented as a server, e.g., file server 240, database 250, a server, an application server, etc., which may be a device such as a Personal Digital Assistant (PDA), a wireless web-browsing device, an application-specific device, or a hybrid device that include any of the above functions. May be implemented as a personal computer including both desktop and notebook computer configurations, and in some embodiments computing device 200 is configured to perform the read-write lock based instruction execution method 300.

FIG. 3 is a flowchart illustrating a method 300 for instruction execution based on a read-write lock, according to an exemplary embodiment of the invention. The read-write lock based instruction execution method 300 of the present invention is suitable for execution in a computing device and further suitable for execution by the operating system 220 shown in FIG. 1. As shown in FIG. 3, the read-write lock based instruction execution method 300 begins with step S310, submitting a first store instruction of the application 110 to store data in the internal memory 140 to the processor 204. When the application 110 needs to store data in the internal memory 140, a first store instruction to store data needs to be submitted to the processor 204 for execution via the operating system 220. The storage area of the internal memory 140 is mapped to a storage space, and the application 110 stores data in the internal memory 140 at a storage address in the storage space.

Subsequently, step S320 is executed, when the processor 204 cannot normally execute the first store instruction due to the store address of the data stored in the first store instruction, a second store instruction is generated according to the data store exception message generated by the processor 204, the second store instruction is suitable for storing the data to be stored in the first store instruction, and the processor 204 does not generate the data store exception message when executing the second store instruction

According to an embodiment of the present invention, when the memory address is not aligned in the internal memory 140, the processor 204 cannot execute the special operation instruction, and generates a data memory exception message. The first store instruction comprises a no-pair store instruction. When the data to be read by the application 110 is stored in the internal memory 140 without being bound, the first operation instruction is a no-bound memory access instruction, and the data storage exception message is a no-bound memory storage exception. The non-alignment means that the initial position of the data stored in the memory is not aligned with the natural boundary of the data of the type stored in the memory sequentially. For example, a 32-bit register, when storing data normally, the register stores a complete 32-bit data, and the first address of the data storage is the first address of the register. However, when the memory is not in the range, the calculator only stores a part of the 32-bit data, the first address of the 32-bit data is offset from the first address of the register, and the first address of the data is at a certain address in the middle of the register. Another portion of the 32-bit data is placed in the next register in a sequential manner. Or a 32-bit register, the processor 204 supports reading 16-bit data at a time, and when the first address of the 16-bit data is in the middle of the 32-bit register, i.e. a 16-bit data cross-store is generated, the processor 204 cannot read the data normally. The processor 204 cannot completely fetch the data from the separately stored 16-bit data according to one instruction, and therefore the processor 204 throws an exception. The non-aligned memory storage exception refers to that the processor 204 throws an exception by directly storing the non-aligned data on the processor 204 which does not support direct storage of the non-aligned data.

FIG. 4 illustrates a schematic diagram of generating a second store instruction according to an exemplary embodiment of the invention. As shown in fig. 4, when the interface access instruction is not converted, the instruction decomposition calculation sequence is executed first, and a first half storage instruction and a second half storage instruction are generated according to the storage address of the first storage instruction, where the first half storage instruction and the second half storage instruction are respectively adapted to store data according to the first half address and the half address, and finally the first half storage instruction and the second half storage instruction are used as the second storage instruction. The first half store instruction and the second half store instruction comprise a pair store instruction.

In the above instruction conversion process, since the memory access model of the application 110 is changed, one memory operation is broken into a plurality of operations, which causes an edge effect, and particularly, causes a change in the atomicity of the memory access. When the correctness of the running logic of the application 110 depends on the assumption of atomicity, the application 110 may be abnormally run due to the lack of atomicity.

FIG. 5 illustrates a diagram of breaking instruction atomicity, according to an exemplary embodiment of the invention. As shown in FIG. 5, since the first half access instruction and the second half access instruction are two independent operations, atomicity does not exist, a view gap exists between them, and other views can be inserted. If a thread with other processing cores in its view performs a memory access write operation, the integrity of the data may be destroyed, possibly causing the application 110 to run abnormally.

Therefore, step S330 needs to be performed to acquire the write lock and lock the process of executing the store instruction. The global read-write lock includes a write lock and a read lock. The write lock and the read lock respectively lock the process of executing the storage instruction and the process of executing the read instruction, so that the same address of the internal memory cannot store and read data at the same time. The store instructions include a first store instruction and a second store instruction, and the read instructions include a first read instruction and a second read instruction. After the process of executing the storage instruction is locked, data reading operation cannot be carried out under the storage address of the storage instruction in the internal memory, and the phenomenon that the integrity of data is damaged when the data is read and wrong data is read is avoided.

According to an embodiment of the present invention, when the write lock is acquired, if the read lock is occupied and the write lock cannot be acquired, the write lock is acquired again. The read lock is occupied indicating that the data for the memory address is being read, and writing the data at this time may result in a memory error. The write lock should need to be acquired again, and if acquired, the data is stored via the second store instruction. If the write lock is acquired, the data representing the storage address is already read, and new data can be written. And if the reading lock is still occupied and the writing lock cannot be acquired, continuously acquiring the writing lock until the reading lock is unoccupied and the writing lock is acquired. In the process of continuously acquiring the write lock, other threads acquiring the read lock are reading data, the read lock can be released after the data reading is completed, and other threads can acquire the write lock.

Subsequently, step S340 is executed, and the second storing instruction is executed by the processor to store the data in the internal memory 140. Specifically, first half data and second half data are generated according to the data, then the processor 204 executes the first half storage instruction, the first half data is stored according to the first half address, and finally the processor 204 executes the second half storage instruction, and the second half data is stored according to the second half address.

After the data is stored in the internal memory 140 by the processor 204, the write lock is released so that other threads of the processor acquire the read lock and read the data.

In the process of storing data, if the thread executes the instruction of accessing data and the operation is to be performed in the storage section where data is currently written, step S350 is executed to protect the atomicity of the data writing process. The read lock is acquired when a first read command is received to read data in the internal memory. If the write lock does not exist, the read lock is acquired, the storage sector is indicated to finish data storage, and the data can be read normally.

Subsequently, step S360 is executed, and if the write lock is occupied and the read lock cannot be acquired, the read lock is acquired again. If the write lock is occupied, it indicates that the storage sector is performing data storage, and if the data is read, erroneous and incomplete data will be read. And acquiring the read lock again, namely judging whether the data is stored completely again.

And if the reading lock still can not be acquired at the moment, continuously acquiring the reading lock, and continuously judging whether the data is completely stored or not until the data is completely stored and the reading lock can be acquired. In the process of continuously and repeatedly acquiring the read lock, data is written, when the data writing is completed, the data can be read normally, and the circulation is exited, so that the wrong data can be prevented from being read.

Subsequently, step S370 is executed, and if the read lock is acquired, the process of executing the read instruction is locked. After the process of executing the reading instruction is locked, data storage operation cannot be carried out under the reading address of the reading instruction in the internal memory, and the problems that data storage errors occur during data storage, the integrity of data is damaged, wrong data is read, and therefore data cannot be written in are avoided.

Finally, step S380 is executed to read data from the internal memory by the processor executing the first read instruction. When reading data, executing a first half section reading instruction through the processor 204, and reading the stored first half section data according to the first half section address; executing the second half instruction through the processor 204, and reading the stored second half data according to the second half address; and then combining the first half data read from the first half address with the second half data read from the second half address to obtain data. When the first half section data and the second half section data are combined and sorted, the obtained first half section data and the obtained second half section data are subjected to logic bit operations such as shifting, AND and/or and the like according to the data structures of the first half section data and the second half section data, and required data are intercepted from data obtained by the interface access instruction and aligned.

After the data is read from the internal memory 140 by the processor 204, the read lock is released so that other threads of the processor can acquire the write lock and store the data.

According to an embodiment of the invention, when instruction conversion is performed, when a certain instruction in an execution instruction stream is a non-interface access instruction, the instruction is converted to obtain an interface access instruction. And traversing all instructions after the instruction stream, and converting the subsequent non-interface access instruction to obtain an interface access instruction. The non-boundary access instruction comprises a non-boundary read instruction and a non-boundary storage instruction, and the boundary access instruction comprises a boundary read instruction and a boundary storage instruction.

If a second read instruction is received from the instruction stream, where the second read instruction includes an untranslated read instruction, the second read instruction is first submitted to the processor 204. When the processor 204 cannot normally execute the second read instruction due to the address of the data read by the second read instruction, the first read instruction is generated according to the data access exception message generated by the processor 204, the first read instruction is suitable for reading the data to be read by the second read instruction, and the processor 204 does not generate the data read exception message when executing the first read instruction.

When a first read instruction is generated according to the data access exception message generated by the processor 204, the instruction decomposition sequence is executed first, and a first half read instruction and a second half read instruction are generated according to the storage address of the second read instruction, wherein the first half read instruction and the second half read instruction are respectively suitable for reading data according to the first half address and the second half address, and the first half read instruction and the second half read instruction are used as the first read instruction.

In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that the invention as claimed requires more features than are expressly recited in each claim.

Those skilled in the art will appreciate that the modules or units or groups of devices in the examples disclosed herein may be arranged in a device as described in this embodiment, or alternatively may be located in one or more devices different from the devices in this example. The modules in the foregoing examples may be combined into one module or may be further divided into multiple sub-modules.

Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. Modules or units or groups in embodiments may be combined into one module or unit or group and may furthermore be divided into sub-modules or sub-units or sub-groups. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments.

Furthermore, some of the described embodiments are described herein as a method or combination of method elements that can be performed by a processor of a computer system or by other means of performing the described functions. A processor having the necessary instructions for carrying out the method or method elements thus forms a means for carrying out the method or method elements. Further, the elements of the apparatus embodiments described herein are examples of the following apparatus: the apparatus is used to implement the functions performed by the elements for the purpose of carrying out the invention.

The various techniques described herein may be implemented in connection with hardware or software or, alternatively, with a combination of both. Thus, the methods and apparatus of the present invention, or certain aspects or portions thereof, may take the form of program code (i.e., instructions) embodied in tangible media, such as floppy diskettes, CD-ROMs, hard drives, or any other machine-readable storage medium, wherein, when the program is loaded into and executed by a machine, such as a computer, the machine becomes an apparatus for practicing the invention.

In the case of program code execution on programmable computers, the computing device will generally include a processor, a storage medium readable by the processor (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device. Wherein the memory is configured to store program code; the processor is configured to execute the read-write lock based instruction execution method of the present invention according to instructions in the program code stored in the memory.

By way of example, and not limitation, computer readable media may comprise computer storage media and communication media. Computer-readable media includes both computer storage media and communication media. Computer storage media store information such as computer readable instructions, data structures, program modules or other data. Communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. Combinations of any of the above are also included within the scope of computer readable media.

As used herein, unless otherwise specified the use of the ordinal adjectives "first", "second", "third", etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner.

While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this description, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as described herein. Furthermore, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter. Accordingly, many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the appended claims. The present invention has been disclosed in an illustrative rather than a restrictive sense, and the scope of the present invention is defined by the appended claims.

Claims

1. An instruction execution method based on a read-write lock, which is suitable for being executed in a computing device, wherein the computing device comprises a processor, an internal memory and one or more applications, a storage area of the internal memory is mapped into a storage space, and the applications read and write data in the internal memory by using storage addresses in the storage space, and the method comprises the following steps:

submitting a first store instruction of the application to the processor that stores data in the internal memory;

when the processor cannot normally execute a first storage instruction due to the storage address of data stored in the first storage instruction, generating a second storage instruction according to a data storage exception message generated by the processor, wherein the second storage instruction is suitable for storing the data to be stored in the first storage instruction, and the processor cannot generate the data storage exception message when executing the second storage instruction;

acquiring a write lock, and locking the process of executing the storage instruction;

storing, by the processor, data in the internal memory by executing the second store instruction;

when a first reading instruction for reading data in the internal memory is received, a reading lock is acquired, the writing lock and the reading lock are mutually exclusive, and when locking is carried out according to the writing lock or the reading lock, the data cannot be stored and read at the same address;

if the write lock is occupied and the read lock cannot be acquired, acquiring the read lock again;

if the read lock is acquired, locking the process of executing the read instruction;

and executing the first reading instruction by the processor to read data from the internal memory.

2. The method of claim 1, wherein said generating a second store instruction based on a data store exception message generated by said processor comprises the steps of:

generating a first half-segment storage instruction and a second half-segment storage instruction according to the storage address of the first storage instruction, wherein the first half-segment storage instruction and the second half-segment storage instruction are respectively suitable for storing data according to a first half-segment address and a half-segment address;

and taking the first half storage instruction and the second half storage instruction as second storage instructions.

3. The method of claim 2, wherein the method further comprises the steps of:

if the read lock is occupied and the write lock cannot be acquired, acquiring the write lock again;

and if the write lock is acquired, storing the data through a second storage instruction.

4. The method of claim 3, wherein said executing said second store instruction by said memory to store data in said internal memory comprises the steps of:

generating first half data and second half data according to the data;

executing the first half segment storage instruction through the processor, and storing the first half segment data according to the first half segment address;

and executing the second half segment storage instruction through the processor, and storing the second half segment data according to the second half segment address.

5. The method of claim 4, wherein the method further comprises the steps of:

and releasing the write lock after the processor finishes storing the data in the internal memory so that other threads of the processor can acquire the read lock and read the data.

6. The method of claim 5, wherein the first read instruction comprises a first half read instruction and a second half read instruction, and the reading of data by the first read instruction comprises the steps of:

executing the first half section reading instruction through the processor, and reading the stored first half section data according to the first half section address;

executing the second half-segment reading instruction through the processor, and reading stored second half-segment data according to the second half-segment address;

and combining the first half data read from the first half address with the second half data read from the second half address to obtain data.

7. The method of claim 6, wherein the method further comprises the steps of:

and releasing the read lock after the processor finishes reading the data in the internal memory so that other threads of the processor can acquire the write lock and store the data.

8. The method of claims 1-7, further comprising the steps of:

if a second read instruction is received, submitting the second read instruction to the processor;

when the processor cannot normally execute the second reading instruction due to the address of the data read by the second reading instruction, generating a first reading instruction according to the data access exception message generated by the processor, wherein the first reading instruction is suitable for reading the data to be read by the second reading instruction, and the processor cannot generate the data reading exception message when executing the first reading instruction.

9. The method of claim 8, wherein said generating a first read instruction based on a data access exception message generated by said processor comprises the steps of:

generating a first half section reading instruction and a second half section reading instruction according to the storage address of the second reading instruction, wherein the first half section reading instruction and the second half section reading instruction are respectively suitable for reading data according to a first half section address and a second half section address;

and taking the first half segment of reading instruction and the second half segment of reading instruction as a first reading instruction.

10. The method of any of claims 1-9, wherein the first store instruction comprises a no-pair store instruction, the first and second half store instructions comprising a pair store instruction.

11. The method of any of claims 1-10, wherein the second read instruction comprises a no bound read instruction, and the first half and second half read instructions comprise bound read instructions.

12. A computing device, comprising:

one or more processors;

a memory; and

one or more apparatuses comprising instructions for performing the method of any of claims 1-11.

13. A computer readable storage medium storing one or more programs, the one or more programs comprising instructions, which when executed by a computing device, cause the computing device to perform the method of any of claims 1-11.