CN113535451A - Processing method and device for processor access exception, storage medium and computing equipment - Google Patents
Processing method and device for processor access exception, storage medium and computing equipment Download PDFInfo
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Abstract
The application discloses a processing method, a device, a storage medium and a computing device for processor access exception, wherein the method comprises the following steps: in the process of accessing a memory by a processor, when detecting that an unaligned access instruction causes an exception, calling an exception service function corresponding to the exception, and storing an exception address and an exception pointer, wherein the exception address is an address to be accessed by the unaligned access instruction, and the exception pointer points to the unaligned access instruction; the control system enters a kernel state, exits the kernel state after a trap task is created, and returns to the system state; and executing a trap task, converting the non-aligned access instruction aiming at the abnormal address into an aligned access instruction covering the abnormal address, and executing the aligned access instruction so as to simulate the non-aligned access instruction to realize the access to the abnormal address. The method and the device solve the technical problem that in the prior art, non-alignment access is complex to process.
Description
Technical Field
The present application relates to the field of data processing technologies, and in particular, to a method and an apparatus for processing a processor access exception, a storage medium, and a computing device.
Background
The Loongson processor is based on MIPS architecture, belongs to RISC instruction set, and has certain requirement on access address, for example, when storing and accessing half word (half word), the memory address is required to be 2 byte alignment or integral multiple thereof, when accessing word (word), the memory address must be 4 byte alignment or integral multiple thereof.
Generally, programs are designed to access data in any address space, but due to the limitation of the MIPS architecture, when many programs are transplanted to a Loongson platform, abnormal execution and unscheduled program crash can occur, which is an abnormal error caused by non-aligned address access.
Aiming at the technical problem of complicated non-aligned access processing in the prior art, an effective solution is not provided at present.
Disclosure of Invention
The embodiment of the application provides a processing method and device for processor access exception, a storage medium and a computing device, so as to at least solve the technical problem that processing non-aligned access is tedious in the prior art.
According to an aspect of the embodiments of the present application, a method for processing a processor access exception is provided, including in a process that a processor accesses a memory, when detecting that an unaligned access instruction causes an exception, calling an exception service function corresponding to the exception, and storing an exception address and an exception pointer, where the exception address is an address to be accessed by the unaligned access instruction, and the exception pointer points to the unaligned access instruction; the control system enters a kernel state, exits the kernel state after a trap task is created, and returns to the system state; and executing a trap task, converting the non-aligned access instruction aiming at the abnormal address into an aligned access instruction covering the abnormal address, and executing the aligned access instruction so as to simulate the non-aligned access instruction to realize the access to the abnormal address.
According to another aspect of the embodiments of the present application, there is provided a processing apparatus for a processor access exception, including: the detection unit is used for calling an abnormal service function corresponding to an abnormal condition when detecting that the non-aligned access instruction causes the abnormal condition in the process that the processor accesses the memory, and storing an abnormal address and an abnormal pointer, wherein the abnormal address is an address to be accessed by the non-aligned access instruction, and the abnormal pointer points to the non-aligned access instruction; the control unit is used for controlling the system to enter the kernel state, exiting the kernel state after the trap task is created, and returning to the system state; and the execution unit is used for executing the trap task, converting the non-aligned access instruction aiming at the abnormal address into an aligned access instruction covering the abnormal address, and executing the aligned access instruction so as to simulate the non-aligned access instruction to realize the access to the abnormal address.
On the basis of any of the above embodiments, the non-aligned access instruction includes: a read access instruction that attempts to read information from a non-aligned address, and/or a write access instruction that attempts to write information to a non-aligned address.
On the basis of any one of the above embodiments, executing the trap task, and converting the non-aligned access instruction for the exception address into the aligned access instruction covering the exception address includes: determining an alignment boundary in the exception address to determine a first portion of the exception address to the left of the alignment boundary and a second portion of the exception address to the right of the alignment boundary; the non-aligned access instruction is split into a first aligned access instruction accessing the first portion and a second aligned access instruction accessing the second portion according to the alignment boundary.
On the basis of any one of the above embodiments, when the non-aligned access instruction includes: when a read access instruction for reading information from a non-aligned address is attempted, the first alignment access instruction comprises a first alignment read access instruction, and the second alignment access instruction comprises a second alignment read access instruction, wherein executing the alignment access instruction to simulate the non-alignment access instruction to realize access to an abnormal address comprises: executing a first alignment read access instruction to obtain a first group of data from a memory; extracting data corresponding to the first part from the first group of data and storing the data in a temporary result; executing a second alignment read access instruction to obtain a second group of data from the memory; extracting data corresponding to the second part from the second group of data; and shifting the temporary result according to the length of the data corresponding to the second part so as to merge the data corresponding to the second part into the temporary result to obtain the data corresponding to the abnormal address.
On the basis of any of the above embodiments, an exception pointer is stored in the EPC register for storing the address of the instruction where the exception occurred, and indicating the address to which the exception should be returned after the exception is processed.
On the basis of any of the above embodiments, the exception address is stored in the Badvaddr invalid virtual address memory for storing the address causing the exception.
On the basis of any of the above embodiments, after the aligned access instruction is executed to simulate the non-aligned access instruction to implement access to the exception address, the method further includes: and restoring the context and returning the address pointed by the exception pointer to continue executing.
According to another aspect of the embodiments of the present application, there is provided a storage medium including a stored program, wherein when the program runs, a device on which the storage medium is located is controlled to execute the method of any of the above embodiments.
According to another aspect of embodiments of the present application, there is provided a computing device comprising a processor for executing a program, wherein the program executes to perform the method of any of the above embodiments.
In the embodiment of the application, in the process of accessing the memory by the processor, when detecting that an unaligned access instruction causes an exception, calling an exception service function corresponding to the exception, and storing an exception address and an exception pointer, wherein the exception address is an address to be accessed by the unaligned access instruction, and the exception pointer points to the unaligned access instruction; the control system enters a kernel state, exits the kernel state after a trap task is created, and returns to the system state; and executing a trap task, converting the non-aligned access instruction aiming at the abnormal address into an aligned access instruction covering the abnormal address, and executing the aligned access instruction so as to simulate the non-aligned access instruction to realize access to the abnormal address, thereby solving the technical problem of fussy processing of the non-aligned access in the prior art.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
fig. 1 is a block diagram of a hardware structure of a computer terminal (or a mobile device) for implementing a processing method for a processor access exception according to an embodiment of the present application;
FIG. 2 is a flow chart of a method for handling a processor access exception according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a memory according to an embodiment of the present application;
FIG. 4 is a flow diagram of another method for handling a processor access exception according to an embodiment of the present application; and
fig. 5 is a schematic structural diagram of a processing apparatus for processing a processor access exception according to an embodiment of the present application.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Example 1
In accordance with an embodiment of the present application, there is provided an embodiment of a method for handling processor access exceptions, where the steps illustrated in the flowchart of the figure may be performed in a computer system such as a set of computer-executable instructions, and where a logical order is illustrated in the flowchart, in some cases the steps illustrated or described may be performed in an order different than that illustrated herein.
The method provided by the first embodiment of the present application may be executed in a mobile terminal, a computer terminal, or a similar computing device. Fig. 1 shows a hardware configuration block diagram of a computer terminal (or mobile device) for implementing a processing method of a processor access exception. As shown in fig. 1, the computer terminal 10 (or mobile device 10) may include one or more (shown as 102a, 102b, … …, 102 n) processors 102 (the processors 102 may include, but are not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA, etc.), a memory 104 for storing data, and a transmission device 106 for communication functions. Besides, the method can also comprise the following steps: a display, an input/output interface (I/O interface), a Universal Serial Bus (USB) port (which may be included as one of the ports of the I/O interface), a network interface, a power source, and/or a camera. It will be understood by those skilled in the art that the structure shown in fig. 1 is only an illustration and is not intended to limit the structure of the electronic device. For example, the computer terminal 10 may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.
It should be noted that the one or more processors 102 and/or other data fusion circuitry described above may be generally referred to herein as "data fusion circuitry". The data fusion circuit may be embodied in whole or in part as software, hardware, firmware, or any combination thereof. Further, the data fusion circuit may be a single stand-alone processing module, or incorporated in whole or in part into any of the other elements in the computer terminal 10 (or mobile device). As referred to in the embodiments of the application, the data fusion circuit acts as a processor control (e.g., selection of variable resistance termination paths connected to the interface).
The memory 104 may be used to store software programs and modules of application software, such as program instructions/data storage devices corresponding to the product activation determination method in the embodiment of the present application, and the processor 102 executes various functional applications and data fusion by running the software programs and modules stored in the memory 104, that is, implementing the processing method of the processor access exception described above. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to the computer terminal 10 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission device 106 is used for receiving or transmitting data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the computer terminal 10. In one example, the transmission device 106 includes a Network adapter (NIC) that can be connected to other Network devices through a base station to communicate with the internet. In one example, the transmission device 106 can be a Radio Frequency (RF) module, which is used to communicate with the internet in a wireless manner.
The display may be, for example, a touch screen type Liquid Crystal Display (LCD) that may enable a user to interact with a user interface of the computer terminal 10 (or mobile device).
Here, it should be noted that in some alternative embodiments, the computer device (or mobile device) shown in fig. 1 described above may include hardware elements (including circuitry), software elements (including computer code stored on a computer-readable medium), or a combination of both hardware and software elements. It should be noted that fig. 1 is only one example of a particular specific example and is intended to illustrate the types of components that may be present in the computer device (or mobile device) described above.
The application runs a processing method of the processor access exception as shown in fig. 2 under the above running environment. Fig. 2 is a flowchart of a processing method of a processor access exception according to an embodiment of the present application, and as shown in fig. 2, the processing method of the processor access exception may include:
step S202: in the process of accessing the memory by the processor, when detecting that the non-aligned access instruction causes an exception, calling an exception service function corresponding to the exception, and storing an exception address and an exception pointer, wherein the exception address is an address to be accessed by the non-aligned access instruction, and the exception pointer points to the non-aligned access instruction.
In step S202, the processor reads a half word by lh on the MIPS platform based on, for example, the MIPS architecture, and the address of the memory must be an integer multiple of 2; iw reads a word, the address of the memory must be an integer multiple of 4; when sd writes a doubleword, the memory address must be an integer multiple of 8. If the target addresses are not aligned during memory access, an exception is caused, typically, the system directly kills the process after prompting a bus error. When the abnormity is detected, the abnormity is directly intercepted, and an abnormal service function corresponding to the abnormity is called. The non-aligned access instruction includes: a read access instruction that attempts to read information from a non-aligned address, and a write access instruction that attempts to write information to a non-aligned address. The method comprises the steps that a non-aligned access instruction, an abnormal vector number and an abnormal service function corresponding to the non-aligned access instruction can be appointed in the system in advance, when a read access instruction which tries to read information from a non-aligned address is detected to cause an abnormality, for example, a load instruction which is used for loading data in a memory into a register causes an abnormality, the abnormal vector number corresponding to the abnormality can be determined to be 4, and the abnormal service function corresponding to the abnormal vector number 4 can be called; for example, when a write access instruction that attempts to write information to a non-aligned address is detected to raise an exception, such as a store instruction used to store data from a register into memory, the exception vector number corresponding to the exception may be determined to be 5, and an exception service function corresponding to exception vector number 5 may be invoked.
In step S202, an exception pointer is stored in the EPC register, and is used to store the instruction address where the exception occurs, and indicate the address to which the exception should be returned after the exception is processed; the exception address is stored in the Badvaddr invalid virtual address memory for storing the address that caused the exception. In addition, exception service functions are stored in other associated field registers.
Step S204: and the control system enters a kernel state, exits the kernel state after the trap task is created, and returns to the system state.
In the step S204, the system enters the kernel mode, constructs an environment for accessing the exception trap program, creates an exception trap task, exits the kernel mode, and returns to the system mode.
Step S206: and executing a trap task, converting the non-aligned access instruction aiming at the abnormal address into an aligned access instruction covering the abnormal address, and executing the aligned access instruction so as to simulate the non-aligned access instruction to realize the access to the abnormal address.
In step S206, the system executes the simulation program in the trap task, acquires the current abnormal instruction by acquiring the currently executing PC register, acquires the address corresponding to the abnormal instruction by acquiring the BadVaddr value, then calls two non-aligned load or store instructions by software simulation, performs data read/write operation on the memory address, stores the data result as a return value after the simulation instruction is executed, then recovers the context, and returns to the address pointed by the EPC register to continue execution.
In summary, through the above steps S202 to S206, in the process of accessing the memory by the processor, when it is detected that the non-aligned access instruction causes an exception, an exception service function corresponding to the exception is called, and an exception address and an exception pointer are stored, where the exception address is an address to be accessed by the non-aligned access instruction, and the exception pointer points to the non-aligned access instruction; the control system enters a kernel state, exits the kernel state after a trap task is created, and returns to the system state; and executing a trap task, converting the non-aligned access instruction aiming at the abnormal address into an aligned access instruction covering the abnormal address, and executing the aligned access instruction so as to simulate the non-aligned access instruction to realize access to the abnormal address, thereby solving the technical problem of complicated processing of the non-aligned access in the prior art, avoiding switching of a kernel state and ensuring the execution efficiency of the system.
The application provides a system level solution for the exception and programming trouble caused by the non-aligned address read-write access of, for example, a Loongson processor, and ensures that no exception error is generated even if the non-aligned read-write access is performed. The method and the system take over the non-aligned access exception, software simulates twice operation of the non-aligned address access instruction to finish loading or storing of data, and compared with other methods, the method and the system thoroughly solve the problem of program crash caused by non-aligned access. The scheme of using byte filling to ensure the alignment of the storage addresses in the process of designing the program data structure can lead to the waste of a very right memory space and the improvement of cost, and meanwhile, developers need to spend more time to think, so the method improves the development efficiency and reduces the occupation of the storage space compared with the scheme. Meanwhile, the method is more flexible compared with the special processing of using the compiler pack to store the structure.
Optionally, the non-aligned access instruction comprises: a read access instruction that attempts to read information from a non-aligned address, and/or a write access instruction that attempts to write information to a non-aligned address.
Optionally, in step S206: executing a trap task, and converting a non-aligned access instruction aiming at an exception address into an aligned access instruction covering the exception address comprises the following steps:
step S2062: determining an alignment boundary in the exception address to determine a first portion of the exception address to the left of the alignment boundary and a second portion of the exception address to the right of the alignment boundary;
in step S2062, the alignment boundary is related to the word length of the access, and when 4-byte content is accessed at a time, the alignment boundary is a boundary of 4 bytes, and when 2-byte content is accessed at a time, the alignment boundary is a boundary of 2 bytes. FIG. 3 is a schematic diagram of a memory according to an embodiment of the present application; referring to FIG. 3, when the processor tries to access address 0x01 in the internal address to obtain a word, an exception is caused by the access instruction accessing a non-aligned address, where the exception address includes 0x01, 0x02, 0x03, and 0x04, then the alignment boundary in the exception address can be determined to be aligned with 0x04, and the determination of the first portion 0x01, 0x02, 0x03 of the exception address to the left of the alignment boundary and the second portion 0x04 of the exception address to the right of the alignment boundary can be continued.
Step S2064: the non-aligned access instruction is split into a first aligned access instruction accessing the first portion and a second aligned access instruction accessing the second portion according to the alignment boundary.
In step S2064, as shown in fig. 3, the first alignment instruction obtains 3 bytes of left edge and stores the left edge in the temporary result R, and the second alignment instruction obtains 1 byte of right edge.
Through the above steps S2062 and S2064, based on the error exception caused by the non-aligned access of the processor, the kernel is used to construct a storage access error execution task, in which the non-aligned address is split by software simulation, two storage operations are performed, and then the storage operations are merged to return correct data.
Optionally, when the non-aligned access instruction includes: when a read access instruction for reading information from a non-aligned address is attempted, the first alignment access instruction comprises a first alignment read access instruction, and the second alignment access instruction comprises a second alignment read access instruction, wherein executing the alignment access instruction to simulate the non-alignment access instruction to realize access to an abnormal address comprises:
executing a first alignment read access instruction to obtain a first group of data from a memory;
extracting data corresponding to the first part from the first group of data and storing the data in a temporary result;
executing a second alignment read access instruction to obtain a second group of data from the memory;
extracting data corresponding to the second part from the second group of data;
and shifting the temporary result according to the length of the data corresponding to the second part to combine the data corresponding to the first part and the data corresponding to the second part to obtain the data corresponding to the abnormal address.
Referring to fig. 3, the load is performed according to the current address and is divided into two steps, the first step is to change the address +3, i.e. the address is 0x01+3, to 0x04, so that 3 bytes of the left edge are obtained by using the load instruction and stored in the temporary result R, and the second step is to obtain 1 byte of the right edge through the load instruction and is denoted as T. And the shifting process moves the result R image obtained in the first step by 3 bits, wherein R is R < <3, so that the lower 8 bits are reserved, and finally, the merging process is carried out, the shifted result and the data obtained in the second step are subjected to bit OR operation, namely R is R | T, and finally, the word to be loaded is merged.
Optionally, an exception pointer is stored in the EPC register for storing the address of the instruction where the exception occurred, while indicating the address to which the exception should be returned after it has been handled.
Optionally, the exception address is stored in a Badvaddr invalid virtual address memory for storing the address that caused the exception.
Optionally, after executing the aligned access instruction to simulate a non-aligned access instruction to implement access to the exception address, the method further includes: and restoring the context and returning the address pointed by the exception pointer to continue executing. Specifically, after the simulation instruction is executed, the data result is stored as a return value, and then the context is restored and the address pointed by the EPC register is returned to continue execution.
According to the application, a trap program is constructed through the non-aligned access exception of the Loongson processor, then the non-aligned address correction is carried out through the simulation program, and therefore a correct result is returned, and the specific scheme is described as follows:
1. an exception handling function is specified in the system and serves as a vector service function of an exception vector number 4 and a vector number 5, the vector number 4 corresponds to an address error in load and iftch, and the vector number 5 corresponds to an address error in store;
2. when the address non-alignment access exception of the exception number 4 and the vector number 5 occurs, jumping to a specified exception vector entry to execute, and storing a field register group in exception processing, wherein BadVaddr and EPC are stored as important parameters and are processed subsequently, and the EPC points to an instruction causing the exception;
3. the system enters a kernel state, an access abnormal trap program environment is constructed, an abnormal trap task is created, the kernel state is exited, and the system state is returned;
4. the system executes a simulation program, acquires a current abnormal instruction by acquiring a currently executed PC register, acquires an address corresponding to the abnormality by acquiring a BadVaddr value, and then simulates and calls two loading or storing instructions by software to perform data reading and writing operations on the memory address;
5. and after the simulation instruction is executed, storing the data result as a return value, then restoring the context, and returning to the address pointed by the EPC register to continue executing.
FIG. 4 is a flow diagram of another method for handling a processor access exception according to an embodiment of the present application; as shown in fig. 4, when reading and writing occurs in the non-aligned address storage, a non-aligned access exception set by the system is triggered, the exception entry function calls the total exception service function, the address where the register context is saved and an error occurs, and the value of the current EPC. And then constructing and executing a storage exception task. And in the storage exception task, software simulation operation is carried out through loading, shifting and combining according to the current wrong instruction and the non-aligned address, if the error occurs, the task is returned, otherwise, the task is returned after error processing is executed. The specific loading process may be combined with that shown in fig. 3, when the CPU tries to access the address 0x01 to obtain a word, a non-aligned access exception may be triggered due to the non-aligned access, and the process may refer to fig. 1, where only the loading, splitting, and merging processes are described here, first, the program algorithm performs loading according to the current address into two steps, where the first step is to change the address +3, that is, the address is 0x01+3, to 0x04, so that a load instruction is used to obtain 3 bytes on a left edge, and store the left edge into a temporary result R, and the second step is to obtain 1 byte on a right edge through the load instruction, which is denoted as T. And the shifting process moves the result R image obtained in the first step by 3 bits, wherein R is R < <3, so that the lower 8 bits are reserved, and finally, the merging process is carried out, the shifted result and the data obtained in the second step are subjected to bit OR operation, namely R is R | T, and finally, the word to be loaded is merged.
The method is based on that errors and exceptions can be caused when a Loongson processor is accessed in a non-aligned mode, a kernel is used for constructing a storage access error execution task, software is adopted to simulate and split non-aligned addresses in the task, storage operation is carried out twice, then the non-aligned addresses are combined, and correct data are returned.
The method and the system take over the non-aligned access exception, software simulates twice operation of the non-aligned address access instruction to finish loading or storing of data, and compared with other methods, the method and the system thoroughly solve the problem of program crash caused by non-aligned access. The scheme of using byte filling to ensure the alignment of the storage addresses in the process of designing the program data structure can lead to the waste of a very right memory space and the improvement of cost, and meanwhile, developers need to spend more time to think, so the method improves the development efficiency and reduces the occupation of the storage space compared with the scheme. Meanwhile, the method is more flexible compared with the special processing of using the compiler pack to store the structure.
It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present application is not limited by the order of acts described, as some steps may occur in other orders or concurrently depending on the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.
Through the above description of the embodiments, those skilled in the art can clearly understand that the processing method of the processor access exception according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method of the embodiments of the present application.
Example 2
According to the embodiment of the application, a processor access exception handling device for implementing the processing method of the processor access exception is further provided, and the device is implemented in a software or hardware mode.
FIG. 5 is a block diagram of an apparatus for handling processor access exceptions according to an embodiment of the present disclosure; as shown in fig. 5, the apparatus 500 includes: a detection unit 502, a control unit 504, and an execution unit 506, wherein:
a detecting unit 502, configured to, in a process that a processor accesses a memory, when it is detected that an unaligned access instruction causes an exception, call an exception service function corresponding to the exception, and store an exception address and an exception pointer, where the exception address is an address to be accessed by the unaligned access instruction, and the exception pointer points to the unaligned access instruction;
the control unit 504 is used for controlling the system to enter a kernel state, exiting the kernel state after a trap task is created, and returning to the system state;
and the execution unit 506 is configured to execute a trap task, convert the non-aligned access instruction for the exception address into an aligned access instruction covering the exception address, and execute the aligned access instruction to simulate the non-aligned access instruction to implement access to the exception address.
Here, it should be noted that the detecting unit 502, the controlling unit 504, and the executing unit 506 correspond to steps S202 to S206 in embodiment 1, and the three modules are the same as the corresponding steps in the implementation example and the application scenario, but are not limited to the disclosure in embodiment 1.
In summary, through the detection unit 502, the control unit 504, and the execution unit 506, in the process of accessing the memory by the processor, when it is detected that the non-aligned access instruction causes an exception, an exception service function corresponding to the exception is called, and an exception address and an exception pointer are stored, where the exception address is an address to be accessed by the non-aligned access instruction, and the exception pointer points to the non-aligned access instruction; the control system enters a kernel state, exits the kernel state after a trap task is created, and returns to the system state; and executing a trap task, converting the non-aligned access instruction aiming at the abnormal address into an aligned access instruction covering the abnormal address, and executing the aligned access instruction so as to simulate the non-aligned access instruction to realize access to the abnormal address, thereby solving the technical problem of fussy processing of the non-aligned access in the prior art.
The application provides a system level solution for the exception and programming trouble caused by the non-aligned address read-write access of, for example, a Loongson processor, and ensures that no exception error is generated even if the non-aligned read-write access is performed. The method and the system take over the non-aligned access exception, software simulates twice operation of the non-aligned address access instruction to finish loading or storing of data, and compared with other methods, the method and the system thoroughly solve the problem of program crash caused by non-aligned access. The scheme of using byte filling to ensure the alignment of the storage addresses in the process of designing the program data structure can lead to the waste of a very right memory space and the improvement of cost, and meanwhile, developers need to spend more time to think, so the method improves the development efficiency and reduces the occupation of the storage space compared with the scheme. Meanwhile, the method is more flexible compared with the special processing of using the compiler pack to store the structure.
Optionally, the non-aligned access instruction comprises: a read access instruction that attempts to read information from a non-aligned address, and/or a write access instruction that attempts to write information to a non-aligned address.
Optionally, the execution unit 506 is further configured to: determining an alignment boundary in the exception address to determine a first portion of the exception address to the left of the alignment boundary and a second portion of the exception address to the right of the alignment boundary; the non-aligned access instruction is split into a first aligned access instruction accessing the first portion and a second aligned access instruction accessing the second portion according to the alignment boundary.
Optionally, when the non-aligned access instruction includes: when attempting a read access instruction to read information from a non-aligned address, the first alignment access instruction comprises a first alignment read access instruction, and the second alignment access instruction comprises a second alignment read access instruction, wherein the execution unit 506 is further configured to: executing a first alignment read access instruction to obtain a first group of data from a memory; extracting data corresponding to the first part from the first group of data and storing the data in a temporary result; executing a second alignment read access instruction to obtain a second group of data from the memory; extracting data corresponding to the second part from the second group of data; and shifting the temporary result according to the length of the data corresponding to the second part to combine the data corresponding to the first part and the data corresponding to the second part to obtain the data corresponding to the abnormal address.
Optionally, an exception pointer is stored in the EPC register for storing the address of the instruction where the exception occurred, while indicating the address to which the exception should be returned after it has been handled.
Optionally, the exception address is stored in a Badvaddr invalid virtual address memory for storing the address that caused the exception.
Optionally, the apparatus further comprises: and the recovery unit is used for recovering the context and returning the address pointed by the exception pointer to continue execution after the alignment access instruction is executed to simulate the non-alignment access instruction to realize the access to the exception address. Specifically, after the simulation instruction is executed, the data result is stored as a return value, and then the context is restored and the address pointed by the EPC register is returned to continue execution.
Example 3
Embodiments of the present application may provide a computing device, which may be any one of computer terminal devices in a computer terminal group. Optionally, in this embodiment, the computing device may also be replaced with a terminal device such as a mobile terminal.
Optionally, in this embodiment, the computing device may be located in at least one network device of a plurality of network devices of a computer network.
Optionally, in this embodiment, the above-mentioned computing device includes one or more processors, a memory, and a transmission device. The memory may be used to store software programs and modules, such as program instructions/modules corresponding to the method and apparatus for processing a processor access exception in the embodiments of the present application. The processor executes various functional applications and data fusion by running software programs and modules stored in the memory, namely, the processing method of the processor access exception is realized.
Alternatively, the memory may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory may further include memory located remotely from the processor, which may be connected to the computing device 120 over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
In this embodiment, when the processor in the above-mentioned computing device runs the stored program code, the following method steps may be executed: in the process of accessing the memory by the processor, when detecting that the non-aligned access instruction causes an exception, calling an exception service function corresponding to the exception, and storing an exception address and an exception pointer, wherein the exception address is an address to be accessed by the non-aligned access instruction, and the exception pointer points to the non-aligned access instruction; the control system enters a kernel state, exits the kernel state after a trap task is created, and returns to the system state; and executing a trap task, converting the non-aligned access instruction aiming at the abnormal address into an aligned access instruction covering the abnormal address, and executing the aligned access instruction so as to simulate the non-aligned access instruction to realize the access to the abnormal address.
Further, in this embodiment, when the processor in the computing device runs the stored program code, any method step listed in embodiment 1 may be executed, which is not described in detail herein for reasons of brevity.
Example 3
Embodiments of the present application also provide a storage medium. Optionally, in this embodiment, the storage medium may be configured to store program codes executed by the processing method for the processor access exception.
Optionally, in this embodiment, the storage medium may be located in any one of computer terminals in a computer terminal group in a computer network, or in any one of mobile terminals in a mobile terminal group.
Optionally, in this embodiment, the storage medium is configured to store program code for performing the following steps: in the process of accessing the memory by the processor, when detecting that the non-aligned access instruction causes an exception, calling an exception service function corresponding to the exception, and storing an exception address and an exception pointer, wherein the exception address is an address to be accessed by the non-aligned access instruction, and the exception pointer points to the non-aligned access instruction; the control system enters a kernel state, exits the kernel state after a trap task is created, and returns to the system state; and executing a trap task, converting the non-aligned access instruction aiming at the abnormal address into an aligned access instruction covering the abnormal address, and executing the aligned access instruction so as to simulate the non-aligned access instruction to realize the access to the abnormal address.
Further, in this embodiment, the storage medium is configured to store the program code for executing any one of the method steps listed in embodiment 1, which is not described in detail herein for brevity.
The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
In the above embodiments of the present application, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the embodiments provided in the present application, it should be understood that the disclosed technology can be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, a division of a unit is merely a division of a logic function, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.
The foregoing is only a preferred embodiment of the present application and it should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.
Claims (10)
1. A method for handling processor access exceptions, comprising:
in the process of accessing a memory by a processor, when detecting that an unaligned access instruction causes an exception, calling an exception service function corresponding to the exception, and storing an exception address and an exception pointer, wherein the exception address is an address to be accessed by the unaligned access instruction, and the exception pointer points to the unaligned access instruction;
the control system enters a kernel state, exits the kernel state after a trap task is created, and returns to the system state;
executing the trap task, converting a non-aligned access instruction aiming at an abnormal address into an aligned access instruction covering the abnormal address, and executing the aligned access instruction to simulate the non-aligned access instruction to realize access to the abnormal address.
2. The method of claim 1, wherein the non-aligned access instruction comprises: a read access instruction that attempts to read information from a non-aligned address, and/or a write access instruction that attempts to write information to a non-aligned address.
3. The processing method of claim 2, wherein executing the trap task to convert a non-aligned access instruction for an exception address to an aligned access instruction that encompasses the exception address comprises:
determining an alignment boundary in the exception address to determine a first portion of the exception address to the left of the alignment boundary and a second portion of the exception address to the right of the alignment boundary;
splitting the non-aligned access instruction into a first aligned access instruction accessing the first portion and a second aligned access instruction accessing the second portion according to the alignment boundary.
4. The processing method of claim 3, wherein when the non-aligned access instruction comprises: when a read access instruction for reading information from a non-aligned address is attempted, the first aligned access instruction comprises a first aligned read access instruction, and the second aligned access instruction comprises a second aligned read access instruction, wherein executing the aligned access instruction to simulate the non-aligned access instruction to implement access to the exception address comprises:
executing the first alignment read access instruction to obtain a first group of data from a memory;
extracting data corresponding to the first part from the first group of data and storing the data in a temporary result;
executing the second alignment read access instruction to obtain a second group of data from the memory;
extracting data corresponding to the second part from a second group of data;
and shifting the temporary result according to the length of the data corresponding to the second part to merge the data corresponding to the second part into the temporary result to obtain the data corresponding to the abnormal address.
5. The method of claim 1, wherein the exception pointer is stored in an EPC register to store the address of the instruction where the exception occurred, while indicating the address to which the exception should be returned after it has been processed.
6. The processing method as in claim 1, wherein the exception address is stored in a Badvaddr invalid virtual address memory for storing the address causing the exception.
7. The processing method of claim 1, wherein after executing the aligned access instruction to emulate the non-aligned access instruction to enable access to the exception address, the method further comprises:
and restoring the context, and returning the address pointed by the exception pointer to continue executing.
8. An apparatus for handling processor access exceptions, comprising:
the device comprises a detection unit, a processing unit and a processing unit, wherein the detection unit is used for calling an abnormal service function corresponding to an abnormal condition when detecting that the abnormal condition is caused by a non-aligned access instruction in the process of accessing a memory by a processor, and storing an abnormal address and an abnormal pointer, wherein the abnormal address is an address to be accessed by the non-aligned access instruction, and the abnormal pointer points to the non-aligned access instruction;
the control unit is used for controlling the system to enter the kernel state, exiting the kernel state after the trap task is created, and returning to the system state;
and the execution unit is used for executing the trap task, converting a non-aligned access instruction aiming at an exception address into an aligned access instruction covering the exception address, and executing the aligned access instruction so as to simulate the non-aligned access instruction to realize access to the exception address.
9. A storage medium, characterized in that the storage medium comprises a stored program, wherein the device on which the storage medium is located is controlled to perform the method according to any of claims 1-7 when the program is run.
10. A computing device comprising a processor, wherein the processor is configured to execute a program, wherein the program when executed performs the method of any of claims 1-7.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114003281A (en) * | 2021-11-02 | 2022-02-01 | 武汉深之度科技有限公司 | Hash value-based instruction execution method, computing device and storage medium |
| CN114003280A (en) * | 2021-11-02 | 2022-02-01 | 武汉深之度科技有限公司 | Instruction execution method based on shared thread read-write lock |
| CN114003289A (en) * | 2021-11-02 | 2022-02-01 | 武汉深之度科技有限公司 | Application program running method, computing device and storage medium |
| CN114003284A (en) * | 2021-11-02 | 2022-02-01 | 武汉深之度科技有限公司 | Instruction execution method based on read-write lock, computing device and storage medium |
| CN114003291A (en) * | 2021-11-02 | 2022-02-01 | 武汉深之度科技有限公司 | Application program running method and device, computing equipment and storage medium |
| CN114003397A (en) * | 2021-11-02 | 2022-02-01 | 武汉深之度科技有限公司 | Instruction execution method based on thread read-write lock |
| CN114003290A (en) * | 2021-11-02 | 2022-02-01 | 武汉深之度科技有限公司 | Application program running method and device related to instruction replacement |
| CN114237708A (en) * | 2021-09-23 | 2022-03-25 | 武汉深之度科技有限公司 | Multiprocessor instruction execution method, computing device and storage medium |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104407880A (en) * | 2014-10-27 | 2015-03-11 | 杭州中天微系统有限公司 | RISC (reduced instruction-set computer) processor loading/storage unit supporting non-aligned hardware storage accessing |
| CN110308933A (en) * | 2019-04-25 | 2019-10-08 | 龙芯中科(合肥)技术有限公司 | Access instruction determines method, apparatus and storage medium |
-
2021
- 2021-07-12 CN CN202110784922.6A patent/CN113535451A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104407880A (en) * | 2014-10-27 | 2015-03-11 | 杭州中天微系统有限公司 | RISC (reduced instruction-set computer) processor loading/storage unit supporting non-aligned hardware storage accessing |
| CN110308933A (en) * | 2019-04-25 | 2019-10-08 | 龙芯中科(合肥)技术有限公司 | Access instruction determines method, apparatus and storage medium |
Non-Patent Citations (2)
| Title |
|---|
| JIURA: "深入浅出MIPS 四 MIPS的异常与中断", 《HTTPS://BLOG.CSDN.NET/JIURA/ARTICLE/DETAILS/6645222》, 29 July 2011 (2011-07-29), pages 1 - 7 * |
| KERNELER_: "mips下非对齐访问问题分析", 《HTTPS://BLOG.CSDN.NET/SKYFLYING2012/ARTICLE/DETAILS/17203285》, 8 December 2013 (2013-12-08), pages 1 - 6 * |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114237708A (en) * | 2021-09-23 | 2022-03-25 | 武汉深之度科技有限公司 | Multiprocessor instruction execution method, computing device and storage medium |
| CN114003281A (en) * | 2021-11-02 | 2022-02-01 | 武汉深之度科技有限公司 | Hash value-based instruction execution method, computing device and storage medium |
| CN114003280A (en) * | 2021-11-02 | 2022-02-01 | 武汉深之度科技有限公司 | Instruction execution method based on shared thread read-write lock |
| CN114003289A (en) * | 2021-11-02 | 2022-02-01 | 武汉深之度科技有限公司 | Application program running method, computing device and storage medium |
| CN114003284A (en) * | 2021-11-02 | 2022-02-01 | 武汉深之度科技有限公司 | Instruction execution method based on read-write lock, computing device and storage medium |
| CN114003291A (en) * | 2021-11-02 | 2022-02-01 | 武汉深之度科技有限公司 | Application program running method and device, computing equipment and storage medium |
| CN114003397A (en) * | 2021-11-02 | 2022-02-01 | 武汉深之度科技有限公司 | Instruction execution method based on thread read-write lock |
| CN114003290A (en) * | 2021-11-02 | 2022-02-01 | 武汉深之度科技有限公司 | Application program running method and device related to instruction replacement |
| CN114003290B (en) * | 2021-11-02 | 2024-09-06 | 武汉深之度科技有限公司 | Application program running method and device related to instruction replacement |
| CN114003289B (en) * | 2021-11-02 | 2024-09-10 | 武汉深之度科技有限公司 | Application program running method, computing device and storage medium |
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