CN113991017A - Capacitor array structure, manufacturing method thereof and semiconductor memory device - Google Patents
Capacitor array structure, manufacturing method thereof and semiconductor memory device Download PDFInfo
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- CN113991017A CN113991017A CN202111120106.1A CN202111120106A CN113991017A CN 113991017 A CN113991017 A CN 113991017A CN 202111120106 A CN202111120106 A CN 202111120106A CN 113991017 A CN113991017 A CN 113991017A
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Abstract
The application discloses a manufacturing method of a capacitor array structure, which comprises the following steps: providing a substrate, and forming a sacrificial layer and a support layer which are alternately superposed on the substrate; forming a capacitor hole on a structure covering the substrate; forming a capacitor unit structure in the capacitor hole; after a capacitor unit structure is formed in the capacitor hole, introducing silicon source gas, and forming seed crystal granularity on the surface of the capacitor unit structure; silicon source gas, boron source gas and germanium source gas are introduced in a special gas doubling or multiple times mode to react to form multi-seed crystal granularity, and the multi-seed crystal granularity is diffused in the capacitor hole to form a film so as to form the conductive filling structure. Under the condition that the concentration of a multi-crystal-seed particle size diffusion film-forming is kept unchanged in the capacitor hole by adopting a special gas doubling or multiple mode, the flow of the introduced gas can be doubled, so that the formed conductive filling structure is more compact and uniform in filling the capacitor hole, and the effects of reducing electric leakage and strengthening the capacitor array structure can be realized.
Description
Technical Field
The present invention relates to, but not limited to, the field of semiconductor technologies, and in particular, to a capacitor array structure, a method for manufacturing the same, and a semiconductor memory device.
Background
Dynamic Random Access Memory (DRAM) is a semiconductor Memory device commonly used in computers, and is composed of many repetitive Memory cells. Each memory cell typically includes a capacitor and a transistor; the grid electrode of the transistor is connected with the word line, the drain electrode of the transistor is connected with the bit line, and the source electrode of the transistor is connected with the capacitor; the voltage signal on the word line can control the transistor to be turned on or off, so that data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor through the bit line for storage. Currently, in the DRAM process below 20nm, the DRAM is constructed with a stacked Capacitor (Capacitor) having a vertical high aspect ratio cylinder shape to increase the surface area.
When the conventional method is used to fill the capacitor structure, due to the high aspect ratio structure (height: 1000-.
Disclosure of Invention
The present application aims to provide a capacitor array structure, a method for manufacturing the same, and a semiconductor memory device, which solve the problem in the prior art that when a conventional method is used to fill a capacitor hole, due to a high aspect ratio structure (height: 1000 + 2000nm, CD:30-60nm) of a capacitor, a phenomenon of sealing in advance occurs during filling, which results in generation of voids in the capacitor structure and thus increase of leakage current.
To solve the above technical problem, according to some embodiments, the present application provides a method for manufacturing a capacitor array structure, including: providing a substrate, and forming a sacrificial layer and a support layer which are alternately superposed on the substrate; forming a capacitor hole on a structure covering the substrate; forming a capacitor unit structure in the capacitor hole; after a capacitor unit structure is formed in the capacitor hole, introducing silicon source gas, and forming seed crystal granularity on the surface of the capacitor unit structure; silicon source gas, boron source gas and germanium source gas are introduced in a special gas doubling or multiple times mode to react to form multi-seed crystal granularity, and the multi-seed crystal granularity is diffused in the capacitor hole to form a film so as to form the conductive filling structure.
Preferably, the forming of the capacitor unit structure on the inner wall of the capacitor hole includes: forming a first electrode layer on the inner wall of the capacitor hole; at least one opening formed on the support layer on the alternately stacked sacrificial layers and support layer to open the support layer and remove the sacrificial layers based on the opening; and forming a dielectric layer on the surface of the structure obtained by removing the sacrificial layer, and forming a second electrode layer on the surface of the dielectric layer.
Preferably, one of the openings is formed to overlap only one of the capacitor holes, or one opening is formed to overlap a plurality of the capacitor holes at the same time.
Preferably, an etching stop layer is formed on the surface of the substrate, and the alternately stacked sacrificial layer and support layer are formed on the surface of the etching stop layer.
Preferably, the germanium source gas includes GeH4Or Ge2H6The silicon source gas comprises SiH4、Si2H6Or SiH6At least one of Cl, the boron source gas comprising BCl3Or B2H6At least one of (1).
Preferably, the introducing a silicon source gas after forming the capacitor unit structure in the capacitor hole, and the forming the seed particle size on the surface of the capacitor unit structure includes: the introduced silicon source gas reacts for 10-30 minutes under the first reaction condition, wherein SiH4The flow rate of the gas is 200 standard milliliter per minute to 300 standard milliliter per minute.
Preferably, the step of reacting the introduced silicon source gas for 10 to 30 minutes under the first reaction condition comprises: the reaction temperature is 360-410 ℃, and the pressure for carrying out the reaction is less than 1 torr.
Preferably, the step of introducing the silicon source gas, the boron source gas and the germanium source gas in a manner of doubling or multiplying the amount of the special gas to react to form the polycrystalline grain size comprises: the introduced silicon source gas, boron source gas and germanium source gas react for 10-40 minutes under the second reaction condition, wherein SiH4The flow rate of the gas is 300 standard milliliter per minute to 700 standard milliliter per minute, GeH4The flow rate of the gas is 850 ml/min to 1300 ml/min under standard condition, BCL3The flow rate of the gas is 50 standard milliliter per minute to 200 standard milliliter per minute.
Preferably, the step of reacting the introduced silicon source gas, boron source gas and germanium source gas under the second reaction condition for 10-40 minutes comprises: the reaction temperature is 360-410 ℃, and the pressure for carrying out the reaction is 1-3 torr.
Preferably, a protective layer is formed on the surface of the conductive filling structure, wherein the material of the protective layer comprises polysilicon doped with boron and germanium.
Preferably, the conductive filling structure and the protective layer are prepared in the same reaction chamber, and the germanium source gas for forming the protective layer comprises GeH4Or Ge2H6The silicon source gas comprises SiH4、Si2H6Or SiH6At least one of Cl, the boron source gas comprising BCl3Or B2H6At least one of (1).
Preferably, the forming of the protective layer on the surface of the conductive filling structure includes: reacting at 410-460 ℃ for 3-4 hours, wherein SiH4The flow rate of the gas is 300 standard milliliter per minute to 700 standard milliliter per minute, GeH4The flow rate of the gas is 1250 ml/min-1800 ml/min and BCL3The flow rate of the gas is 50 standard milliliter per minute to 200 standard milliliter per minute, and the pressure for carrying out the reaction is less than 1 torr.
According to other embodiments, the present application also provides a capacitor array structure comprising: the substrate is provided with sacrificial layers and supporting layers which are alternately superposed; a capacitor hole opened on the structure covering the substrate; the capacitor unit structure is formed on the inner wall of the capacitor hole; the conductive filling structure is filled on the surface of the capacitor unit structure, silicon source gas, boron source gas and germanium source gas are introduced in a special gas doubling or multiple-time mode to form multi-seed crystal granularity in the capacitor hole, and the multi-seed crystal granularity is formed by film diffusion in the capacitor hole.
Preferably, the method further comprises the following steps: and the etching stop layer covers the substrate, and the sacrificial layer and the support layer which are alternately overlapped are formed on the surface of the etching stop layer.
Preferably, the method further comprises the following steps: and the protective layer covers the surface of the conductive filling structure.
According to other embodiments, the present application also provides a semiconductor memory device including the capacitor array structure.
Embodiments of the present disclosure have at least the following advantages: the grain size of the crystal seed formed by the silicon source gas on the surface of the capacitor unit structure is inhibited to grow under the low-temperature condition, the uniformity and the compactness can be realized in the process of filling the capacitor hole, the problem of sealing in advance is avoided, and the subsequent germanium-doped polycrystalline silicon can be smoothly filled into the capacitor hole in the environment which is not easy to seal; then silicon source gas, boron source gas and germanium source gas are introduced in a special gas doubling or multiple times manner to react to form multiple crystal seed granularity, so that the polycrystalline silicon reactant doped with germanium can be better diffused into the tiny holes in the capacitor holes, perfect filling of the inside of the capacitor holes is realized, and the effects of reducing electric leakage and strengthening the capacitor array structure can be realized.
Drawings
In order to more clearly illustrate the embodiments of the present application or technical solutions in the conventional technology, the drawings needed to be used in the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a flow chart of a method for fabricating a capacitor array structure according to an embodiment of the present disclosure;
fig. 2A-2L are schematic cross-sectional views of steps of a method for fabricating a capacitor array structure according to an embodiment of the present disclosure;
FIG. 3A is a flow chart of a method for fabricating a conductive fill structure according to an embodiment of the present application;
fig. 3B-3D are schematic cross-sectional views of steps in a method for manufacturing a conductive filling structure according to an embodiment of the present disclosure.
Detailed Description
When the conventional method is used to fill the capacitor structure, due to the high aspect ratio structure (height: 1000-.
In order to solve the above problem, an embodiment of the present application provides a method for manufacturing a capacitor array structure, including: providing a substrate, and forming a sacrificial layer and a support layer which are alternately superposed on the substrate; forming a capacitor hole on the structure of the cover substrate; forming a capacitor unit structure in the capacitor hole; after a capacitor unit structure is formed in the capacitor hole, introducing silicon source gas, and forming seed crystal granularity on the surface of the capacitor unit structure; silicon source gas, boron source gas and germanium source gas are introduced in a special gas doubling or multiple times mode to react to form multi-seed crystal granularity, and the multi-seed crystal granularity is diffused in the capacitor hole to form a film so as to form the conductive filling structure.
Silicon source gas, boron source gas and germanium source gas are introduced in a special gas doubling or multiple times manner to react to form multiple seed crystal granularity, so that the polycrystalline silicon reactant doped with germanium can be better diffused into tiny holes in the capacitor holes, and perfect filling of the inside of the capacitor holes is realized.
The formed capacitor unit structure is an annular capacitor or a cylindrical capacitor, and an annular capacitor (also called a double-sided capacitor, having two capacitors: inner and outer) is formed.
To make the objects, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in the examples of the present application, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not constitute any limitation to the specific implementation manner of the present application, and the embodiments may be combined with each other and cited as reference to each other without contradiction.
Fig. 1 is a flow chart of a method for fabricating a capacitor array structure according to an embodiment of the present disclosure; fig. 2A to fig. 2L are schematic cross-sectional views of steps in a method for manufacturing a capacitor array structure according to an embodiment of the present disclosure. The following describes the manufacturing method of the capacitor array structure provided in this embodiment in further detail with reference to the accompanying drawings, and the specific steps are as follows:
step S11, providing a substrate, and forming a sacrificial layer and a support layer alternately stacked on the substrate.
Referring to fig. 1 and fig. 2A, a detailed process may include forming an etch stop layer 102, a first sacrificial layer 103, a first support layer 104, a second sacrificial layer 105, and a second support layer 106 on a substrate 101 in sequence, wherein the thickness of the first sacrificial layer 103 is greater than the thickness of the second sacrificial layer 105, and the thickness of the second support layer 106 is greater than the thickness of the first support layer 104.
In an example, the materials of the sacrificial layer and the support layer may be the same or different, and in the embodiment of the present application, the material of the sacrificial layer is different from the material of the support layer, and in the same etching process, the etching rate of the sacrificial layer is much greater than that of the support layer, so that when the sacrificial layer is completely removed, the support layer is almost completely retained, thereby playing a role in support.
In another example, the material of the sacrificial layer includes silicon oxide or silicon oxynitride or polysilicon layer, the material of the support layer includes any one or a combination of any two or more of silicon nitride, silicon oxynitride or aluminum oxide, and in the embodiment of the present application, the material of the sacrificial layer is SiO2And the material of the supporting layer is SiN.
In some embodiments, it is known in the art that various methods of forming the support Layer and the sacrificial Layer may be used, such as an Atomic Layer Deposition process (Atomic Layer Deposition) or a Plasma enhanced Chemical Vapor Deposition process (Plasma enhanced Chemical Vapor Deposition).
In this embodiment, it should be noted that the etching stop Layer 102 may be used as an insulating Layer for protecting and isolating other circuits, and preferably, the etching stop Layer 102 is formed by using an Atomic Layer Deposition process (Atomic Layer Deposition) or a Low Pressure Chemical Vapor Deposition process (Low Pressure Chemical Vapor Deposition), and the thickness is preferably between 15nm and 35 nm.
In some embodiments, the material of the substrate 101 may include a semiconductor substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, a single crystal metal oxide substrate, or the like. In this embodiment, the substrate 101 is made of a silicon material, and the silicon material is used as the substrate 101 in this embodiment to facilitate understanding of a subsequent forming method by a person skilled in the art, and is not limited to this embodiment.
Step S12, forming a patterned mask layer on the structure obtained in step S11, and etching the sacrificial layer and the support layer to form a capacitor hole based on the patterned mask layer.
Referring to fig. 1 and fig. 2B, in detail, a photoresist layer may be coated on a surface region of the formed second supporting layer 106, in other embodiments, other mask layers (such as a silicon nitride hard mask layer and the like) may also be formed, and the mask layer is patterned by using a photolithography process to sequentially form a patterned first mask layer 107 and a patterned second mask layer 108 on the surface region of the second supporting layer 106, in this embodiment, it is to be noted that the structure covering the substrate 101 is etched by using the formed first mask layer 107 and the formed second mask layer 108 as masks through an etching process until the etching stop layer 102 is exposed, and the first mask layer 107 and the second mask layer 108 are removed to form the capacitor hole 109, as shown in fig. 2C. Fig. 2D is a top view of the capacitor after etching in the related art, and the arrangement of the capacitor holes 109 is shown in fig. 2D.
Step S13, after forming the capacitor hole, depositing titanium nitride on the inner wall of the capacitor hole to form a first electrode layer.
Referring to fig. 1, 2C and 2E, the detailed process may include depositing a bottom electrode material Layer on the sidewalls and bottom of the capacitor hole 109 and on the top surface of the second support Layer 106 by using an Atomic Layer Deposition (Atomic Layer Deposition) process or a plasma Chemical Vapor Deposition (Chemical Vapor Deposition) process, wherein the bottom electrode material Layer includes a compound formed by one or both of a metal Nitride and a metal Silicide, such as Titanium Nitride (ti Nitride), Titanium Silicide (ti Silicide), nickel Silicide (ti Silicide) and Titanium silicon Nitride (TiSixNy), and preferably, the material of the bottom electrode material Layer is Titanium Nitride (ti in this embodiment). After the lower electrode material layer is formed, the lower electrode material layer on the upper surface of the second support layer 106 is removed by using chemical mechanical polishing or etching, and the lower electrode material layer remaining on the sidewall and the bottom of the capacitor hole 109 is the first electrode layer 110 (see fig. 2E).
Step S14, a patterned third mask layer with openings is formed on the surface region of the second support layer, and the second support layer is etched based on the third mask layer to form the first openings on the second support layer.
In detail, with continued reference to fig. 1 and fig. 2F, a patterned third mask layer 111 having an opening is formed on a surface region of the second support layer 106, wherein the opening defines a position and a shape of the first opening on the second support layer 106, and the second support layer 106 is etched based on the third mask layer 111 to form a first opening 112 (see fig. 2G) on the second support layer 106, and a bottom of the first opening 112 exposes a top region of the second sacrificial layer 105.
Alternatively, as an example, the first openings 112 formed in step S14 are arranged at regular intervals, and one first opening 112 overlaps only one capacitor hole 109, or one first opening 112 overlaps a plurality of capacitor holes 109 at the same time, as shown in fig. 2H, taking as an example that one first opening 112 overlaps three capacitor holes 109. Fig. 2H is a plan view of the second support layer 106 having the first opening 112, and the positional relationship between the first opening 112 and the capacitor hole 109 is shown in fig. 2H. With continued reference to fig. 1 and fig. 2I, the second sacrificial layer 105 between the first support layer 104 and the second support layer 106 is removed by a wet etching process according to the first opening 112. The second support layer 106 with the first opening 112 formed by the method has a proper opening position, which is not only beneficial to wet etching of the sacrificial layer, but also can ensure enough support strength.
Step S15 is to form a second opening on the first support layer based on the first opening and remove the first sacrificial layer.
Referring to fig. 1 and fig. 2I, a detailed process may include forming a second opening 113 on the first supporting layer 104 based on the first opening 112, as shown by a dashed line in fig. 2I, where fig. 2J is a cross-sectional view of the first supporting layer with the second opening, and a positional relationship between the second opening 113 and the capacitor hole 109 is shown in fig. 2J. The first sacrificial layer 103 between the etch stop layer 102 and the first support layer 104 is removed using a wet etching process according to the second opening 113.
Step S16, a dielectric layer is formed on the surface of the structure obtained in step S15, and a second electrode layer is formed on the surface of the dielectric layer.
In detail, please refer to fig. 1 and fig. 2K, a dielectric layer 114 is formed on the inner and outer surfaces of the first electrode layer 110 and the surfaces of the first support layer 104 and the second support layer 106 on the inner wall of the capacitor hole 109, wherein the dielectric layer 114 is selected from strontium titanate (SrTiO)3) And titanium oxide (TiO)2) Laminated structure of the composition, alumina (Al)2O3) And hafnium oxide (HfO) and a composite perovskite-type ferroelectric material (BST material, ferroelectric material of composite perovskite structure, made of BaTiO3And SrTiO3Solid solution composed in a certain proportion).
Forming a second electrode Layer 115 on the surface of the dielectric Layer 114, in some embodiments, forming the dielectric Layer 114 and the second electrode Layer 115 by an Atomic Layer Deposition (Atomic Layer Deposition) process or a Chemical Vapor Deposition (Chemical Vapor Deposition) process or a Physical Vapor Deposition (Physical Vapor Deposition) process, wherein the material of the second electrode Layer 115 includes a compound formed by one or both of a metal Nitride and a metal Silicide, such as Titanium Nitride (Titanium Nitride), Titanium Silicide (Titanium Silicide), nickel Silicide (Titanium Silicide), Titanium silicon Nitride (Titanium Nitride), and metal electrode material can be Ru (ruthenium), Pt (platinum), Ir (iridium), Pd (palladium), or metal oxide such as RuO (ruthenium oxide), or metal electrode material can be conductive material such as Titanium Nitride (Titanium Nitride), Titanium Silicide, or metal oxide (Titanium Nitride (Titanium oxide), or metal electrode material can be conductive material such as Ru (ruthenium), Pt (platinum), Ir (iridium), Pd (palladium), or metal oxide such as RuO (ruthenium oxide)2(ruthenium oxide), IrO2(iridium oxide), and the like.
In step S17, a conductive filling structure is formed on the surface of the second electrode layer, and the conductive filling structure fills the gap between the adjacent second electrode layers and is electrically connected to the second electrode layers.
As shown in fig. 2L, in detail, a conductive filling structure may be formed on the second electrode layer 115 in the gap between the adjacent second electrode layers 115.
FIG. 3A is a flow chart of a method for fabricating a conductive fill structure according to an embodiment of the present application; fig. 3B-3D are schematic cross-sectional views of steps in a method for manufacturing a conductive filling structure according to an embodiment of the present disclosure. The manufacturing method of the conductive filling structure specifically comprises the following steps:
in step S171, a seed grain size is formed in the capacitor hole under the first reaction condition.
As shown in fig. 3A and 3B: specifically, the conductive filling structure obtained in step S17 may be placed in a chemical vapor deposition furnace tube, a silicon source gas is introduced into the chemical vapor deposition furnace tube, and the silicon source gas reacts for 10 to 30 minutes under the first reaction condition, so as to form the seed crystal grain size 117 on the outer surface of the second electrode layer 115 in the capacitor hole 109. Wherein the introduced silicon source gas comprises SiH4、Si2H6Or SiH6At least one of Cl, in the embodiment of the application, a silicon source gas is SiH4For illustration, in one example, the first reaction conditions specifically include: the temperature is set to 360-410 ℃, the reaction pressure is controlled to be less than 1torr, wherein, SiH4The flow rate of the gas is 200 standard milliliter per minute to 300 standard milliliter per minute.
In the embodiment of the application, the silicon source gas is introduced into the process of filling the capacitor hole 109, the silicon source gas forms the seed crystal granularity 117 on the outer surface of the second electrode layer 115 under the first reaction condition, and the temperature in the first reaction condition is reduced to 360-410 ℃, so that the formed seed crystal granularity 117 is inhibited to grow up in the capacitor hole 109 at a lower temperature, therefore, in the process of filling the capacitor hole 109, the uniformity and the compactness can be realized, the problem of sealing in advance can not occur, and the subsequent germanium-doped polycrystalline silicon can be smoothly filled into the capacitor hole 109 in an environment which is not easy to seal.
In other embodiments, the formed seed grain size 117 is also located on the upper surface of the second support layer 106 around the capacitive aperture 109.
And step S172, diffusing the polycrystalline grain size in the capacitor hole under a second reaction condition to form a film so as to form a conductive filling structure.
As shown in fig. 3A and 3C, the conductive filling structure may include a filling conductive layer 116, wherein the filling conductive layer 116 fills the hole of the capacitor hole 109 and also extends to cover the upper surface of the second supporting layer 106 around the capacitor hole 109.
In some embodiments, a silicon source gas, a boron source gas, and a germanium source gas are introduced into the cvd furnace tube in a double or multiple manner to react for 10-40 minutes under the second reaction condition, so as to form a multi-seed grain size in the capacitor hole 109, and the multi-seed grain is diffused to form a film to form the filled conductive layer 116. Under the condition that the concentration of the multi-crystal-seed particle size diffusion film-forming is kept unchanged in the capacitor hole 109 by adopting a special gas doubling or multiple mode, the flow of the introduced gas can be doubled, so that the high-pressure condition of the chemical vapor deposition furnace tube machine is realized.
Wherein the introduced silicon source gas comprises SiH4、Si2H6Or SiH6At least one of Cl, a germanium source gas including GeH4、Ge2H6Wherein the boron source gas comprises BCl3、B2H6In the present embodiment, the silicon source gas is SiH4Germanium source gas and GeH4The boron source gas is BCl3The description is given for the sake of example. In the present application, a boron-doped germanium-silicon layer is used as the filled conductive layer 116, and germanium is present in the filled conductive layer 116, which can increase the carrier mobility, so as to reduce the resistance of the filled conductive layer 116.
Introducing silicon source gas, boron source gas and germanium source gas in a special gas doubling or multiple times manner to react for 10-40 minutes under a second reaction condition, wherein the second reaction condition is specificThe method comprises the following steps: the temperature is 360-410 ℃, the reaction pressure is controlled to be 1-3 torr, wherein SiH4The flow rate of the gas is 300 standard milliliter per minute to 700 standard milliliter per minute, GeH4The flow rate of the gas is 850 ml/min to 1300 ml/min under standard conditions, BCl3The flow rate of the gas is 50 standard milliliter per minute to 200 standard milliliter per minute. Wherein GeH4The flow rate of the gas is 850 ml/min to 1300 ml/min, and the low concentration GeH4The film can be formed in the capacitor hole 109 with a small crystal grain size, and the film can be formed more densely when the capacitor hole 109 is filled.
According to the embodiment of the application, silicon source gas is introduced simultaneously, boron source gas and germanium source gas react under the second reaction condition, the reaction temperature of 360-410 ℃ in the second reaction condition and the reaction temperature of 360-410 ℃ in the first reaction condition are controlled to be kept unchanged, the reaction pressure is increased to 1-3 torr simultaneously, the polycrystalline silicon reactant doped with germanium is enabled to be diffused into the tiny holes in the capacitor holes 109 better, perfect filling of the interior of the capacitor holes 109 is achieved, electric leakage reduction can be achieved, and the effect of the capacitor array structure is enhanced.
Step S173, forming a protection layer on the surface of the filled conductive layer under a third reaction condition.
As shown in fig. 3A and 3D, the method may further include forming a protection layer 118 for preventing germanium in the filled conductive layer 116 from affecting subsequent processes, wherein the protection layer 118 is made of polysilicon doped with boron and germanium, the protection layer 118 and the filled conductive layer 116 are prepared in the same chamber, and the germanium source gas for forming the protection layer 118 includes GeH4Or Ge2H6The silicon source gas comprises SiH4、Si2H6Or SiH6At least one of Cl, boron source gas including BCl3Or B2H6At least one of (1). In the embodiment of the application, germanium source gas is used as GeH4The silicon source gas is SiH4And the boron source gas is BCl3For example, the third reaction condition comprises reacting at 410-460 ℃ for 3-4 hours under a pressure of less than 1torr,in which SiH4The flow rate of the gas is 300 standard milliliter per minute to 700 standard milliliter per minute, GeH4The flow rate of the gas is 1250 ml/min-1800 ml/min and BCl3The flow rate of the gas is 50 standard milliliter per minute to 200 standard milliliter per minute. In this step, GeH is introduced4The flow rate of the gas is 1250 standard milliliter per minute to 1800 standard milliliter per minute, GeH4The germanium can increase the carrier mobility, thereby reducing the resistance of the filled conductive layer 116, and increasing the GeH4The flow of gas may reduce the resistance of the formed capacitor.
Example two
With reference to fig. 2L in combination with the first embodiment, an embodiment of the present invention further provides a capacitor array structure manufactured by the manufacturing method of the first embodiment, the capacitor array structure is disposed on a substrate 101, and a sacrificial layer and a supporting layer are disposed on the substrate 101 in an alternating stacking manner; the sacrificial layer comprises a first sacrificial layer 103 and a second sacrificial layer 105, and the support layer comprises a first support layer 104 and a second support layer 106; a first sacrificial layer 103, a first support layer 104, a second sacrificial layer 105, and a second support layer 106 are sequentially formed on the substrate 101 in an overlapping manner. An etch stop layer 102 is also formed between the first sacrificial layer 103 and the substrate 101, and the etch stop layer 102 may serve as an insulating layer for protecting and isolating other lines.
A capacitor hole 109 which is opened in the first sacrificial layer 103, the first support layer 104, the second sacrificial layer 105 and the second support layer 106 and exposes the etching stop layer 102;
the capacitor array structure comprises a first electrode layer 110, wherein the first electrode layer 110 is deposited on the inner wall of the capacitor hole 109; a dielectric layer 114, wherein the dielectric layer 114 covers the surface of the first electrode layer 110; and the second electrode layer 115 covers the surface of the dielectric layer 114.
The conductive filling structure includes a filling conductive layer 116 covering the outer surface of the second electrode layer 115, filling the gap between adjacent second electrode layers 115, and electrically connecting to the second electrode layers 115. The material of the filling conductive layer 116 includes a boron-doped silicon germanium (B-doped SiGe). The filling conductive layer 116 is formed by forming multiple seed grain sizes in the capacitor hole 109 by doubling or multiplying the specific gas, and then diffusing the seed grain sizes to form a film and fill the film on the surface of the capacitor unit structure.
As an example, the capacitor array structure further includes a protection layer 118, and the protection layer 118 covers the surface of the filled conductive layer 116. Optionally, the material of the protection layer 118 includes polysilicon doped with boron and germanium. By way of example, dielectric layer 114 is a high-K dielectric layer to increase capacitance per area capacitor, and includes strontium titanate (SrTiO)3) And titanium oxide (TiO)2) A laminated structure composed of aluminum oxide (AlO) and hafnium oxide (HfO).
EXAMPLE III
Correspondingly, the embodiment of the application also provides a semiconductor memory device structure, and the semiconductor memory device structure comprises the capacitor array structure as described in the second embodiment. By way of example, the semiconductor memory device structure may be, but is not limited to, a Dynamic Random Access Memory (DRAM).
In summary, in the embodiment of the disclosure, the grain size of the seed crystal formed on the surface of the conductive layer by the introduced silicon source gas is inhibited from growing at the reaction temperature of 360-410 ℃, and during the process of filling the capacitor hole, uniformity and compactness can be achieved without the problem of sealing in advance, so that the subsequent germanium-doped polysilicon can be smoothly filled into the capacitor hole in an environment where sealing is difficult; then, under the reaction pressure of 1-3 torr, silicon source gas, boron source gas and germanium source gas are simultaneously introduced in a special gas doubling or multiple mode to react under the high-pressure condition, parameters in the second reaction condition are controlled, so that the germanium-doped polycrystalline silicon reactant can be better diffused into the tiny holes in the capacitor holes, perfect filling of the inner parts of the capacitor holes is realized, and the effects of reducing electric leakage and strengthening the capacitor array structure can be realized.
It is to be understood that the above-described embodiments of the present application are merely illustrative of or illustrative of the principles of the present application and are not to be construed as limiting the present application. Therefore, any modification, equivalent replacement, improvement and the like made without departing from the spirit and scope of the present application shall be included in the protection scope of the present application. Further, it is intended that the appended claims cover all such changes and modifications that fall within the scope and range of equivalents of the appended claims, or the equivalents of such scope and range.
Claims (16)
1. A method of fabricating a capacitor array structure, comprising:
providing a substrate, and forming a sacrificial layer and a support layer which are alternately superposed on the substrate;
forming a capacitor hole on a structure covering the substrate;
forming a capacitor unit structure in the capacitor hole;
after a capacitor unit structure is formed in the capacitor hole, introducing silicon source gas, and forming seed crystal granularity on the surface of the capacitor unit structure;
silicon source gas, boron source gas and germanium source gas are introduced in a special gas doubling or multiple times mode to react to form multi-seed crystal granularity, and the multi-seed crystal granularity is diffused in the capacitor hole to form a film so as to form the conductive filling structure.
2. The method of claim 1, wherein forming a capacitor cell structure in the capacitor hole comprises:
forming a first electrode layer on the inner wall of the capacitor hole;
at least one opening formed on the support layer on the alternately stacked sacrificial layers and support layer to open the support layer and remove the sacrificial layers based on the opening;
and forming a dielectric layer on the surface of the structure obtained by removing the sacrificial layer, and forming a second electrode layer on the surface of the dielectric layer.
3. The manufacturing method according to claim 2,
one of the openings is formed to overlap only one of the capacitor holes, or one opening is formed to overlap a plurality of the capacitor holes at the same time.
4. The manufacturing method according to claim 2, wherein an etching stop layer is formed on the surface of the substrate, and the alternately stacked sacrificial layer and support layer are formed on the surface of the etching stop layer.
5. The manufacturing method according to claim 1,
the germanium source gas comprises GeH4Or Ge2H6The silicon source gas comprises SiH4、Si2H6Or SiH6At least one of Cl, the boron source gas comprising BCl3Or B2H6At least one of (1).
6. The manufacturing method according to claim 5,
introducing a silicon source gas after forming a capacitor unit structure in the capacitor hole, wherein the step of forming the seed crystal granularity on the surface of the capacitor unit structure comprises the following steps:
the introduced silicon source gas reacts for 10-30 minutes under the first reaction condition, wherein SiH4The flow rate of the gas is 200 standard milliliter per minute to 300 standard milliliter per minute.
7. The method of claim 6, wherein reacting the introduced silicon source gas under the first reaction condition for 10 to 30 minutes comprises:
the reaction temperature is 360-410 ℃, and the pressure for carrying out the reaction is less than 1 torr.
8. The manufacturing method according to claim 7,
the method for introducing the silicon source gas, the boron source gas and the germanium source gas in a special gas doubling or multiple times mode to react to form the polycrystalline grain size comprises the following steps:
the introduced silicon source gas, boron source gas and germanium source gas react for 10-40 minutes under the second reaction condition, wherein SiH4The flow rate of the gas is 300 standard milliliter per minute to 700 standard milliliter per minute,GeH4The flow rate of the gas is 850 ml/min to 1300 ml/min under standard condition, BCL3The flow rate of the gas is 50 standard milliliter per minute to 200 standard milliliter per minute.
9. The method according to claim 8, wherein reacting the introduced silicon source gas, boron source gas, and germanium source gas under the second reaction condition for 10 to 40 minutes comprises:
the reaction temperature is 360-410 ℃, and the pressure for carrying out the reaction is 1-3 torr.
10. The manufacturing method according to claim 9,
and forming a protective layer on the surface of the conductive filling structure, wherein the material of the protective layer comprises polysilicon doped with boron and germanium.
11. The manufacturing method according to claim 10,
the conductive filling structure and the protective layer are prepared in the same reaction chamber, and the germanium source gas for forming the protective layer comprises GeH4Or Ge2H6The silicon source gas comprises SiH4、Si2H6Or SiH6At least one of Cl, the boron source gas comprising BCl3Or B2H6At least one of (1).
12. The manufacturing method according to claim 11,
forming a protective layer on the surface of the conductive filling structure comprises:
reacting at 410-460 ℃ for 3-4 hours, wherein SiH4The flow rate of the gas is 300 standard milliliter per minute to 700 standard milliliter per minute, GeH4The flow rate of the gas is 1250 ml/min-1800 ml/min and BCL3The flow rate of the gas is 50 standard milliliter per minute to 200 standard milliliter per minute, and the pressure for carrying out the reaction is less than 1 torr.
13. A capacitor array structure, comprising:
the substrate is provided with sacrificial layers and supporting layers which are alternately superposed;
a capacitor hole opened on the structure covering the substrate;
a capacitor unit structure formed in the capacitor hole;
the conductive filling structure is filled on the surface of the capacitor unit structure, silicon source gas, boron source gas and germanium source gas are introduced in a special gas doubling or multiple-time mode to form multi-seed crystal granularity in the capacitor hole, and the multi-seed crystal granularity is formed by film diffusion in the capacitor hole.
14. The array structure of claim 13, further comprising:
and the etching stop layer covers the substrate, and the sacrificial layer and the support layer which are alternately overlapped are formed on the surface of the etching stop layer.
15. The array structure of claim 14, further comprising:
and the protective layer covers the surface of the conductive filling structure.
16. A semiconductor memory device characterized by comprising the capacitor array structure according to claim 13.
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| CN202111120106.1A CN113991017A (en) | 2021-09-18 | 2021-09-18 | Capacitor array structure, manufacturing method thereof and semiconductor memory device |
| PCT/CN2021/130797 WO2023040030A1 (en) | 2021-09-18 | 2021-11-16 | Capacitor array structure, fabrication method therefor and semiconductor memory device |
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| CN202111120106.1A CN113991017A (en) | 2021-09-18 | 2021-09-18 | Capacitor array structure, manufacturing method thereof and semiconductor memory device |
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| CN116056558A (en) * | 2023-03-28 | 2023-05-02 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and structure thereof |
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| KR100634241B1 (en) * | 2005-05-30 | 2006-10-13 | 삼성전자주식회사 | Semiconductor capacitor and method of manufacturing the same |
| KR100655691B1 (en) * | 2005-09-21 | 2006-12-08 | 삼성전자주식회사 | Capacitor and method of manufacturing the same |
| JP2013089889A (en) * | 2011-10-21 | 2013-05-13 | Elpida Memory Inc | Semiconductor device and method for manufacturing the same |
| JP6624998B2 (en) * | 2016-03-30 | 2019-12-25 | 東京エレクトロン株式会社 | Method and apparatus for forming boron-doped silicon germanium film |
| CN107910327A (en) * | 2017-11-07 | 2018-04-13 | 睿力集成电路有限公司 | Array of capacitors structure and its manufacture method |
| CN107968044B (en) * | 2017-12-19 | 2024-02-09 | 长鑫存储技术有限公司 | Capacitor array structure, semiconductor memory and preparation method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116056558A (en) * | 2023-03-28 | 2023-05-02 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and structure thereof |
| CN116056558B (en) * | 2023-03-28 | 2023-08-29 | 长鑫存储技术有限公司 | Manufacturing method of semiconductor structure and structure thereof |
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