CN113990951A - 半导体结构 - Google Patents

半导体结构 Download PDF

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Publication number
CN113990951A
CN113990951A CN202110026057.9A CN202110026057A CN113990951A CN 113990951 A CN113990951 A CN 113990951A CN 202110026057 A CN202110026057 A CN 202110026057A CN 113990951 A CN113990951 A CN 113990951A
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epitaxial layer
layer
dielectric
substrate
epitaxial
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CN202110026057.9A
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摩尔·沙哈吉·B
蔡俊雄
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本揭示案是关于一种半导体结构，包括：一基板；一介电质，在该基板上；一磊晶层，安置在该介电质上且包括一第一区域及一第二区域，其中该磊晶层的侧壁与该介电质的侧壁对准；一源极/漏极结构，安置在该磊晶层的该第一区域上；一垂直堆叠，包括安置在该磊晶层的该第二区域之上的纳米薄片层；以及一栅极堆叠，安置在该磊晶层的该第二区域上且环绕该垂直堆叠的这些纳米薄片层。

Description

半导体结构
技术领域
本揭露涉及一种半导体结构及其制造方法。
背景技术
基于鳍片的场效应晶体管(finFET)中的源极/漏极区域是自鳍片结构的侧表面及其上形成有鳍片结构的半导体基板的顶表面生长。在操作期间，可能在源极/漏极区域与半导体基板之间形成寄生接面电容，此会使finFET的效能降级。
发明内容
根据本揭露的一些实施例中，一种半导体结构包括：一基板；一介电质，在该基板上；一磊晶层，安置在该介电质上且包括一第一区域及一第二区域，其中该磊晶层的侧壁与该介电质的侧壁对准；一源极/漏极结构，安置在该磊晶层的该第一区域上；一垂直堆叠，包括安置在该磊晶层的该第二区域之上的纳米薄片层；以及一栅极堆叠，安置在该磊晶层的该第二区域上且环绕该垂直堆叠的这些纳米薄片层。
附图说明
当结合随附诸图阅读时，得以自以下详细描述最佳地理解本揭示案的态样。
图1为根据一些实施例的在局部隔离结构之上的环绕式栅极纳米薄片FET的横截面图；
图2为根据一些实施例的在局部隔离结构之上的环绕式栅极纳米薄片FET的横截面图；
图3A至图3B为根据一些实施例的用于制造在环绕式栅极纳米薄片FET之下的局部隔离结构的方法的流程图；
图4为根据一些实施例的在制造环绕式栅极纳米薄片FET之下的局部隔离结构期间的中间结构的等角视图；
图5至图12B为根据一些实施例的在制造环绕式栅极纳米薄片FET之下的局部隔离结构期间的中间结构的横截面图；
图12C为根据一些实施例的形成于具有交替纳米薄片层的鳍片结构之下的局部隔离结构的等角视图；
图13A及图13B为根据一些实施例的用于制造在环绕式栅极纳米薄片FET之下的局部隔离结构的方法的流程图；
图14至图16A为根据一些实施例的在制造环绕式栅极纳米薄片FET之下的局部隔离结构期间的中间结构的等角视图；
图16B至图19A为根据一些实施例的在制造环绕式栅极纳米薄片FET之下的局部隔离结构期间的中间结构的横截面图；
图19B为根据一些实施例的在制造环绕式栅极纳米薄片FET之下的局部隔离结构期间的中间结构的等角视图。
【符号说明】
100:环绕式栅极场效应晶体管(GAA FET)
110:磊晶层
110t:厚度
115:局部隔离结构
120:基板
125:源极/漏极(S/D)磊晶结构
130:纳米薄片(NS)/纳米线(NW)/NS层
135:间隔物结构
140:栅极堆叠
145:界面层(IL)
150:高介电常数介电质
155:栅电极
160:栅极间隔物
165:层间介电质(ILD)
200:隔离结构
205:磊晶层
205t:厚度
300:制造方法
305:操作
310:操作
315:操作
320:操作
325:操作
330:操作
335:操作
340:操作
400:第一磊晶层
405:第二磊晶层
410:图案化结构
500:沟槽开口
600:缝隙
700:第一介电质
710:气穴或空隙
900:内衬
905:第三磊晶层
1100:堆叠
1105:NS层
1200:鳍片结构
1205:封盖层
1210:第二介电质
1215:浅沟槽隔离(STI)结构
1300:制造方法
1305:操作
1310:操作
1315:操作
1320:操作
1325:操作
1330:操作
1335:操作
1340:操作
1345:操作
1350:操作
1500:开口
1800:鳍片结构
1900:第二介电质
1905:浅沟槽隔离(STI)结构
1910:凹陷部分
具体实施方式
以下揭示内容提供用于实施所提供标的的不同特征的许多不同实施例或实例。以下描述部件及布置的特定实例以简化本揭示案。当然，此些仅为实例，且并不意欲为限制性的。举例而言，在以下描述中第一特征在第二特征之上形成可包括其中第一特征及第二特形成为直接接触的实施例，且亦可包括其中可形成在第一特征与第二特征之间的额外特征而使得第一特征与第二特征不直接接触的实施例。
另外，为了描述简单，可在本文中使用诸如“在……下面”、“在……下方”、“下部”、“在……上方”、“上部”及其类似术语的空间相对术语，以描述如诸图中所绘示的一个元件或特征与另一(另外)元件或特征的关系。除了诸图中所描绘的定向以外，此些空间相对术语意欲涵盖元件在使用中或操作中的不同定向。装置可以其他方式定向(旋转90度或以其他定向)，且可同样相应地解释本文中所使用的空间相对描述词。
如本文中所使用，术语“标称”代表在产品或制程的设计阶段期间设定的部件或制程操作的特性或参数的期望值或目标值，以及高于及/或低于此期望值的值的范围。值的此范围可归因于制造制程或容限的微小变化。
在一些实施例中，术语“约”及“大体上”可指示给定量的值在此值的5％(例如，此值的±1％、±2％、±3％、±4％、±5％)、此值的5％至10％、此值的10％至20％等之内变化。此些值仅为实例，且并不意欲为限制性的。应理解，术语“约”及“大体上”可代表如由熟悉(若干)相关技术者根据本文中教示所解释的值的百分比。
如本文中所使用，术语“垂直”意谓名义上垂直于基板的表面。
如本文中所使用，术语“绝缘层”代表用作电绝缘体(例如，介电层)的层。
与栅极结构覆盖半导体鳍片结构的侧壁部分及顶表面的其他类型的FET相比较而言，环绕式栅极(GAA)场效应晶体管(GAA-FET)(诸如，纳米薄片或纳米线GAA-FET)具有对其通道区域的改良的栅极控制。由于其环绕式栅极的几何形状，GAA FET实现了更大的有效通道宽度及更高的驱动电流。同时，GAA FET的独特几何形状使得其易于受漏电流及寄生接面电容影响。举例而言，包裹FET的纳米薄片或纳米线的栅电极形成为紧邻半导体基板。因此，在GAA FET的操作期间，可能在半导体基板内在生长于半导体基板上的源极/漏极端之间形成寄生通道。此寄生通道可使GAA FET的效能降级并增大其功耗。为了抑制寄生通道形成，半导体基板为“反掺杂的”—例如，通过与用于通道区域的掺杂剂类型相反的掺杂剂类型来掺杂。掺杂半导体基板增加了制造制程的成本及/或可能无法有效地消除或抑制寄生通道形成。除了反掺杂以外，GAA FET可形成在绝缘层上硅晶(silicon-on-insulator,SOI)基板上，与块体基板相比较而言，绝缘层上硅晶(SOI)基板可减少寄生电容形成及漏电流的出现。然而，SOI基板比块体半导体更昂贵，且其实施增大了制造成本。
本文中所描述的实施例是针对用于制造具有低功耗的纳米结构晶体管(如GAA纳米薄片或纳米线FET，其统称为“GAA FET”)的方法。在一些实施例中，通过在GAA FET之下的块体基板上形成局部介电层而实现低功耗。局部介电质与SOI基板相比较而言提供了元件隔离，而不会增加SOI基板的制造成本。在一些实施例中，局部介电层形成在GAA FET的源极/漏极磊晶结构下方的区域中。根据一些实施例，局部介电层包括氧化硅。在一些实施例中，在形成GAA结构之前，可在块体基板上沉积硅-锗/硅双层或硅-砷/硅双层。在一些实施例中，可将锗或砷布植在硅基板中以形成前述双层。随后，经由形成在双层中的开口选择性地移除硅-锗(或硅-砷)层的部分并用介电层替代，以在源极/漏极磊晶结构下方或在整个GAA FET结构之下形成局部介电结构。在一些实施例中，本文所述方法并不限于GAA FET，且可应用于其他类型的晶体管，诸如，finFET。
根据一些实施例，图1为形成在磊晶层110上的GAA FET 100的横截面图，此磊晶层110又安置在局部隔离结构115上。另外，局部隔离结构115形成在基板120上。GAA FET 100的特征在于形成在磊晶层110的凹陷部分上的源极/漏极(source/drain,S/D)磊晶结构125(以下称S/D磊晶结构125)。刚形成的S/D磊晶结构125邻接GAA FET 100的半导体纳米薄片(nano-sheet,NS)或纳米线(nano-wire,NW)130。NS或NW 130通过间隔物结构135垂直地(例如，在z方向上)分离且被栅极堆叠140环绕。举例而言且并非限制，栅极堆叠140包括界面层(IL)145、高介电常数介电质150及栅电极155。在一些实施例中，栅电极155进一步包括图1中未示出的功函数层及金属填充层。如图1中所示，栅极堆叠140通过栅极间隔物160及层间介电质(interlayer dielectric,ILD)165与相邻导电结构(诸如，图1中未示出的S/D接触件)电隔离。
根据一些实施例，局部隔离结构115在GAA FET 100之下延伸。在一些实施例中，局部隔离结构115局部地在GAA FET 100周围形成—与全域地在基板120(例如，具有形成为覆盖基板120的整个表面的内埋式氧化物(buried oxide,BOX)层的SOI基板)的整个表面上相反。
在一些实施例中，磊晶层110具有在NS或NW 130下方的厚度110t，其被量测为在约5nm与约100nm之间。在一些实施例中，如图1中所示，磊晶层110可在S/D磊晶结构125之下较薄(例如，凹陷)。此磊晶层110布置并非限制性的；磊晶层110可在整个GAA FET 100之上具有大体上恒定的厚度。在一些实施例中，厚于约100nm的磊晶层110会引发对GAA FET 100的不当的机械应力，此可能对GAA FET 100的操作不利。
根据一些实施例，取决于形成于磊晶层110上的晶体管的类型，磊晶层110可为本征的(例如，未掺杂)或掺杂的。举例而言，磊晶层110可在其上形成有GAA FET(如GAA FET100)时为本征的(例如，未掺杂)，且在其上形成有finFET时为掺杂的。举例而言且并非限制，磊晶层110中的掺杂浓度的范围可为自约1×1018掺杂剂/cm3至约5×1019掺杂剂/cm3。
根据一些实施例，局部隔离结构115的存在抑制了S/D磊晶结构125与基板120之间寄生电容的形成。另外，局部隔离结构115限制了漏电流的出现。出于此原因，当操作时，GAAFET 100具有减小的功耗。
在一些实施例中，局部隔离结构115包括基于硅的介电材料，诸如，氧化硅。在一些实施例中，可将其他介电材料用于局部隔离结构115。举例而言，具有比氧化硅高的介电常数的介电材料，诸如，氮化硅、氧氮化硅及硅碳氮化物。取决于形成在局部隔离结构115之上的晶体管的类型，局部隔离结构115可具有约5nm与约100nm之间的厚度。举例而言，与finFET相比较而言，GAA FET(例如，如GAA FET 100)可能需要较薄的局部隔离结构115。在一些实施例中，比约5nm薄的隔离结构115提供不足的防寄生电容及漏电流的保护。举例而言，具有小于5nm的厚度的隔离结构115无法提供GAA FET100与基板120之间的充分电隔离。在一些实施例中，厚于约100nm的隔离结构115提供足够的电隔离，但是不必要地厚。因此，厚于约100nm的隔离结构115增大了制造复杂性及成本。
根据一些实施例，图2为形成在隔离结构200之上的GAA FET 100的横截面图，此隔离结构200在S/D磊晶结构125下方。在一些实施例中，不同于隔离结构115，此些隔离结构限于基板120的在S/D磊晶结构125下方的区域。隔离结构200不在栅极堆叠140下方延伸。实情为，隔离结构200通过磊晶层205分离开，此磊晶层205根据一些实施例在隔离结构200之间形成间隔S。隔离结构200可具有与隔离结构115相同的厚度—例如，在约5nm与约100nm之间。另外，隔离结构200及隔离结构115可由同一材料制成，例如，氧化硅。
如图2中所示，磊晶层205部分地被局部隔离结构200、栅极堆叠140的底部部分及基板120环绕。磊晶层205(其在一些实施例中具有约5nm与约100nm之间的厚度205t)促进了隔离结构200的形成。磊晶层205可被视为基板120的“延伸部”，即使磊晶层205为生长在基板120的顶部上而非由基板120形成(例如，经由蚀刻)的层。类似于磊晶层110，磊晶层205在S/D磊晶结构125之下延伸。
根据一些实施例，图1及图2中所示的磊晶层110及205可由与基板120类似的材料制成。磊晶层110及205可由与基板120的材料不同的材料制成。举例而言且并非限制，基板120及磊晶层110/205可包括结晶硅(Si)或另一元素半导体，诸如，锗(Ge)。或者，基板120及磊晶层110/205可包括(i)化合物半导体，如碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)及/或锑化铟(InSb)；(ii)合金半导体，如硅-锗(SiGe)、镓砷磷(GaAsP)、铝铟砷(AlInAs)、铝镓砷(AlGaAs)、镓铟砷(GaInAs)、镓铟磷(GaInP)及/或镓铟砷磷(GaInAsP)；或(iii)或其组合。
出于举例目的，将在结晶硅(Si)的上下文中描述基板120及磊晶层110/205。基于本文揭示内容，如上所述，可使用其他材料。此些材料在本揭示案的精神及范畴内。
举例而言且并非限制，p型GAA FET 100中的S/D磊晶结构125可包括硼掺杂(B掺杂)SiGe、B掺杂Ge、B掺杂锗-锡(GeSn)或其组合。因此，n型GAA FET 100中的S/D磊晶结构125可包括砷(As)或磷(P)掺杂Si、碳掺杂硅(Si:C)或其组合。在一些实施例中，S/D磊晶结构125包括图1及图2中未示出的两个或更多个磊晶生长层。在一些实施例中，如上所述，S/D磊晶结构125与NS或NW 130实体接触。
在一些实施例中，当NS或NW 130沿y方向的宽度与其沿z方向的高度大体上不同时—例如，当宽度大于或窄于其高度时，NS或NW 130称作“纳米薄片”。因此，当NS或NW 130沿y方向的宽度与其沿z方向的高度大体上相等时，NS或NW 130称作“纳米线”。举例而言且并非限制，将在NS层的上下文中描述NS或NW 130。基于本文揭示内容，纳米线在本揭示案的精神及范畴内。
在一些实施例中，每一NS 130具有在约3nm与约15nm之间的垂直厚度(例如，沿z方向)，及沿y方向在约10nm与约150nm之间的宽度。相邻NS 130以范围在约3nm与约15nm之间的空间垂直地分离开。在一些实施例中，NS 130包括Si或Si(1-x)Gex，其中Ge原子浓度在约10％与约100％(例如，纯Ge)之间。或者，NS 130可包括III-V族化合物半导体，诸如，GaAs、InP、GaP及GaN。出于举例目的，将在Si NS层的上下文中描述NS 130。基于本文揭示内容，如上所述，可使用其他材料且其在本揭示案的精神及范畴内。
在一些实施例中，取决于晶体管的特性，GAA FET 100可包括2个与8个之间的个别NS 130。更大数目个NS 130是可能的且在本揭示案的精神及范畴内。在一些实施例中，NS130为轻微掺杂的或未掺杂的。根据一些实施例，若为轻微掺杂，则NS 130的掺杂位准小于约1019掺杂剂/cm3。
如图1及图2中所示，NS 130之间的空间被栅极堆叠140的层(例如，界面层(IL)145、高介电常数介电质150及栅电极155)所占用。在一些实施例中，栅极堆叠140覆盖NS130的中间部分。NS 130的边缘部分被间隔物结构135覆盖。在一些实施例中，间隔物结构135包括氮化物，诸如，氮化硅(Si3N4或“SiN”)、硅碳氮化物(SiCN)及硅碳氧氮化物(SiCON)。在一些实施例中，间隔物结构135沿x方向的宽度的范围在约3nm与约10nm之间。如图1及图2中所示，间隔物结构135插入在栅极堆叠140与S/D磊晶结构125之间，以将栅极堆叠140与S/D磊晶结构125隔离开。
如图1及图2中所示，栅极间隔物160覆盖栅极堆叠140的侧壁表面且安置在最顶部NS 130上。栅极间隔物160(如间隔物结构135)可包括SiN、SiCN或SiCON。在一些实施例中，栅极间隔物160促进栅极堆叠140的形成。
在一些实施例中，ILD 165包括介电材料的一或更多个层。举例而言且并非限制，ILD 165可为基于氧化硅的介电质，其包括氮、氢、碳或其组合。根据一些实施例，ILD 165为栅极堆叠140、S/D接触件(未示出)及S/D磊晶结构125提供电隔离及结构支撑。
根据一些实施例，图3A及图3B为描述图1中所示的局部隔离结构115的形成的制造方法300的流程图。可在方法300的各种操作之间执行其他制造操作且仅为了简化而将其省略。本揭示案并不限于此操作描述。实情为，其他操作在本揭示案的精神及范畴内。应了解，可执行额外操作。此外，执行本文中所提供的揭示内容可能并不需要所有操作。另外，可同时地或以不同于图3A及图3B中所呈现的次序的次序来执行操作中的一些。在一些实施例中，可另外或替代于当前所述操作而执行一或更多个其他操作。出于说明目的，参考图4至图12B中所示的实施例来描述方法300。
参考图3A，方法300以操作305及在基板120上沉积第一磊晶层及第二磊晶层的制程开始。举例而言且并非限制，可在无真空破坏的情况下(例如，原位)在基板120的整个顶表面上依次沉积第一及第二磊晶层，以避免所沉积的磊晶层之间的界面氧化物形成。在一些实施例中，第一磊晶层包括SiGe，其中Ge原子百分比在约20％与40％之间。在一些实施例中，与第二磊晶层及基板120相比较而言，第一磊晶层中的Ge浓度可用以精细调节所得SiGe层的蚀刻选择性。在一些实施例中，不同的蚀刻化学物质可能需要不同的Ge原子百分比以实现所期望的蚀刻选择性。另一方面，第二磊晶层包括大体上不含Ge的Si—例如，具有小于约0.5％的Ge的Ge浓度。在一些实施例中，与第二磊晶层及基板120相比较而言，在沉积期间掺杂第一磊晶层(例如，SiGe)，以进一步调节其蚀刻选择性。举例而言而非限制，第一磊晶层可掺杂有砷(As)掺杂剂、其他适当的掺杂剂物质，或其组合。
举例而言且并非限制，可通过使用前驱物气体的化学气相沉积(CVD)制程“毯覆沉积”第一及第二磊晶层，此些前驱物气体是诸如硅烷(SiH4)、二硅烷(Si2H6)、锗烷(GeH4)、二锗烷(Ge2H6)、二氯硅烷(SiH2Cl2)、其他适当气体，或其组合。在一些实施例中，第一及第二磊晶层是在约550℃与800℃之间的温度下及约1托与约600托之间的制程压力下沉积。在一些实施例中，第二磊晶层是在比第一磊晶层的温度高的温度下沉积的。
在一些实施例中，第一磊晶层可通过离子布植形成，其中基板的顶部部分掺杂有Ge或As以形成SiGe层或As掺杂的硅层。第二磊晶层可随后形成在第一磊晶层上。
在一些实施例中，图4为根据操作305沉积在基板120上的第一磊晶层400及第二磊晶层405的等角视图。根据一些实施例，图4中所示的第一磊晶层400的厚度对应于图1中所示的局部隔离结构115的厚度。因此，第一磊晶层400的厚度大体上类似于局部隔离结构115的厚度—例如，在约5nm与约100nm之间。根据一些实施例，第二磊晶层将经图案化以形成图1中所示的磊晶层110。因此，第二磊晶层405的刚沉积厚度对应于磊晶层110的厚度，例如，在约5nm与约100nm之间。如以上关于磊晶层110所论述，厚度大于约100nm的第二磊晶层可引发对基板120的不当的机械应力。
参考图3A，方法300继续操作310及在第一磊晶层400、第二磊晶层405及基板120中蚀刻沟槽开口的制程。举例而言且并非限制，可通过以下所描述的图案化制程来形成第一磊晶层400、第二磊晶层405及基板120中的沟槽开口。参考图4，在第二磊晶层405上安置遮罩堆叠，以覆盖第二磊晶层405的整个表面。随后图案化此遮罩堆叠以形成图案化结构410。图案化结构410在后续蚀刻制程中充当蚀刻遮罩以移除第二磊晶层405、第一磊晶层400及基板120的已暴露部分，以便形成图5(图4中所示的结构沿切线AB的横截面图)中所示的沟槽开口500。在一些实施例中，图案化结构410包括为了简化起见而未在图4及图5中示出的底部硬遮罩层(例如，氧化物层)及顶部光罩层(例如，光阻层)。在一些实施例中，图案化结构410包括交替的氧化物及氮化物层(诸如，氧化硅及氮化硅)的底部硬遮罩堆叠，及顶部光阻层。
蚀刻制程可包括干式蚀刻制程、湿式蚀刻制程，或其组合。在一些实施例中，蚀刻制程使用对靶层(例如，基板120、第一磊晶层400及第二磊晶层405)有选择性的蚀刻化学物质。
举例而言且并非限制，干式蚀刻制程可包括含氧气体、含氟气体、含氯气体、含溴气体、含碘气体、其他适当蚀刻气体及/或电浆，或其组合。含氟气体的实例包括但不限于四氟化碳(CF4)、六氟化硫(SF6)、二氟甲烷(CH2F2)、三氟甲烷(CHF3)及六氟乙烷(C2F6)。含氯气体的实例包括但不限于氯气(Cl2)、氯仿(CHCl3)、四氯化碳(CCl4)及三氯化硼(BCl3)。含溴气体的实例包括但不限于溴化氢(HBr)及溴仿(CHBr3)。
举例而言且并非限制，湿式蚀刻制程可包括稀氢氟酸(DHF)；氢氧化钾(KOH)；氨水；含氢氟酸(HF)、硝酸(HNO3)、乙酸(CH3COOH)的溶液；及其组合。
参考图5，沟槽开口500形成在第二磊晶层405、第一磊晶层400及基板120的未被遮罩的部分中。因此，图案化结构410形成在基板120的不期望形成沟槽开口500的位置上。在操作310的蚀刻制程期间，可如图5中所示形成多个沟槽开口500。沟槽开口500的位置及大小由图案化结构410的相对定位及尺寸(例如，长度及宽度)限定。根据一些实施例，沟槽开口500形成浅沟槽隔离(STI)开口，其在随后通过介电材料填充时在基板120中形成相应的浅沟槽隔离(STI)结构。在一些实施例中，图案化结构410可具有与图5中所示的图案化结构不同的间距、形状及大小。另外，每一图案化结构410的间距、形状及大小可彼此不同。根据一些实施例，图5示出基板120的形成沟槽开口500的选择性部分。基板120的其他部分(图5中未示出)可保持被图案化结构410覆盖或带有具有不同间距、形状及/或大小的图案化结构410。
根据一些实施例，如图5中所示，沟槽开口500暴露第一磊晶层400及第二磊晶层405的侧壁表面。
参考图3A，方法300继续操作315及经由沟槽开口500移除第一磊晶层400的部分以在第二磊晶层405与基板120之间形成缝隙的制程。在一些实施例中，操作315的移除制程不会移除整个第一磊晶层400。实情为，移除制程移除了第一磊晶层400在沟槽开口500附近的部分。换言之，所得缝隙形成在沟槽开口500周围且并非在整个基板120之上。此可(例如)通过适当地调整蚀刻制程时序或通过用掺杂剂局部地控制对第一磊晶层400的蚀刻选择性而完成。在一些实施例中，操作315中所使用的蚀刻制程能够横向地蚀刻第一磊晶层400以在第二磊晶层405与基板120之间形成缝隙。
在一些实施例中，蚀刻制程可包括干式蚀刻、湿式蚀刻或其组合。举例而言，蚀刻制程可包括干式及湿式蚀刻制程的循环制程。举例而言且并非限制，干式蚀刻化学物质可包括含氯气体，诸如，盐酸(HCl)、Cl2、三氟氯甲烷(CF3Cl)、CCl4，或以氦气(He)或氩气(Ar)作为载气的四氯化硅(SiCl4)。相应地，若先前通过As或另一掺杂剂掺杂了第一磊晶层400，则湿式蚀刻化学物质可包括氢氧化四甲铵(TMAH)水溶液。或者，湿式蚀刻可包括过氧化氢(H2O2)、CH3COOH及氢氟酸(HF)的溶液，之后通过去离子水(DIW)进行清洁。
根据一些实施例，图6示出在操作315之后图5的结构。如图6中所示，已横向地蚀刻(例如，移除)第一磊晶层400的部分以形成缝隙600，而第一磊晶层400的其他部分(例如，位于距沟槽开口500距离L处)得以保留(例如，未被移除)。在一些实施例中，距离L的范围为自约5nm至约1μm。第一磊晶层400的未蚀刻部分为缝隙600之上的第二磊晶层405及图案化结构410提供支撑，并防止第二磊晶层405及图案化结构410坍塌。
参考图3A，方法300继续操作320及在沟槽开口500中沉积第一介电质以填充第二磊晶层405与基板120之间的缝隙600的制程。举例而言且并非限制，可通过可流动CVD高深宽比制程(HARP)来沉积第一介电质，其中液体状的可流动介电质经沉积、固化并随后退火以形成第一介电质。或者，可通过高密度电浆制程(HDP)来沉积第一介电质。在一些实施例中，在操作320中沉积的第一介电质用以形成图1中所描述的隔离结构115。根据一些实施例，图7示出在根据操作320形成第一介电质700之后图6的结构。将第一介电质700沉积地足够厚以大体上填充图6中所示的缝隙600。在一些实施例中，第一介电质700不完全填充缝隙600。举例而言，如在图7的插入图(其为第一介电质700的放大视图)中所示，可能在第二磊晶层405与基板120之间形成气穴或空隙710。
参考图3B，方法300继续操作325及自沟槽开口回蚀第一介电质700以在第二磊晶层405与基板120之间形成图1中所示的隔离结构115的制程。在一些实施例中，此回蚀制程为能够选择性地蚀刻第一介电质700(例如，氧化硅)的各向异性干式蚀刻制程。在一些实施例中，回蚀制程移除第一介电质700，以使得沟槽开口500如图8中所示被暴露。由于回蚀制程的各向异性，第一介电质700未被横向地蚀刻，且因此未在第二磊晶层405与基板120之间被移除。因此，如图8中所示，第二磊晶层405的侧壁表面与第一介电质700的侧壁表面对准。在一些实施例中，第一介电质700在第二磊晶层405与基板120之间的未经蚀刻部分形成图1中所示的隔离结构115。在一些实施例中，在操作325之后，可通过湿式蚀刻制程或任何其他适当制程将图案化结构410移除。
参考图3B，方法300继续操作330及在沟槽开口500中沉积第三磊晶层的制程。在一些实施例中，第三磊晶层类似于第二磊晶层405。举例而言，第三磊晶层可为通过使用前驱物气体的CVD制程沉积的大体上不含Ge的Si磊晶层，此些前驱物气体是诸如硅烷(SiH4)、二硅烷(Si2H6)、二氯硅烷(SiH2Cl2)、其他适当气体及其组合。
在一些实施例中，在沉积第三磊晶层之前，在沟槽开口500的表面上以约1nm与约5nm之间的厚度形成内衬材料。此内衬材料可充当钝化或缓冲层，其在第三磊晶层的生长制程期间抑制缺陷形成。在一些实施例中，在第三磊晶层的沉积之前，内衬材料在约850℃下退火历时约100秒。举例而言且并非限制，图9示出在根据操作330形成内衬900及第三磊晶层905之后图8的结构。在一些实施例中，内衬900促进第三磊晶层905的形成，且第三磊晶层905促进在操作340中所形成的纳米薄片层的形成。举例而言，第三磊晶层905防止或抑制了在形成于其上的纳米薄片层中形成缺陷。
参考图3B，方法300继续操作335及平坦化第三磊晶层905以使得第三磊晶层905变成与第二磊晶层405共平面的制程。举例而言且并非限制，可通过化学机械平坦化(CMP)制程来平坦化第三磊晶层905，此化学机械平坦化(CMP)制程移除在第二磊晶层405的顶表面之上的第三磊晶层905及内衬900并导致平面的顶表面形貌。在图10中示出具有经平坦化/经研磨的第三磊晶层905的所得结构。
参考图3B，方法300继续操作340及在第二磊晶层405上形成纳米薄片(NS)层的堆叠的制程。在一些实施例中，此堆叠亦形成在第三磊晶层905上。在一些实施例中，NS层的堆叠包括图1中所示的NS层130及与NS层130不同的另一类型的NS层的交替层。举例而言且并非限制，图11示出NS层的堆叠1100(堆叠1100)，其具有NS层1105及根据操作340形成在第二磊晶层405及第三磊晶层905上的NS层130的交替层。在一些实施例中，选择用于堆叠1100中的NS层1105的材料，以使得可经由蚀刻自堆叠1100选择性地移除NS层1105而不会移除NS层130。举例而言，若NS层130为硅NS层，则NS层1105可为SiGe NS层。在一些实施例中，NS层130及NS层1105是通过类似于用以沉积第一磊晶层400及第二磊晶层405的方法的方法形成。自堆叠1100移除NS层1105形成了图1中所示的GAA FET 100的通道区域。
举例而言且并非限制，堆叠1100可形成在基板120的整个表面上，且随后经图案化而使得堆叠1100的在第三磊晶层905上的部分如图12A中所示被选择性地移除。因此，鳍片结构1200形成在第二磊晶层405的选定部分上，且鳍片结构1200的侧壁表面与第二磊晶层405及第一介电质700的侧壁表面对准。在前述图案化制程期间，如图12A中所示，亦移除了在鳍片结构1200之间的第三磊晶层905及内衬900。在一些实施例中，如图12B中所示，沉积具有约5nm与约15nm之间的厚度的封盖层1205，以覆盖鳍片结构1200。在一些实施例中，封盖层1205为保护鳍片结构1200免于后续回蚀制程的氧化物层(例如，氧化硅层)。参考图12B，第二介电质1210被沉积在鳍片结构1200之上的封盖层1205上，通过CMP制程平坦化，且随后经回蚀以形成浅沟槽隔离(STI)结构1215。在一些实施例中，回蚀制程使封盖层1205及第二介电质1210凹陷至第二磊晶层405的高度位准，使得封盖层1205及STI结构1215的顶表面与第二磊晶层405的顶表面共平面。
在一些实施例中，沿y方向在鳍片结构1200的中间部分上形成牺牲栅极结构(未示出)，以使得鳍片结构的末端部分沿x轴自牺牲栅极结构突出。随后，蚀刻制程移除(例如，修整)鳍片结构1200的已暴露的末端部分。如图12C的等角视图中所示，在蚀刻制程期间，第二磊晶层400的未被牺牲栅极结构覆盖的部分将被暴露，并随后相对于磊晶层400的被覆盖的中间部分及STI结构1215的顶表面凹陷以形成凹陷部分1215。牺牲栅极结构可用作上述蚀刻操作的遮罩层，为了简化及易于可视化而未在图12C中示出。
根据一些实施例，具有凹陷部分1215的第二磊晶层405及图12C中所示的第一介电质700分别对应于图1中所示的磊晶层110及隔离结构115。在一些实施例中，S/D磊晶结构125形成在第二磊晶层405的凹陷部分1215上。另外，通过选择性蚀刻制程自鳍片结构1200移除NS层1105，且栅极堆叠140替代牺牲栅极结构以形成图1中所示的GAA FET 100。
根据一些实施例，图13A及图13B为用于形成图2中所示的局部隔离结构200及磊晶层205的制造方法1300的流程图。可在方法1300的各种操作之间执行其他制造操作且仅为了简化而将其省略。本揭示案并不限于此操作描述。实情为，其他操作在本揭示案的精神及范畴内。应了解，可执行额外操作。此外，执行本文中所提供的揭示内容可能并不需要所有操作。另外，可同时地或以不同于图13A及图13B中所呈现的次序的次序来执行操作中的一些。在一些实施例中，可另外或替代当前所述操作而执行一或更多个其他操作。出于说明目的，参考图4至图9及图14至图17中所示的实施例来描述方法1300。
在一些实施例中，方法1300的操作1305至1335等同于以上所述方法300的操作305至335。因此，用以描述方法300的操作305至335的图4至图10可用以描述方法1300的操作1305至1335。出于此原因，方法1300的描述将自图10以及图13B中所示的操作1340继续。
参考图13B，方法1300继续操作1340及图案化第二磊晶层405及第一介电质700以在第一介电质700中形成开口以便暴露基板120的制程。在一些实施例中，图14为图10的等角视图。如图14中所示，被内衬900环绕的第三磊晶层905形成具有沿x方向的长度及沿y方向的宽度的结构，使得第二磊晶层405及第一介电质700的侧壁表面对准。如图15中所示，根据操作1340，图案化第二磊晶层405及第一介电质700的在由第三磊晶层905及内衬900所形成的结构之间的部分，以形成具有长度L的开口1500以便暴露基板120。在一些实施例中，开口1500的长度L对应于图2中所示的隔离结构200之间的距离S。在一些实施例中，如图15中所示，开口1500沿y方向的宽度在由内衬900及第三磊晶层905形成的相邻结构之间延伸。
参考图13B，方法1300继续操作1345及在开口1500中沉积第四磊晶层(例如，磊晶层205)的制程。在一些实施例中，磊晶层205沉积在第二磊晶层405、第三磊晶层905及内衬900的已暴露表面上。在一些实施例中，如图16A中所示，磊晶层205在沉积之后通过CMP制程进行平坦化，以使得磊晶层205在开口1500内的厚度等于图2中所示的厚度205t。根据一些实施例，图16B为图16A跨切线AB的横截面图。
参考图13B，方法1300继续操作1350及在磊晶层205(例如，第四磊晶层)上形成具有NS层的堆叠(类似于图11中所示的堆叠1100)的制程。举例而言，图17示出在根据操作1350沉积了堆叠1100之后的图16A。在一些实施例中，操作1350类似于图3B中所示的方法300的操作340。举例而言，可随后图案化所沉积的堆叠，以形成图18中所示的鳍片结构1800。形成鳍片结构1800的图案化制程可类似于用以形成图12A中的鳍片结构1200的图案化制程。因此，如图18中所示，操作1350的图案化制程移除了第三磊晶层905及内衬900。在一些实施例中，如图18中所示，沉积具有约5nm与约15nm之间的厚度的封盖层1205，以覆盖鳍片结构1800。在一些实施例中，封盖层1205为保护鳍片结构1800免于后续回蚀制程的氧化物层(例如，氧化硅层)。参考图19A，第二介电质1900沉积在封盖层1205上，经图案化，且被回蚀(连同封盖层1205一起)至磊晶层205的高度位准以形成浅沟槽隔离(STI)结构1905。在一些实施例中，第二介电质1900类似于图12B中所示的第二介电质1210。在图19A的实例中，不同于第二介电质1210，第二介电质1900在第一介电质700之上延伸。然而，此并非限制性的，且第一介电质700的其他部分可不被第二介电质1900覆盖。
在一些实施例中，沿y方向在鳍片结构1800的中间部分上形成牺牲栅极结构(未示出)，以使得鳍片结构1800沿x轴的末端部分自牺牲栅极结构突出。随后，蚀刻制程移除(例如，修整)鳍片结构1800的已暴露的末端部分。如图19B的等角视图中所示，在蚀刻制程期间，相对于磊晶层205的被覆盖的中间部分及STI结构1905的顶表面来蚀刻磊晶层205的未被牺牲栅极结构覆盖的部分或磊晶层205的整个厚度，以形成凹陷部分1910。在一些实施例中，凹陷部分1910包括第二磊晶层405与磊晶层205的一部分的堆叠。或者，凹陷部分1910包括第二磊晶层405，其中磊晶层205被图19B中所示的上述修整制程全部移除。因此，参考图2，插入在S/D磊晶结构125与隔离结构200之间的磊晶层可包括第二磊晶层405与磊晶层205的一部分的堆叠，或仅包括磊晶层405。在图2的说明中，插入在S/D磊晶结构125与隔离结构200之间的磊晶层包括第二磊晶层405(未示出)与磊晶层205的一部分的堆叠。前述牺牲栅极结构可用作上述蚀刻操作的遮罩层，为了简化及易于可视化而未在图19B中示出。
在一些实施例中，S/D磊晶结构125形成在凹陷部分1910上。另外，通过选择性蚀刻制程自鳍片结构1800移除NS层1105，且栅极堆叠140替代牺牲栅极结构以形成图2中所示的GAA FET 100。
本文中所描述的实施例是针对用于制造具有低功耗的GAA FET的方法。在一些实施例中，局部介电层形成在GAA FET的源极/漏极磊晶结构下方的基板区域上。在一些实施例中，局部介电质形成在整个GAA FET之下。在一些实施例中，在形成GAA结构之前，在块体基板上形成硅-锗/硅双层。随后，经由双层中的沟槽开口选择性地移除硅-锗层的多个部分，并以介电层替代，以在GAA FET下方形成局部隔离结构。在一些实施例中，图案化局部隔离结构，以使得局部隔离结构的在GAA FET的通道区域之下的部分被移除。在一些实施例中，局部隔离结构包括氧化硅。在一些实施例中，本文所述方法并不限于GAA FET，且可应用于其他类型的晶体管，诸如，finFET。
在一些实施例中，一种半导体结构包括具有第一区域的基板，此第一区域具有第一及第二沟槽隔离结构。另外，此半导体结构包括在基板的第一区域上的介电质，其安置在第一及第二沟槽隔离结构之间。此半导体结构亦包括在介电质上的磊晶层，其中此磊晶层包括第一区域及第二区域。此半导体结构进一步包括安置在磊晶层的第一区域上的源极/漏极结构、包括安置在磊晶层的第二区域之上的纳米薄片层的垂直堆叠，及安置在磊晶层的第二区域上环绕垂直堆叠的纳米薄片层的栅极堆叠。在一些实施例中，半导体结构进一步包括使纳米薄片层垂直地分离并插入在栅极堆叠与源极/漏极结构之间的间隔物结构。磊晶层的第一区域的一上部表面低于磊晶层的第二区域的一上部表面。磊晶层的第二区域具有在约5nm与约100nm之间的一厚度。基板包括一第一区域与一第二区域，第一区域具有通过介电质间隔开的一第一隔离结构及一第二隔离结构。第二区域定位成与基板的第一区域相邻，其中基板的第二区域不包括隔离结构且包括与介电质共平面且与磊晶层不同的一另外磊晶层。另外磊晶层包括硅锗且磊晶层包括不含锗的硅。介电质包括氧化硅。介电质具有在约5nm与约100nm之间的一厚度。磊晶层的第二区域定位在磊晶层的一中间部分中，且磊晶层的第一区域定位在磊晶层的一边缘部分中。
在一些实施例中，一种半导体结构包括具有间隔开的沟槽隔离结构的基板，及在基板上安置于沟槽隔离结构之间的介电结构。此半导体结构进一步包括在介电结构上的磊晶层，其中此磊晶层包括与介电结构的上部表面接触的第一区域，及形成在基板上且与介电结构的侧表面接触的第二区域。另外，此半导体结构包括在磊晶层的第一区域上的源极/漏极结构、包括安置在磊晶层的第二区域之上的纳米薄片层的垂直堆叠，及在磊晶层的第二区域上环绕垂直堆叠的纳米薄片层的栅极堆叠。在一些实施例中，半导体结构进一步包括使纳米薄片层垂直地分离并插入在栅极堆叠与源极/漏极结构之间的间隔物结构。第一区域的一上部表面低于第二区域的一上部表面。磊晶层的第二区域具有在约5nm与约100nm之间的一厚度。所述介电结构包括氧化硅且具有在约5nm与约100nm之间的一厚度。第二区域定位在磊晶层的一中间部分中，且第一区域定位在磊晶层的一边缘部分中。半导体结构进一步包括在基板上的一另外磊晶层，其中另外磊晶层与所述介电结构共平面。另外磊晶层包括硅锗。
在一些实施例中，一种方法包括在基板上沉积第一及第二磊晶层，及在第一及第二磊晶层以及基板中蚀刻沟槽开口。此方法进一步包括经由沟槽开口移除第一磊晶层的部分以在第二磊晶层与基板之间形成缝隙，及经由沟槽开口沉积第一介电质以填充缝隙并形成隔离结构。另外，此方法包括在沟槽开口中沉积第二介电质以形成沟槽隔离结构，及在第二磊晶层上形成晶体管结构。在一些实施例中，移除第一磊晶层的所述部分包括在第二磊晶层与基板之间形成缝隙。沉积第一磊晶层及第二磊晶层包括分别沉积一硅-锗磊晶层及一硅磊晶层。
应了解，预期使用实施方式部分而非揭示案摘要部分来解释权利要求。如(若干)发明人所预期，揭示案摘要部分可阐述本揭示案的一或更多个但非全部的实施例，且因此并不旨在以任何方式限制附加权利要求书。
前述揭示内容概述了若干实施例的特征，使得熟悉此项技术者可较佳地理解本揭示案的态样。熟悉此项技术者应了解，他们可容易地使用本揭示案作为设计或修改用于实现相同目的及/或达成本文中所介绍的实施例的相同优势的其他制程及结构的基础。熟悉此项技术者亦将认识到，此些等效构造不脱离本揭示案的精神及范畴，且他们可在不脱离本揭示案的精神及范畴的情况下在本文中作出各种改变、代替及替换。

Claims (1)

1.一种半导体结构，其特征在于，包括：
一基板；
一介电质，在该基板上；
一磊晶层，安置在该介电质上且包括一第一区域及一第二区域，其中该磊晶层的侧壁与该介电质的侧壁对准；
一源极/漏极结构，安置在该磊晶层的该第一区域上；
一垂直堆叠，包括安置在该磊晶层的该第二区域之上的纳米薄片层；以及
一栅极堆叠，安置在该磊晶层的该第二区域上且环绕该垂直堆叠的所述纳米薄片层。
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