CN113990761A - Flexible coreless 3D printed integrated circuit die pressing process - Google Patents
Flexible coreless 3D printed integrated circuit die pressing process Download PDFInfo
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- CN113990761A CN113990761A CN202111247805.2A CN202111247805A CN113990761A CN 113990761 A CN113990761 A CN 113990761A CN 202111247805 A CN202111247805 A CN 202111247805A CN 113990761 A CN113990761 A CN 113990761A
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- 230000008569 process Effects 0.000 title claims abstract description 137
- 238000007723 die pressing method Methods 0.000 title claims description 8
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- 229910052709 silver Inorganic materials 0.000 claims abstract description 43
- 239000004332 silver Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 238000000465 moulding Methods 0.000 claims abstract description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 12
- 238000005245 sintering Methods 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000011161 development Methods 0.000 claims abstract description 6
- 238000009713 electroplating Methods 0.000 claims abstract description 5
- 238000010030 laminating Methods 0.000 claims abstract description 4
- 238000004049 embossing Methods 0.000 claims description 12
- 239000010935 stainless steel Substances 0.000 claims description 8
- 229910001220 stainless steel Inorganic materials 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 238000010304 firing Methods 0.000 claims description 4
- 238000007790 scraping Methods 0.000 claims description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
The invention provides a flexible coreless 3D printed integrated circuit mould pressing process, which comprises an integrated circuit carrier process and an integrated circuit assembly process, wherein the integrated circuit carrier process flow comprises 101 laminating; 102. exposing; 103. carrying out development; 104. electroplating; 105. baking the photoresist; 106. backfilling; 107. sintering, wherein the integrated circuit assembly process flow comprises 201 flip chip application; 202. molding; 203. back side etching. Compared with the traditional CSI process, the method has the advantages that the material warping problem is effectively avoided by adopting a series of measures, the influence of silver softness on adhesion and the silver discoloration problem are solved, the substrate is effectively and cleanly removed on the premise of no damage, and meanwhile, the method has the advantage of saving material cost.
Description
Technical Field
The invention belongs to the field of integrated circuit design, and particularly relates to a flexible coreless 3D printed integrated circuit die pressing process.
Background
With the development of science and technology, the chip exists in all aspects of life, and Chinese chips have gone out of one way of the chip regardless of computers or mobile phones. Electronic packaging is an indispensable process for integrated circuit chips and is a device-to-system bridge. This production process has a great influence on the quality and competitiveness of microelectronic products. Packaging research has been rapidly developed on a global scale, and challenges and opportunities that it faces have never been encountered since the advent of electronic products; the packaging is a new highly integrated high-tech discipline from materials to processes, from inorganic to polymeric, from large production facilities to computational mechanics, to many more widespread and rare in many other fields.
The most important of the current package is the manufacturing process of the substrate frame, the conventional CSI process is liable to cause warpage of the metal substrate due to the need of pre-treating and sintering the substrate at a very high temperature, and the thickness and characteristics of silver are liable to cause the problem of bondability, in addition, the peeling mechanism of the molded substrate also causes some technical problems related to mold cracks, silver bubbles and voids, and after the substrate is removed, the silver is liable to be contaminated by sulfur in the environment and discolored due to no protection.
For example, chinese patent No. cn201811222274.x discloses a novel chip package and a packaging method thereof, which includes a base board, a pin and a cap, and solves the sample preparation problems of slow speed and high cost in the integrated circuit engineering stage, but does not consider the manufacturing process of the most important substrate frame of the package, so that the problem of the conventional CSI process is urgently solved.
For example, chinese patent CN 201810563822.9 discloses a chip package and a packaging method thereof, which includes a lead frame, a plurality of chips and a first conductive sheet; the lead frame is provided with a plurality of base islands and a plurality of negative electrode pins; the first conducting strip is welded on the negative electrodes of all the chips, so that the heat dissipation performance and the capacity of bearing high current are greatly improved, but the problems generated in the manufacturing process of the substrate frame are not considered.
Therefore, how to innovatively design the existing package product to make the package thinner and lighter, while being compatible with the structural layout of the current package, a more complex flow and layout are adopted, and in addition, the problems of metal substrate warpage, silver adhesiveness and discoloration, mold cracks generated by peeling the substrate, and the like in the conventional CSI process are further solved in an optimized manner, which are all technical problems to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides a flexible coreless 3D printed integrated circuit molding process, which adopts a series of measures to avoid the material warpage problem easily generated by the conventional process, improve the adhesion, and protect the mold from crack and void.
In order to achieve the above purpose, the present application provides the following technical solutions:
a flexible coreless 3D printed integrated circuit molding process includes an integrated circuit carrier process;
the integrated circuit carrier process flow comprises the following steps:
101. laminating;
102. exposing;
103. carrying out development;
104. electroplating;
105. baking the photoresist;
106. backfilling;
107. firing/sintering;
preferably, the process 101 must be performed in a yellow room, while also ensuring that the laminated substrate remains in the yellow room during the UV exposure machine used to perform the process 102;
preferably, process 104 refers to plugging a 15um tin (Sn) layer on the clusters formed on the stainless steel/copper;
preferably, process 105 refers to hardening the photoresist using a bake oven or conveyor;
preferably, the process 106 refers to printing silver paste onto the patterned substrate using a printer, a machine with a front and back squeegee strip hardness of 100-.
Preferably, the process 107 is controlled at 220 ℃ for 120 minutes;
preferably, the flexible coreless 3D printed integrated circuit molding process further comprises an integrated circuit assembly process;
the integrated circuit assembly process flow comprises the following steps:
201. flip chip applications;
202. molding;
203. back side erosion;
preferably, the process 201 refers to picking up and placing the required flip chip on a dedicated silver pad, and then performing corresponding curing;
preferably, the process 203 refers to the removal of the substrate using an etch back process.
Compared with the prior art, the invention has the following beneficial effects:
1. according to the flexible coreless 3D printed integrated circuit die pressing process, the problem of material warping caused by repeated pretreatment of a metal base material in a high-temperature environment in the traditional CSI process is solved through controlled heat treatment of shape and material selection.
2. According to the flexible coreless 3D printed integrated circuit die pressing process, the influence of the softness of silver on the adhesion is solved, the construction cost of materials is reduced, and meanwhile, the formation of the silver-tin (Ag-Sn) alloy interlayer is beneficial to improving the mechanical strength, the thermal fatigue performance and the wettability.
3. According to the flexible coreless 3D printed integrated circuit die pressing process, the reverse etching process is adopted when the base plate is removed, in the process, the metal substrate is easy to remove, and the influence on the internal structure of a die part caused by a stripping mechanism of the traditional CSI process die base plate is avoided.
4. According to the flexible coreless 3D printed integrated circuit die pressing process, the tin (Sn) layer of 15um is plated on the pattern formed on the stainless steel/copper, so that the problem of silver discoloration after the substrate is removed is solved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Throughout the drawings, like elements or portions are generally identified by like reference numerals. In the drawings, elements or portions are not necessarily drawn to scale.
FIG. 1 is a flow chart of an integrated circuit carrier process in a flexible coreless 3D printed integrated circuit molding process provided by the present invention;
FIG. 2 is a flow chart of an integrated circuit assembly process in a flexible coreless 3D printed integrated circuit molding process provided by the present invention;
FIG. 3 is a schematic diagram illustrating the requirements and operation of a squeegee strip in a flexible coreless 3D printed integrated circuit molding process according to the present invention;
FIG. 4 is a schematic diagram of a printing operation in a backfill process in a flexible coreless 3D printed integrated circuit molding process provided by the present invention;
figure 5 is a schematic cross-sectional view of a silver-tin (Ag-Sn) alloy interlayer in a flexible coreless 3D printed integrated circuit molding process provided by the present invention;
figure 6 is a phase diagram of silver-tin (Ag-Sn) system equilibrium in a flexible coreless 3D printed integrated circuit molding process provided by the present invention;
FIG. 7 is a schematic diagram of a reverse etching process in a flexible coreless 3D printed integrated circuit molding process provided by the present invention;
figure 8 is a comparison of substrate morphology for a CSI process and a flexible coreless 3D printed integrated circuit embossing process as provided herein;
figure 9 is a schematic illustration comparing a silver printing process of a CSI process with a flexible coreless 3D printed integrated circuit embossing process provided herein;
FIG. 10 is a schematic view of molded substrate stripping in a CSI process;
figure 11 is a schematic diagram comparing the molding profiles of a CSI process with a flexible coreless 3D printed integrated circuit embossing process as provided by the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. In the following description, specific details such as specific configurations and components are provided only to help the embodiments of the present application be fully understood. Accordingly, it will be apparent to those skilled in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present application. In addition, descriptions of well-known functions and constructions are omitted in the embodiments for clarity and conciseness.
It should be appreciated that reference throughout this specification to "one embodiment" or "the embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrase "one embodiment" or "the present embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Further, the present application may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
The term "and/or" herein is merely an association describing an associated object, meaning that three relationships may exist, e.g., a and/or B, may mean: a exists alone, B exists alone, and A and B exist at the same time, and the term "/and" is used herein to describe another association object relationship, which means that two relationships may exist, for example, A/and B, may mean: a alone, and both a and B alone, and further, the character "/" in this document generally means that the former and latter associated objects are in an "or" relationship.
The term "at least one" herein is merely an association relationship describing an associated object, and means that there may be three relationships, for example, at least one of a and B, may mean: a exists alone, A and B exist simultaneously, and B exists alone.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion.
Example 1
This embodiment describes an integrated circuit carrier process in a flexible coreless 3D printed integrated circuit molding process.
Referring to fig. 1, fig. 1 is a flowchart of an integrated circuit carrier process in a flexible coreless 3D printed integrated circuit molding process provided by the present invention; referring to fig. 3, fig. 3 is a schematic diagram illustrating the requirements and operation of a glue scraping strip in a flexible coreless 3D printed integrated circuit molding process according to the present invention; referring to fig. 4, fig. 4 is a schematic diagram illustrating a backfill process printing operation in a flexible coreless 3D printed integrated circuit molding process provided by the present invention.
The integrated circuit carrier process flow comprises the following steps:
101. laminating;
102. exposing;
103. carrying out development;
104. electroplating;
105. baking the photoresist;
106. backfilling;
107. firing/sintering;
further, since the photoresist used is very sensitive to light in the lower spectral range of the visible and ultraviolet spectrum, the process 101 must be performed in a yellow room. In process 101, a photoresist layer press is set to a desired temperature and loaded in a substrate for lamination, then a cutting area is precisely located on the laminate, and the photoresist is cut according to the shape of the substrate. Note that the last polyester film layer is not removed prior to the development process.
Further, a UV exposure machine is selected for performing the exposure process in process 102 while ensuring that the laminated substrate remains in the yellow room. First, the top and bottom surfaces of the photomask are wiped to ensure no foreign material is present, then the substrate is inspected to ensure that the spacer areas are free of excess photoresist and the mylar is still intact, then the photomask with the desired design pattern is placed on the laminated substrate and the uv energy is set using a uv energy detector. The slower the speed of the exposure conveyor at this time, the higher the ultraviolet energy.
Further, during process 103, a developer having the desired alkali concentration and pH is required and the correct speed, chemical pressure, city water pressure, deionized water pressure, and water tank temperature are set. At the same time, the polyester film is surely removed from the substrate before being loaded into the developing machine. The front and back sides of the substrate are inspected and cleaned of any resist debris.
Further, process 104 is to prevent silver discoloration problems after substrate removal by plating a 15um tin (Sn) layer over the pattern formed on the stainless steel/copper. The tin-plated layer will serve as a protective layer and be ready for continued use on future electronic PCB assemblies.
Further, process 105 refers to using a bake oven or conveyor to harden the photoresist and is ready for the backfill process.
Further, process 106 is to print silver paste onto the patterned substrate using a printer. The hardness of the front and rear adhesive tape of the installation machine is set to be 100-150, the scratch board is ensured to be flat and then the scratch board bracket is installed, and simultaneously, the silver paste is ensured to be rotated before use so as to obtain uniform silver paste. Before backfilling, the substrate is air purged to remove any potential foreign material (as applicable), particularly debris or silver particles. After backfilling, excess silver was removed from the edges and back of the substrate.
Further, in process 107, firing is a heating process that is used to burn off the photoresist on the substrate, leaving only the metal. The sintering process converts the silver paste into silver metal in the same time period. A silver-tin (Ag-Sn) alloy interlayer is also formed at this time. After the sintering process is complete, air guns may be used to blow off any surface particles, if necessary. The temperature of the process 107 is controlled at 220 ℃.
According to the technical scheme, the tin-plated layer is used as the protective layer through the electroplating process, the silver discoloration problem is effectively avoided, and meanwhile, the influence of the softness of the silver on the adhesiveness can be solved by using the thin silver in the backfilling process.
Example 2
Based on the above embodiment 1, this embodiment describes an integrated circuit assembly process in a flexible coreless 3D printed integrated circuit molding process.
Referring to fig. 2, fig. 2 is a flowchart illustrating an integrated circuit assembly process in a flexible coreless 3D printed integrated circuit molding process according to the present invention; referring to fig. 5, fig. 5 is a schematic cross-sectional view of a silver-tin (Ag-Sn) alloy interlayer in a flexible coreless 3D printed integrated circuit molding process according to the present invention; referring to fig. 6, fig. 6 is a silver-tin (Ag-Sn) system equilibrium phase diagram in a flexible coreless 3D printed integrated circuit molding process according to the present invention; referring to fig. 7, fig. 7 is a schematic diagram illustrating an etching back process in a flexible coreless 3D printed integrated circuit molding process provided by the present invention.
The integrated circuit assembly process flow comprises the following steps:
201. flip chip applications;
202. molding;
203. back side etching.
Further, the process 201 refers to picking and placing the desired flip chip on a dedicated silver pad, followed by a corresponding curing. Solidification results in fusion between silver and tin, which enables the formation of a thin silver-tin (Ag-Sn) alloy with high mechanical strength, thermal fatigue properties and wettability.
Further, process 202 means that the package after flip chip application will undergo a molding process.
Further, during process 203, the substrate removal will be performed using an etch back process, and the designed substrate-less package will produce a lighter weight, thinner assembly.
The technical solution of this embodiment is based on embodiment 1, and is to perform fusion between silver and tin through a solidification process to form a silver-tin (Ag-Sn) alloy having high mechanical strength, thermal fatigue properties, and wettability, and to use a back-etching process to more easily remove a metal substrate, leaving a clean assembly.
Example 3
Based on the above embodiment 1 or 2, in order to further illustrate the technical effect of the technical solution of the present invention, the present embodiment compares and analyzes the present invention and the conventional CSI process.
Referring to fig. 8, fig. 8 is a comparison of substrate configurations of a CSI process and a flexible coreless 3D printed integrated circuit molding process provided herein; during the initial stages of the CSI technique, a stainless steel substrate was used and pre-treated at a high temperature of 950 ℃ to provide an easily adaptable environment for the later silver paste. Under such high temperature conditions, the stainless steel substrate starts to deform and causes warpage during die bonding, wire bonding, and molding. The concept of the present invention is to avoid material degradation caused by repeated pre-treatments of metal substrates using high temperature environments.
Referring to fig. 9, fig. 9 is a schematic diagram illustrating a comparison between a CSI process and a silver printing process of a flexible coreless 3D printed integrated circuit molding process provided in the present application; in the silver printing process section, the CSI uses self-formulated silver as a paste (average silver thickness of about 45 μm) to control the flow and printability during silver printing. The thickness and nature of silver causes problems with bondability. Also, silver paste needs to be sintered at 850 ℃ and causes stainless steel to warp. At the same time, the use of large amounts of silver increases the construction costs of the material.
Through the comparison, the invention reduces the sintering temperature of silver, avoids the problem of material warping, uses lower silver thickness and saves material cost.
The release mechanism of the molded substrate in the CSI process also leads to some technical problems related to mold cracks, silver bubbles and voids. During the removal of the substrate, excessive peel forces are applied to the molded part. This peel force is the root cause of the above-mentioned situation. Referring to fig. 10, fig. 10 is a schematic diagram illustrating a mold substrate peeling process in a CSI process.
In order for a die crack to occur, the peel force of the Ag-stainless steel must be greater than that of the Ag-molding compound, in the following order: first the silver will tear off and then the mould will crack from the inside to the outside and if the situation is severe. To solve this problem, the present invention employs an etch-back process to remove the metal substrate. In such a process, the metal substrate is easily removed and does not affect the internal structure of the molded part.
Referring to fig. 11, fig. 11 is a schematic diagram illustrating a comparison between a CSI process and a molding profile of a flexible coreless 3D printed integrated circuit molding process provided in the present application. Silver in the CSI process is directly exposed and contacted with air, and discoloration is easy to occur, and the tin-plated molded component is used as a silver protective layer to avoid discoloration aiming at the weakness of the silver discoloration problem.
While the invention has been described with respect to a preferred embodiment, it will be understood by those skilled in the art that the foregoing and other changes, omissions and deviations in the form and detail thereof may be made without departing from the scope of this invention. Those skilled in the art can make various changes, modifications and equivalent arrangements, which are equivalent to the embodiments of the present invention, without departing from the spirit and scope of the present invention, and which may be made by utilizing the techniques disclosed above; meanwhile, any changes, modifications and variations of the above-described embodiments, which are equivalent to those of the technical spirit of the present invention, are within the scope of the technical solution of the present invention.
Claims (10)
1. A flexible coreless 3D printed integrated circuit die pressing process is characterized in that: includes an integrated circuit carrier process;
the integrated circuit carrier process flow comprises the following steps:
101. laminating;
102. exposing;
103. carrying out development;
104. electroplating;
105. baking the photoresist;
106. backfilling;
107. firing/sintering.
2. The flexible coreless 3D printed integrated circuit embossing process of claim 1, wherein: the process 101 must be performed in a yellow room while ensuring that the laminated substrate remains in the yellow room during the UV exposure machine used to perform the process 102.
3. The flexible coreless 3D printed integrated circuit embossing process of claim 1, wherein: the process 104 refers to plugging a 15um tin (Sn) layer on a cluster formed on stainless steel/copper.
4. The flexible coreless 3D printed integrated circuit embossing process of claim 1, wherein: the process 105 refers to hardening the photoresist using a bake oven or conveyor.
5. The flexible coreless 3D printed integrated circuit embossing process of claim 1, wherein: the process 106 is to print silver paste on a pattern substrate by using a printer, and the hardness of the front and rear scraping strips of the machine is 100-150.
6. The flexible coreless 3D printed integrated circuit embossing process of claim 5, wherein: thinner silver is used during the process 106.
7. The flexible coreless 3D printed integrated circuit embossing process of claim 1, wherein: the process 107 was controlled at 220 ℃ for 120 minutes.
8. The flexible coreless 3D printed integrated circuit embossing process of any one of claims 1 to 7, wherein: also includes the integrated circuit assembly process;
the integrated circuit assembly process flow comprises the following steps:
201. flip chip applications;
202. molding;
203. back side etching.
9. The flexible coreless 3D printed integrated circuit embossing process of claim 8, wherein: the process 201 refers to picking and placing the desired flip chip on a dedicated silver pad and then curing accordingly.
10. The flexible coreless 3D printed integrated circuit embossing process of claim 8, wherein: the process 203 refers to removing the substrate by using an etch-back process.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111247805.2A CN113990761A (en) | 2021-10-26 | 2021-10-26 | Flexible coreless 3D printed integrated circuit die pressing process |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111247805.2A CN113990761A (en) | 2021-10-26 | 2021-10-26 | Flexible coreless 3D printed integrated circuit die pressing process |
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| CN113990761A true CN113990761A (en) | 2022-01-28 |
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| CN202111247805.2A Pending CN113990761A (en) | 2021-10-26 | 2021-10-26 | Flexible coreless 3D printed integrated circuit die pressing process |
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