CN113987978A - Generation method and device of simulation netlist of arrayed device and simulation verification method - Google Patents

Generation method and device of simulation netlist of arrayed device and simulation verification method Download PDF

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CN113987978A
CN113987978A CN202111189729.4A CN202111189729A CN113987978A CN 113987978 A CN113987978 A CN 113987978A CN 202111189729 A CN202111189729 A CN 202111189729A CN 113987978 A CN113987978 A CN 113987978A
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basic unit
module
unit module
netlist
coordinate
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蒙奕帆
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Shanghai Anlu Information Technology Co ltd
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    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

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Abstract

The invention belongs to the technical field of arrayed devices, and discloses a method and a device for generating a simulation netlist of an arrayed device and a simulation verification method, wherein the generation method comprises the following steps: selecting a basic unit module in the arrayed device as a coordinate system origin, establishing a two-dimensional coordinate system to carry out coordinate marking on all modules, taking the coordinate marking of the basic unit module as an example name of the basic unit module, taking the coordinate marking of the non-basic unit module and the name of the non-basic unit module as example names to obtain a Verilog hardware netlist, screening the Verilog hardware netlist according to a preset resource log, reserving modules with the example names recorded in the resource log, and obtaining a first netlist corresponding to a simulation case. Has the advantages that: the simulation netlist generation method can effectively reduce the netlist scale in the simulation process, further greatly reduce the compiling time and the required storage space in the simulation verification process, and greatly improve the simulation verification efficiency.

Description

Generation method and device of simulation netlist of arrayed device and simulation verification method
Technical Field
The invention relates to the technical field of arrayed devices, in particular to a method and a device for generating a simulation netlist of an arrayed device and a simulation verification method.
Background
With the continuous updating and upgrading of micro-nano technology nodes, various chip scales gradually develop towards the advanced directions of higher integration level, higher density, more tiny basic unit degree and the like. However, as the scale increases, the correctness of the internal functions becomes more difficult to verify, and especially, the correctness of the arrayed devices having strong correlation with each other, such as the general purpose chips of FPGA, DSP, SOC + FPGA/DSP, etc., is especially difficult to verify on a million-gate or even billion-gate scale.
In the existing verification process, due to the fact that the netlist of a chip is very large in scale, the compiled netlist can be expanded by one to two orders of magnitude, a large amount of storage space is occupied, a large amount of storage space needs to be prepared for storage, and meanwhile a waveform file generated by simulation after compiling occupies a large amount of storage space and is low in processing speed. The verification method according to the prior art requires at least three hours for compiling once and at least one and a half hours for simulating once, which seriously reduces the verification efficiency.
Therefore, it is necessary to improve the verification method in the prior art, reduce the information storage requirement in the verification process, increase the compiling and verification speed, and increase the efficiency of the correctness verification.
Disclosure of Invention
The purpose of the invention is: the verification method in the prior art is improved, the information storage requirement in the verification process is reduced, the compiling and verifying speed is increased, and the correctness verification efficiency is improved.
In order to achieve the above object, the present invention provides a method for generating a simulation netlist of an arrayed device, including:
selecting one basic unit module in the arrayed device as a coordinate system origin, and carrying out coordinate marking on all the residual basic unit modules by using the coordinate system origin to obtain coordinates of all the basic unit modules; the array device comprises a basic unit module and a non-basic unit module, wherein the basic unit module is a module which has the largest array times and the smallest physical area in the array device.
And carrying out coordinate marking on adjacent non-basic unit modules according to the coordinate marks of the basic unit modules, wherein any one non-basic unit module is bound to be adjacent to at least one non-basic unit module.
And taking the coordinate mark of the basic unit module as an instantiation name of the basic unit module, and taking the coordinate mark of the non-basic unit module and the name of the non-basic unit module as instantiation names to obtain the Verilog hardware netlist.
And screening a module for reserving instantiation names recorded in the resource logs on the Verilog hardware netlist according to a preset resource log to obtain a first netlist corresponding to the simulation case, wherein the resource log is compiled according to the simulation case.
Further, the basic unit module is an array module, and the non-basic unit module includes: an IP module and an IO module.
Further, the selecting a basic unit module in the arrayed device as the origin of the coordinate system specifically includes:
and judging whether the modules at the four corners in the arrayed device are basic unit modules or not, and if the module at one corner in the four corners is the basic unit module, taking the basic unit module in the corner as the origin of the coordinate system.
And if the modules in the four corners are all non-basic unit modules, taking the first basic unit module on the left side or the right side of the non-basic unit module in the corner as the origin of the coordinate system.
Further, the coordinate marking of all the remaining basic unit modules by using the origin of the coordinate system specifically includes:
the origin of the coordinate system is marked as x0y 0; in the horizontal direction, the x coordinate of the basic unit module on the right side of the origin of the coordinate system is increased progressively, and the x coordinate of the basic unit module on the left side of the origin of the coordinate system is decreased progressively; in the vertical direction, the y-coordinate of the base unit module on the upper side of the origin of the coordinate system increases progressively, and the y-coordinate of the base unit module on the lower side of the origin of the coordinate system decreases progressively.
Further, the coordinate marking of the adjacent non-basic unit module according to the coordinate marking of the basic unit module specifically includes:
and when the non-basic unit module is adjacent to a plurality of basic unit modules, taking the coordinate mark of the basic unit module at the lower left corner of the non-basic unit module as the coordinate mark of the non-basic unit module.
If the left lower corner of the non-basic unit module has no basic unit module, the coordinate mark of the basic unit module at the right lower corner of the non-basic unit module is used as the coordinate mark of the non-basic unit module.
Further, the resource log is compiled according to the simulation case, specifically:
and compiling a plurality of simulation cases according to verification requirements, wherein each simulation case can be singly corresponding to a preset function.
Inputting a plurality of compiled simulation cases into software for compiling, carrying out resource selection after the software is compiled, and generating a resource list of a required device, wherein resource names in the resource list are matched with instantiated names in a Verilog hardware netlist.
And generating a resource log according to the resource list.
Further, the step of screening the Verilog hardware netlist according to a preset resource log and reserving a module of the instantiation name record in the resource log to obtain a first netlist corresponding to the simulation case includes:
and acquiring the instantiated name of the required module according to the resource log.
Traversing each instantiated name of the Verilog hardware netlist, judging whether the instantiated name is in a resource log, if so, retaining a module corresponding to the instantiated name, and if not, deleting the module corresponding to the instantiated name.
And after traversing, generating a first netlist which uniquely corresponds to the simulation case.
The invention also discloses a device for generating the simulation netlist of the arrayed device, which comprises the following components: the device comprises a first coordinate marking module, a second coordinate marking module, an example name module and a netlist generating module.
The first coordinate marking module is used for selecting one basic unit module in the arrayed device as a coordinate system origin, and marking coordinates of all the residual basic unit modules by using the coordinate system origin to obtain coordinates of all the basic unit modules; the array device comprises a basic unit module and a non-basic unit module, wherein the basic unit module is a module which has the largest array times and the smallest physical area in the array device.
The second coordinate marking module is used for carrying out coordinate marking on adjacent non-basic unit modules according to the coordinate marking of the basic unit module, and any one non-basic unit module is bound to be adjacent to at least one non-basic unit module.
The instantiation name module is used for taking the coordinate mark of the basic unit module as the instantiation name of the basic unit module and taking the coordinate mark of the non-basic unit module and the name of the non-basic unit module as the instantiation names to obtain the Verilog hardware netlist.
The netlist generation module is used for screening the Verilog hardware netlist according to a preset resource log, reserving a module of the instantiation name record in the resource log, and obtaining a first netlist corresponding to the simulation case, wherein the resource log is compiled according to the simulation case.
Further, the basic unit module is an array module, and the non-basic unit module includes: an IP module and an IO module.
The invention also discloses a simulation verification method of the arrayed device, which applies the first netlist to recompile and carry out simulation verification.
Compared with the prior art, the method, the device and the simulation verification method for generating the simulation netlist of the arrayed device have the advantages that: the simulation netlist generation method can effectively reduce the netlist scale in the simulation process, further greatly reduce the compiling time and the required storage space in the simulation verification process, and greatly improve the simulation verification efficiency.
Drawings
FIG. 1 is a schematic flow chart of a method for generating a simulated netlist of an arrayed device according to the present invention;
FIG. 2 is a schematic diagram of one embodiment of the arrayed device of the invention to establish a two-dimensional coordinate system;
FIG. 3 is a schematic flow chart of obtaining a first netlist according to a simulation case;
FIG. 4 is a schematic diagram of one embodiment of a resource log of the present invention;
FIG. 5 is a schematic diagram of one embodiment of a first netlist of the present invention;
FIG. 6 is a comparison of the effects of applying the simulation verification method of the present invention and the prior art verification method;
FIG. 7 is a schematic structural diagram of an apparatus for generating an arrayed device simulation netlist according to the present invention.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
The english abbreviations appearing in the present application are explained. FPGA (field Programmable Gate array); a DSP (digital Signal processor); SOC (System On chip); IP core (Intellectual property core); intellectual property core io (input output) input and output.
Further explanation is made on the technical problems mentioned in the background art.
In the present application, after the applicant researches the prior art, it is found that as the scale of a chip increases, the correctness of the internal function becomes more and more difficult to verify, especially for arrayed devices having strong correlation with each other, such as an FPGA, a DSP, an SOC + FPGA/DSP, and other general chips. The size of these chips is often in the tens of millions of gates or even hundreds of millions of gates, and the verification of the correctness is particularly difficult.
Applicants will illustrate in more detail the logic capacity 400k FPGA device, which may encounter the following problems:
1. the netlist of the chip itself is very large in size, and only comprises the most basic programmable logic units and programmable routing units in the FPGA, and the netlist itself already has the size of 900Mb (excluding the rest modules such as input/output (IO)/block memory (BRAM)/Digital Signal Processor (DSP)/Clock network (Clock Tree)).
2. The linkage problem caused by 1 is that the database is extremely huge after compiling is finished and is close to 30 Gb.
3. The chaining problem caused by 2, that is, each time the waveform simulated after compiling is used, even if the detailed waveform inside any module is not loaded (dump), the waveform file with the size of nearly 5Gb is possessed.
4. 3, when the number of dump modules is small, the waveform time of turning on a signal is 5 minutes; when the number of modules of dump is large, the time for turning on a signal is far more than 10 minutes.
5. The problems mentioned above with 1-4 result in at least 3 hours per compilation and 1.5 hours for simulation.
Due to the many objective problems mentioned above, verification across a chip can also cause other problems, including:
1. the method comprises the steps that a large enough memory space is not available, and a netlist, a compiled file and a waveform file are stored under different simulation cases (cases); if the storage is forced, precious storage resources are greatly wasted.
2. When the simulation case is not verified once, or the design is modified, the case needs to be re-run once, so that the design modification or the case modification can be correct. Each run requires approximately 4.5 hours, when the design is not correct, the run time may be longer and much longer than 4.5 hours, and this is a time cost of one modification, which may be longer when there is too much modification.
3. When the number of simulation cases is large, such a method is very time-consuming, and if the compiled files can be reused each time, each case simulation needs at least 1.5 hours, and it is difficult to do the simulation in a short time when there are many cases.
4. When the simulation case only uses some parts of resources, even if compiling is completed, 1.5 hours of simulation time is also needed, which is not worth paying, and valuable testing time is wasted.
By synthesizing the problems, the scale of the netlist has direct influence on a series of subsequent problems, and if the scale of the netlist can be effectively reduced, the efficiency of simulation verification can be fundamentally improved and the data capacity in the process of simulation verification can be greatly saved.
Therefore, in embodiment 1, the present invention first provides a method for generating a simulation netlist, which can fundamentally reduce the scale of the simulation netlist, improve the simulation efficiency, and reduce the data capacity during the simulation process.
Example 1:
as shown in FIG. 1, the invention discloses a method for generating a simulation netlist of an arrayed device, comprising the following steps:
step S1, selecting one basic unit module in the arrayed device as a coordinate system origin, and carrying out coordinate marking on all the residual basic unit modules by using the coordinate system origin to obtain the coordinates of all the basic unit modules; the array device comprises a basic unit module and a non-basic unit module, wherein the basic unit module is a module which has the largest array times and the smallest physical area in the array device.
In step S2, coordinate marks are performed on adjacent non-basic unit modules according to the coordinate marks of the basic unit modules, and any one non-basic unit module is bound to be adjacent to at least one non-basic unit module.
And step S3, taking the coordinate mark of the basic unit module as the instantiation name of the basic unit module, and taking the coordinate mark of the non-basic unit module and the name of the non-basic unit module as the instantiation names, so as to obtain the Verilog hardware netlist.
And step S4, screening the Verilog hardware netlist according to a preset resource log, reserving a module of the instantiation name record in the resource log, and obtaining a first netlist corresponding to the simulation case, wherein the resource log is compiled according to the simulation case.
In order to better understand the technical solution, a basic description is made on the arrayed device, and referring to fig. 2, a plurality of small modules are arranged on the arrayed device, wherein the small modules include basic unit modules and non-basic unit modules. The basic unit module is generally the module with the largest arraying times and the smallest physical area, and the non-basic unit module is the complement of the basic unit module.
In this embodiment, an alternative implementation of the arrayed device is provided, in which the basic cell module is an array module, and the non-basic cell module includes: an IP module and an IO module. The skilled person can select the corresponding basic cell module and non-basic cell module according to the actual arrayed device.
In this implementation, it is emphasized that the length or width of the non-base unit module is an integer multiple of the length or width of the base unit module. Therefore, the length and width of the IP module and the IO module are integral multiples of the length and width of the array module. Specifically, the method comprises the following steps: the length of the IP module is twice that of the array module, the width of the IP module is three times that of the array module, the length of the IO module is 1 time that of the array module, and the width of the IO module is two times that of the array module. The size of the non-basic module can be adjusted by those skilled in the art according to actual needs, including but not limited to the examples described above.
In step S1, one basic unit module in the arrayed device is selected as a coordinate system origin, and coordinates of all the remaining basic unit modules are labeled with the coordinate system origin to obtain coordinates of all the basic unit modules, where the arrayed device includes the basic unit modules and the non-basic unit modules, and the basic unit module is a module with the largest number of arrayed times and the smallest physical area in the arrayed device.
In this embodiment, the selecting a basic unit module in the arrayed device as the origin of the coordinate system specifically includes:
judging whether the modules at the four corners in the arrayed device are basic unit modules or not, and if the module at one corner in the four corners is a basic unit module, taking the basic unit module in the corner as the origin of a coordinate system;
and if the modules in the four corners are all non-basic unit modules, taking the first basic unit module on the left side or the right side of the non-basic unit module in the corner as the origin of the coordinate system.
In this embodiment, the module is subjected to two-dimensional coordination during netlist generation, which is beneficial to software and hardware synchronization and convenient for processing.
Establishing a better coordinate system origin can better mark coordinates of each module in the arrayed device, and simultaneously can reduce the complexity of data storage. The origin of the preferred coordinate system should be the basic unit module of the four corners of the arrayed device. The most preferable basic unit module which is the lower left corner can enable the whole arrayed device to fall into the first quadrant of the coordinate system, the complexity of coordinate expression is reduced, and the negative sign is avoided.
In this embodiment, the coordinate marking of all the remaining basic unit modules by using the origin of the coordinate system specifically includes:
the origin of the coordinate system is marked as x0y 0; in the horizontal direction, the x coordinate of the basic unit module on the right side of the origin of the coordinate system is increased progressively, and the x coordinate of the basic unit module on the left side of the origin of the coordinate system is decreased progressively; in the vertical direction, the y-coordinate of the base unit module on the upper side of the origin of the coordinate system increases progressively, and the y-coordinate of the base unit module on the lower side of the origin of the coordinate system decreases progressively.
In step S2, adjacent non-basic-unit modules are coordinate-labeled based on the coordinate labels of the basic-unit modules, and any one non-basic-unit module necessarily adjoins at least one non-basic-unit module.
In this embodiment, the coordinate marking of the adjacent non-basic unit module according to the coordinate marking of the basic unit module specifically includes:
when the non-basic unit module is adjacent to a plurality of basic unit modules, taking the coordinate mark of the basic unit module at the lower left corner of the non-basic unit module as the coordinate mark of the non-basic unit module;
if the left lower corner of the non-basic unit module has no basic unit module, the coordinate mark of the basic unit module at the right lower corner of the non-basic unit module is used as the coordinate mark of the non-basic unit module.
In order to better describe step 1 and step 2, the arrayed device in fig. 2 is actually exemplified, in fig. 2, when the arrayed device designs a netlist, a module-array module with the largest arraying frequency and the smallest physical area is used as the most basic unit, the length and the width of the array module are used as the smallest coordinate measurement unit, the basic unit at the leftmost lower corner of the full chip except the IO module array is used as the origin of a coordinate system to construct a two-dimensional rectangular coordinate system, and the origin of the coordinate is denoted as x0y 0. In the horizontal direction, the x-coordinate of each basic unit is gradually increased to the right and gradually decreased to the left. In the vertical direction, the coordinates of each basic unit are gradually increased upwards and gradually decreased downwards. In the full-chip netlist, no matter any digital intellectual property core (IP core)/array module/input/output (IO), a coordinate position needs to be set, and the coordinate of the coordinate is consistent with the array basic unit closest to the lower left corner of the full-chip netlist. In the present application, all circuit modules need to exist independently, and cannot contain basic repeating units, and cannot be combined with other modules with unrelated functions to form a new module to appear in the netlist. When a certain IP/IO module is positioned at the leftmost side of the chip and no array module is arranged at the lower left corner, the array module coordinate at the lower right corner is taken as the coordinate of the module. Taking the IOB module on the left in fig. 2 as an example, the nearest basic unit is only x0y0, so its coordinate is x0y 0. Because the height of an IOB accounts for 2 bins, it adds two to every third bin, the y coordinate. Other modules also make coordinate selection according to the rule.
In step S3, the coordinate labels of the basic cell modules are used as instantiation names of the basic cell modules, and the coordinate labels of the non-basic cell modules and the names of the non-basic cell modules are used as instantiation names, so as to obtain a Verilog hardware netlist.
In this embodiment, referring to fig. 2, the instantiated names of the array modules in the netlist are the same as their coordinate names, and the instantiated names of the IP modules/IO in the netlist are the module names + "_" + coordinate names, based on which the Verilog hardware netlist is generated. In this embodiment, adding "___" can conveniently distinguish name and coordinate name, which is a more preferable technical solution.
In step S4, a module in which the instantiation name is recorded in the resource log is screened from the Verilog hardware netlist according to the preset resource log, so as to obtain a first netlist corresponding to the simulation case, where the resource log is compiled according to the simulation case.
In this embodiment, referring to fig. 3, the resource log is compiled according to a simulation case, specifically:
compiling a plurality of simulation cases according to verification requirements, wherein each simulation case can be singly corresponding to a preset function;
inputting a plurality of compiled simulation cases into software for compiling, performing resource selection after the software is compiled, and generating a resource list of a required device, wherein resource names in the resource list are matched with instantiated names in a Verilog hardware netlist;
and generating a resource log according to the resource list.
In this embodiment, the matching of the resource name in the resource list and the instantiated name in the Verilog hardware netlist specifically includes: and the software directly generates a hardware resource list according to the optimization result of the case, and the names correspond to the instantiated names of the hardware one by one. The treatment method can bring the following beneficial effects:
(1) whether the hardware resources are used or not is determined by software, and the accuracy of hardware resource operation is greatly improved.
(2) The resource list generated by the software is the same as the hardware instantiated name, so that the correctness and the rationality of the operation are greatly improved
(3) The flexibility of netlist operation can be greatly improved by operating the netlist through software.
In this embodiment, referring to fig. 4, fig. 4 is a schematic diagram of an embodiment of a resource log.
In this embodiment, referring to fig. 3, the step of screening the Verilog hardware netlist according to the preset resource log and retaining a module of the instantiation name recorded in the resource log to obtain a first netlist corresponding to the simulation case specifically includes:
acquiring an instantiated name of a required module according to the resource log;
traversing each instantiated name of the Verilog hardware netlist, judging whether the instantiated name is in a resource log, if so, retaining a module corresponding to the instantiated name, and if not, deleting the module corresponding to the instantiated name;
and after traversing, generating a first netlist which uniquely corresponds to the simulation case.
In the implementation method, hardware resources which are not used by software are directly deleted for simulation, the netlist scale is directly simplified, and the simulation time is optimized.
Referring to FIG. 5, FIG. 5 is a diagram of an embodiment of a first netlist.
By combining the steps, the technical scheme of the application obtains the netlist with few contained modules, and the scale of the netlist is greatly reduced. Those skilled in the art can no doubt presume that the speed of compilation and simulation will increase substantially as the size of the netlist decreases substantially.
Referring to fig. 6, fig. 6 is a comparison graph of simulation + compile time/netlist size/compile byproduct size of the simulation netlist and the unmodified netlist obtained by applying the above-mentioned simulation netlist generation method with reference to the minimum array module with a device size of 400 k.
In conclusion, the method for generating the simulation netlist of the arrayed device can greatly reduce the scale of the netlist, so that the compiling time and compiling byproducts in the simulation verification process are greatly reduced, and the simulation verification efficiency is greatly improved.
In the embodiment, the method can be used in verification regardless of the case, so that the time cost and the storage cost can be directly reduced.
Example 2:
referring to fig. 7, on the basis of embodiment 1, the present application further discloses an apparatus for generating a simulated netlist of an arrayed device, including: a first coordinate marking module 101, a second coordinate marking module 102, an instantiation name module 103, and a netlist generation module 104.
The first coordinate marking module 101 is configured to select one basic unit module in the arrayed device as a coordinate system origin, and mark coordinates of all remaining basic unit modules with the coordinate system origin to obtain coordinates of all basic unit modules; the array device comprises a basic unit module and a non-basic unit module, wherein the basic unit module is a module which has the largest array times and the smallest physical area in the array device.
The second coordinate marking module 102 is configured to perform coordinate marking on adjacent non-basic unit modules according to the coordinate marking of the basic unit module, where any one non-basic unit module necessarily adjoins at least one non-basic unit module.
The instantiation name module 103 is configured to use the coordinate label of the basic unit module as an instantiation name of the basic unit module, and use the coordinate label of the non-basic unit module and the name of the non-basic unit module as instantiation names to obtain a Verilog hardware netlist.
The netlist generation module 104 is configured to screen a Verilog hardware netlist according to a preset resource log, and obtain a first netlist corresponding to a simulation case by using a module that retains instantiation names recorded in the resource log, where the resource log is compiled according to the simulation case.
In this embodiment, the basic unit module is an array module, and the non-basic unit module includes: an IP module and an IO module.
Example 2 was written on the basis of example 1, and example 2 includes all the technical features of the examples. The definition and perfection of the method for generating the simulated netlist in embodiment 1 are also applicable to the device for generating the simulated netlist in embodiment 2.
Example 3:
on the basis of the embodiment 1, the invention also discloses a simulation verification method of the arrayed device, which is used for recompiling and carrying out simulation verification on the first netlist obtained by applying the generation method of the arrayed device simulation netlist in the embodiment 1.
To sum up, the embodiment of the invention provides a method and a device for generating a simulation netlist of an arrayed device and a simulation verification method, and the method has the advantages that:
(1) the simulation netlist generation method can effectively reduce the netlist scale in the simulation process, further greatly reduce the compiling time and the required storage space in the simulation verification process, and greatly improve the simulation verification efficiency.
(2) The invention separately tests different simulation cases, and only needs to test one simulation case once an error occurs, thereby greatly improving the debugging efficiency. If a large number of cases are compressed into a test excitation, a simulation can traverse a plurality of cases, if one of the cases is wrong, the design is modified once every error is found, the compiling/simulation is continued to iterate, and when a new error is caused after the previous error is corrected, the cases are repeated continuously. The simulation time is very time-consuming due to the cyclic reciprocating.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and substitutions can be made without departing from the technical principle of the present invention, and these modifications and substitutions should also be regarded as the protection scope of the present invention.

Claims (10)

1. A method for generating a simulation netlist of an arrayed device is characterized by comprising the following steps:
selecting one basic unit module in the arrayed device as a coordinate system origin, and carrying out coordinate marking on all the residual basic unit modules by using the coordinate system origin to obtain coordinates of all the basic unit modules; the array device comprises a basic unit module and a non-basic unit module, wherein the basic unit module is a module with the largest array times and the smallest physical area in the array device;
coordinate marking is carried out on adjacent non-basic unit modules according to the coordinate marks of the basic unit modules, and any one non-basic unit module is bound to be adjacent to at least one non-basic unit module;
taking the coordinate mark of the basic unit module as an instantiation name of the basic unit module, and taking the coordinate mark of the non-basic unit module and the name of the non-basic unit module as instantiation names to obtain a Verilog hardware netlist;
and screening a module for reserving instantiation names recorded in the resource logs on the Verilog hardware netlist according to a preset resource log to obtain a first netlist corresponding to the simulation case, wherein the resource log is compiled according to the simulation case.
2. The method for generating the arrayed device simulation netlist as claimed in claim 1, wherein the basic unit module is an array module, and the non-basic unit module comprises: an IP module and an IO module.
3. The method for generating the simulated netlist of the arrayed device according to claim 1, wherein one basic unit module in the arrayed device is selected as an origin of a coordinate system, and specifically:
judging whether the modules at the four corners in the arrayed device are basic unit modules or not, and if the module at one corner in the four corners is a basic unit module, taking the basic unit module in the corner as the origin of a coordinate system;
and if the modules in the four corners are all non-basic unit modules, taking the first basic unit module on the left side or the right side of the non-basic unit module in the corner as the origin of the coordinate system.
4. The method for generating the arrayed device simulation netlist as claimed in claim 1, wherein the coordinate labeling is performed on all the remaining basic unit modules by using a coordinate system origin, specifically:
the origin of the coordinate system is marked as x0y 0; in the horizontal direction, the x coordinate of the basic unit module on the right side of the origin of the coordinate system is increased progressively, and the x coordinate of the basic unit module on the left side of the origin of the coordinate system is decreased progressively; in the vertical direction, the y-coordinate of the base unit module on the upper side of the origin of the coordinate system increases progressively, and the y-coordinate of the base unit module on the lower side of the origin of the coordinate system decreases progressively.
5. The method for generating the arrayed device simulation netlist as claimed in claim 1, wherein the coordinate labeling is performed on the adjacent non-basic unit modules according to the coordinate labeling of the basic unit modules, specifically:
when the non-basic unit module is adjacent to a plurality of basic unit modules, taking the coordinate mark of the basic unit module at the lower left corner of the non-basic unit module as the coordinate mark of the non-basic unit module;
if the left lower corner of the non-basic unit module has no basic unit module, the coordinate mark of the basic unit module at the right lower corner of the non-basic unit module is used as the coordinate mark of the non-basic unit module.
6. The method for generating the simulation netlist of the arrayed device as claimed in claim 1, wherein the resource log is compiled according to a simulation case, and specifically comprises:
compiling a plurality of simulation cases according to verification requirements, wherein each simulation case can be singly corresponding to a preset function;
inputting a plurality of compiled simulation cases into software for compiling, performing resource selection after the software is compiled, and generating a resource list of a required device, wherein resource names in the resource list are matched with instantiated names in a Verilog hardware netlist;
and generating a resource log according to the resource list.
7. The method for generating the arrayed device simulation netlist as claimed in claim 1, wherein the module for screening the Verilog hardware netlist according to the preset resource log and retaining the instantiation names recorded in the resource log is used to obtain the first netlist corresponding to the simulation case, and specifically comprises:
acquiring an instantiated name of a required module according to the resource log;
traversing each instantiated name of the Verilog hardware netlist, judging whether the instantiated name is in a resource log, if so, retaining a module corresponding to the instantiated name, and if not, deleting the module corresponding to the instantiated name;
and after traversing, generating a first netlist which uniquely corresponds to the simulation case.
8. An apparatus for generating a simulated netlist of an arrayed device, comprising: the device comprises a first coordinate marking module, a second coordinate marking module, an instantiated name module and a netlist generating module;
the first coordinate marking module is used for selecting one basic unit module in the arrayed device as a coordinate system origin, and marking coordinates of all the residual basic unit modules by using the coordinate system origin to obtain coordinates of all the basic unit modules; the array device comprises a basic unit module and a non-basic unit module, wherein the basic unit module is a module with the largest array times and the smallest physical area in the array device;
the second coordinate marking module is used for carrying out coordinate marking on adjacent non-basic unit modules according to the coordinate marking of the basic unit module, and any one non-basic unit module is bound to be adjacent to at least one non-basic unit module;
the instantiation name module is used for taking the coordinate mark of the basic unit module as an instantiation name of the basic unit module and taking the coordinate mark of the non-basic unit module and the name of the non-basic unit module as instantiation names to obtain a Verilog hardware netlist;
the netlist generation module is used for screening the Verilog hardware netlist according to a preset resource log, reserving a module of the instantiation name record in the resource log, and obtaining a first netlist corresponding to the simulation case, wherein the resource log is compiled according to the simulation case.
9. The apparatus for generating an arrayed device simulation netlist as claimed in claim 8, wherein the basic unit module is an array module, and the non-basic unit module comprises: an IP module and an IO module.
10. A simulation verification method of an arrayed device is characterized in that a first netlist in the generation method of the simulation netlist of the arrayed device according to any one of claims 1 to 8 is applied for recompilation and simulation verification.
CN202111189729.4A 2021-10-12 2021-10-12 Generation method and device of simulation netlist of arrayed device and simulation verification method Pending CN113987978A (en)

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