CN113969396B - Preparation method of control wafer - Google Patents

Preparation method of control wafer Download PDF

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Publication number
CN113969396B
CN113969396B CN202010711734.6A CN202010711734A CN113969396B CN 113969396 B CN113969396 B CN 113969396B CN 202010711734 A CN202010711734 A CN 202010711734A CN 113969396 B CN113969396 B CN 113969396B
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titanium layer
wafer
silicon dioxide
radio frequency
layer
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CN113969396A (en
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陈扣林
周祖源
吴政达
林正忠
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SJ Semiconductor Jiangyin Corp
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Shenghejing Micro Semiconductor Jiangyin Co Ltd
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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/34—Sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/02—Pretreatment of the material to be coated
    • C23C14/024—Deposition of sublayers, e.g. to promote adhesion of the coating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C23C14/14—Metallic material, boron or silicon
    • C23C14/16—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon
    • C23C14/165—Metallic material, boron or silicon on metallic substrates or on substrates of boron or silicon by cathodic sputtering
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/54—Controlling or regulating the coating process
    • C23C14/541—Heating or cooling of the substrates
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • C23C16/402—Silicon dioxide
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/30—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
    • C23C28/32—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one pure metallic layer
    • C23C28/322—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one pure metallic layer only coatings of metal elements only
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/30—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer
    • C23C28/34—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates
    • C23C28/345—Coatings combining at least one metallic layer and at least one inorganic non-metallic layer including at least one inorganic non-metallic material layer, e.g. metal carbide, nitride, boride, silicide layer and their mixtures, enamels, phosphates and sulphates with at least one oxide layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment

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  • Chemical Kinetics & Catalysis (AREA)
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  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The invention provides a preparation method of a control wafer. The method comprises the following steps: 1) Providing a bare wafer, and forming a silicon dioxide layer; 2) Placing the bare wafer in a chamber with a radio frequency device for radio frequency heating, wherein the heating temperature is 100-150 ℃ and the heating time is 30-120 s; 3) And placing the heated bare wafer in a physical vapor deposition chamber, and sputtering to form a titanium layer, wherein the thickness of the titanium layer is more than 2000 angstroms. When the control wafer for debugging wet etching equipment is prepared, the bare wafer with the silicon dioxide layer formed on the surface is placed in the cavity with the radio frequency device for radio frequency heating, so that the thermal uniformity of the surface of the wafer can be effectively improved, the surface uniformity of a subsequently formed titanium layer and the adhesion between the subsequently formed titanium layer and the silicon dioxide layer can be improved, the surface uniformity of the titanium layer prepared by the preparation method is still very good when the surface uniformity of the titanium layer reaches more than 3000 angstroms, the surface color of the titanium layer is normal, the titanium layer can be used for debugging a wet etching machine table, the titanium layer can be repeatedly used, and the production cost can be reduced.

Description

Preparation method of control wafer
Technical Field
The invention belongs to the technical field of semiconductor packaging, and particularly relates to a preparation method of a control wafer.
Background
Wafer level packaging (Water Level Packaging, WLP for short) technology is a process flow in which a whole wafer is used as a packaging and testing object, and after packaging, the wafer is cut into individual finished chips, which is quite different from the conventional chip packaging process. The chip size packaged by the WLP process can be reduced by more than 20% compared with the chip size packaged by the traditional process, and the WLP packaging has the advantages of high packaging speed, low packaging cost and the like, so that the WLP packaging has become the main stream of the packaging market.
In the WLP packaging process, wet etching equipment (wet tool) is used for multiple times, for example, the wet etching equipment is used for cleaning to remove impurity particles on a wafer, or wet etching is used for forming a required pattern. Since there are hundreds or thousands of chips on a single wafer, and multiple wafers are typically processed simultaneously in the same wet etching apparatus, there is a significant economic penalty once the apparatus fails. It is very important to debug wet equipment prior to wet processing in a packaging plant (e.g., debug etch rate, liquid supply rate, etc.). One method of debugging wet process equipment commonly used at present is to put a monitor wafer (monitor wafer) with a titanium layer formed on the surface into wet process etching equipment before formal process treatment, and in this process, adjust various parameters of the equipment and observe the morphology change of the surface of the monitor wafer so as to finally debug the parameters of the equipment to be optimal. The wafer with the silicon dioxide layer formed on the surface is usually placed in a physical vapor deposition chamber after being simply cleaned, and is not heated or heated by a hot plate (namely, the wafer is placed on the hot plate, and the hot plate is electrified and heated to conduct heat to the wafer for heating), and then the titanium layer with a certain thickness is formed through sputtering. In the prior art, the titanium layer is usually about 1000 angstroms, and the surface flatness (namely thickness uniformity and surface uniformity) of the titanium layer can still meet the requirements because the titanium layer is relatively thin, and the surface color of the formed titanium layer is also normal. However, since the titanium layer is formed too thin, the control wafer can be used only once, resulting in an increase in production cost. The original method is that the wafer with the silicon dioxide layer formed on the surface is subjected to simple cleaning treatment, and is placed in physical vapor deposition equipment after being heated without a heating process or by a hot plate (i.e. the wafer is placed on the hot plate, the hot plate is electrified and heated to conduct heat to the wafer for heating), when the titanium layer is formed to more than 2000 angstroms, the surface flatness of the titanium layer is obviously reduced, especially when the titanium layer is deposited to 3000 angstroms, the surface flatness of the titanium layer is very poor, and the color of the surface is very different (blackened) from that when 1000 angstroms is deposited. Through observation under an electron microscope, holes exist in the titanium layer, and subsequent debugging finds that parameters meeting process requirements are difficult to debug on wet etching equipment by adopting the control wafer.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing a control wafer, which is used for solving the problem that when a control wafer for debugging wet etching equipment is manufactured by adopting an existing method, if a titanium layer on a surface of the control wafer is thinner, the control wafer can only be used once, resulting in an increase in production cost; if the titanium layer is deposited to more than 2000 angstroms, the uniformity of the surface of the titanium layer is reduced, holes appear in the titanium layer, the surface of the titanium layer is blackened, and the titanium layer is difficult to debug wet etching equipment and the like.
To achieve the above and other related objects, the present invention provides a method for preparing a control wafer, including the steps of:
1) Providing a bare wafer, and forming a silicon dioxide layer on the surface of the bare wafer;
2) Placing the bare wafer with the silicon dioxide layer in a chamber with a radio frequency device, and performing radio frequency heating under an inert gas atmosphere at a heating temperature of 100-150 ℃ for 30-120 s;
3) And placing the heated bare wafer in a physical vapor deposition cavity, and sputtering the surface of the silicon dioxide layer to form a titanium layer, wherein the thickness of the titanium layer is larger than 2000 angstroms.
Optionally, the heating temperature in the step 2) is 140 ℃, and the heating time is 45s.
Optionally, the titanium layer is formed to a thickness of 3000 to 5000 angstroms.
Alternatively, the method of forming the silicon oxide layer includes a thermal oxidation method and a chemical vapor deposition method.
Optionally, the silicon dioxide layer is formed to a thickness of 500 to 2000 angstroms.
Optionally, the chamber in step 2) is an ICP chamber.
Optionally, in the radio frequency heating process, the flow rate of the inert gas introduced into the cavity is 20-50 sccm.
As described above, when the control wafer for debugging wet etching equipment is prepared, the bare wafer with the silicon dioxide layer formed on the surface is placed in the chamber with the radio frequency device, and radio frequency heating is carried out in the inert gas atmosphere, so that the thermal uniformity of the wafer surface can be effectively improved, and the surface uniformity of the subsequently formed titanium layer and the adhesion between the silicon dioxide layer can be improved. The titanium layer prepared by the preparation method provided by the invention has good surface uniformity when the thickness of the titanium layer reaches more than 3000 angstroms, and the surface of the titanium layer has normal color, so that the titanium layer can be used for debugging a wet etching machine, can be repeatedly used, and is beneficial to reducing the production cost.
Drawings
Fig. 1 shows a flowchart of a method for preparing a control wafer according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
As shown in fig. 1, the present invention provides a method for preparing a control wafer, which includes the steps of:
s1: providing a bare wafer, and forming a silicon dioxide layer on the surface of the bare wafer;
s2: placing the bare wafer with the silicon dioxide layer in a chamber with a radio frequency device, and performing radio frequency heating under an inert gas atmosphere at a heating temperature of 100-150 ℃ for 30-120 s;
s3: and placing the heated bare wafer in a physical vapor deposition cavity, and sputtering the surface of the silicon dioxide layer to form a titanium layer, wherein the thickness of the titanium layer is larger than 2000 angstroms.
In the prior art, when preparing a control wafer for debugging wet etching equipment, when a titanium layer is sputtered, a bare wafer (i.e. a wafer with no device formed on the surface) is not heated and preheated, or the bare wafer is heated by adopting a hot plate heating mode, namely, the bare wafer is placed on the surface of a hot plate, and the hot plate is heated after being electrified, so that the bare wafer is heated through heat conduction. In the process of forming the titanium layer, if the formed titanium layer is thinner, for example, within 1000 angstroms, the thickness uniformity of the titanium layer is still good, or the thickness difference of the titanium layer is not obvious, so that the bare wafer heated by the hot plate can also be used for debugging a wet etching machine, but because the titanium layer is too thin, the control wafer needs to re-sputter the titanium layer only once, so that the production cost is increased, and the quality of the subsequently sputtered titanium layer is difficult to ensure. The inventors tried to sputter the thickness of the titanium layer to 2000 angstroms or more after heating by the original method, but found that the uniformity of the thickness of the titanium layer was drastically reduced, and especially when the titanium layer was increased to 3000 angstroms or more, the surface of the titanium layer exhibited serious unevenness and the surface color of the titanium layer was blackened. The inventors found that pores exist inside the titanium layer by observation with an electron microscope. When the control chip is adopted to debug wet etching equipment, the parameters such as the etching rate and the like cannot meet the process production requirements, namely the control chip has lost the original meaning. The inventors have studied repeatedly, and found that this is because the hot plate is heated unevenly and the temperature is controlled inaccurately, and the cleanliness in the chamber with the hot plate is usually not high, the internal impurity particles may fall on the surface of the bare wafer, or the surface of the bare wafer is affected by the particle impurities originally (the size of the particle impurities is uneven and also affects the heating), so the heated surface of the bare wafer is not even in temperature, resulting in poor uniformity of the subsequently formed titanium layer and reduced adhesion with the silicon dioxide layer. Therefore, the inventor adopts a chamber with a radio frequency device (comprising a radio frequency power supply, a radio frequency coil and the like) after multiple experiments, such as an ICP chamber (inductively coupled plasma) for carrying out radio frequency heating on a wafer, and the heating process is carried out under an inert gas atmosphere, such as continuously introducing inert gas such as nitrogen into the chamber in the heating process, the wafer can be placed on an electrostatic chuck for fixing, molecules of the inert gas move to the surface of the wafer under the excitation of radio frequency energy to heat the wafer, and even if impurity particles remain in the chamber or particle impurities exist on the surface of a bare wafer, the heating uniformity of the surface of the bare wafer can be effectively improved, and the impurity particles on the surface of the wafer can be removed by the inert gas molecules. When the bare wafer heated uniformly is placed in physical vapor deposition equipment, even if the deposited titanium layer reaches more than 2000 angstroms, the titanium layer still presents good thickness uniformity, has normal color and luster and good adhesion with the silicon dioxide layer, and no holes exist in the titanium layer after observation under an electron microscope. When the control chip prepared by the method is used for debugging a wet etching machine, each debugged parameter completely meets the process production requirement, the control chip can be used for multiple times, and the production cost can be effectively reduced.
The bare wafer, i.e., the wafer with no device formed on the surface, includes but is not limited to a silicon wafer, a gallium nitride wafer, a gallium arsenide wafer, etc., and the specific material is preferably consistent with the material of the wafer to be subjected to the subsequent wet etching process.
Of course, the thickness of the titanium layer is not limited to increase. The inventors have found through many experiments that even when the preparation method of the present invention is used, the surface uniformity of the titanium layer is reduced when the thickness of the titanium layer reaches more than 5000 angstroms, and thus the thickness of the formed titanium layer is preferably 3000 to 5000 angstroms (inclusive), and particularly, the surface flatness is preferable at about 3000 angstroms. In other examples, the titanium layer may also be planarized using a chemical mechanical polishing process after deposition to form the titanium layer, such as polishing to improve the thickness uniformity of the titanium layer surface when the titanium layer is over 4000 angstroms thick.
The inventors found that the heating effect is particularly good when the heating temperature in the step 2) is 140 ℃. And in a further example, the heating time is 45s.
The flow rate of the inert gas introduced in the heating process is not too large or too small, and the inventor finds that the flow rate of the inert gas is more suitable in the range of 20-50 sccm through multiple experiments.
As an example, the method of forming the silicon oxide layer includes a thermal oxidation method and a chemical vapor deposition method, and a chemical vapor deposition method is preferable. Because the silicon dioxide layer deposited by the chemical vapor deposition method is compact, the silicon dioxide layer can be better adhered to the titanium layer, and is not easy to be damaged in the process of debugging a machine. The thickness of the silicon dioxide layer is preferably 500-2000 angstrom, and is too thin, so that the silicon dioxide layer is easy to damage in the process of multiple use to cause damage of a bare wafer, and too thick, the surface uniformity is reduced, defects such as warpage and the like are easy to occur, and defects such as warpage and the surface uniformity reduction and the like are easy to occur in a subsequently formed titanium layer.
In order to reduce pollution in the preparation process of the control wafer as much as possible and improve the preparation efficiency, the preparation process of the control wafer can be carried out in different chambers of the same equipment. For example, a bare wafer with a silicon dioxide layer formed on the surface is transferred from a wafer loading chamber (loadport) to an ICP chamber, the bare wafer is cleaned to remove impurities on the surface of the bare wafer, then the bare wafer is heated by a radio frequency device in the ICP chamber, inert gases such as nitrogen and the like are introduced in the heating process, and the bare wafer is transferred to a physical vapor deposition chamber to be sputtered to form a titanium layer with a preset thickness after being heated for a preset period of time. Since the ICP chamber itself is an etching machine, when necessary, after a bare wafer having a silicon dioxide layer formed on the surface is placed in the ICP chamber, the silicon dioxide layer on the surface can be removed by using an etching gas.
As described above, the present invention provides a method for preparing a control wafer. The preparation method comprises the following steps: 1) Providing a bare wafer, and forming a silicon dioxide layer on the surface of the bare wafer; 2) Placing the bare wafer with the silicon dioxide layer in a chamber with a radio frequency device, and performing radio frequency heating under an inert gas atmosphere at a heating temperature of 100-150 ℃ for 30-120 s; 3) And placing the heated bare wafer in a physical vapor deposition cavity, and sputtering the surface of the silicon dioxide layer to form a titanium layer, wherein the thickness of the titanium layer is larger than 2000 angstroms. When the control wafer for debugging wet etching equipment is prepared, the bare wafer with the silicon dioxide layer formed on the surface is placed in the chamber with the radio frequency device, and radio frequency heating is carried out under the inert gas atmosphere, so that the thermal uniformity of the surface of the wafer can be effectively improved, the surface uniformity of a subsequently formed titanium layer and the adhesiveness with the silicon dioxide layer can be improved, the surface uniformity of the titanium layer prepared by the preparation method is still very good when the surface uniformity of the titanium layer reaches more than 3000 angstroms, the surface color of the titanium layer is normal, the titanium layer can be used for debugging the wet etching equipment, the titanium layer can be repeatedly used, and the production cost can be reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (2)

1. The preparation method of the control wafer is characterized by comprising the following steps:
1) Providing a bare wafer, forming a silicon dioxide layer on the surface of the bare wafer, wherein the method for forming the silicon dioxide layer comprises a thermal oxidation method and a chemical vapor deposition method, and the thickness of the silicon dioxide layer is 500-2000 angstroms;
2) Placing the bare wafer with the silicon dioxide layer in a chamber with a radio frequency device, and performing radio frequency heating in an inert gas atmosphere at 140 ℃ for 45 seconds; in the radio frequency heating process, the flow rate of inert gas introduced into the cavity is 20-50 sccm;
3) And placing the heated bare wafer in a physical vapor deposition cavity, and sputtering the surface of the silicon dioxide layer to form a titanium layer, wherein the thickness of the titanium layer is 3000-5000 angstroms.
2. The method of manufacturing according to claim 1, characterized in that: the chamber in step 2) is an ICP chamber.
CN202010711734.6A 2020-07-22 2020-07-22 Preparation method of control wafer Active CN113969396B (en)

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Citations (2)

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KR19990060887A (en) * 1997-12-31 1999-07-26 김영환 Particle Detection Method of Semiconductor Manufacturing Equipment
CN102842500A (en) * 2011-06-22 2012-12-26 上海华虹Nec电子有限公司 Method for depositing liner silicon dioxide layer by utilizing high density plasma chemical vapor deposition (HDP-CVD) process

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US7465680B2 (en) * 2005-09-07 2008-12-16 Applied Materials, Inc. Post deposition plasma treatment to increase tensile stress of HDP-CVD SIO2

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990060887A (en) * 1997-12-31 1999-07-26 김영환 Particle Detection Method of Semiconductor Manufacturing Equipment
CN102842500A (en) * 2011-06-22 2012-12-26 上海华虹Nec电子有限公司 Method for depositing liner silicon dioxide layer by utilizing high density plasma chemical vapor deposition (HDP-CVD) process

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