CN102842500A - Method for depositing liner silicon dioxide layer by utilizing high density plasma chemical vapor deposition (HDP-CVD) process - Google Patents
Method for depositing liner silicon dioxide layer by utilizing high density plasma chemical vapor deposition (HDP-CVD) process Download PDFInfo
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- CN102842500A CN102842500A CN2011101704272A CN201110170427A CN102842500A CN 102842500 A CN102842500 A CN 102842500A CN 2011101704272 A CN2011101704272 A CN 2011101704272A CN 201110170427 A CN201110170427 A CN 201110170427A CN 102842500 A CN102842500 A CN 102842500A
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Abstract
The invention discloses a method for depositing a liner silicon dioxide layer by utilizing a high density plasma-chemical vapor deposition (HDP-CVD) process, and the method comprises a preheating step, wherein the preheating step is a previous step of a deposition step of the liner silicon dioxide layer; and the preheating step forms high density plasma inside a cavity and utilizes the high density plasma to heat a silicon sheet, so that the temperature of the silicon sheet is increased from the initial temperature of the cavity, and the final temperature of the silicon sheet after the preheating step can reach up to 400 degrees. Due to the adoption of the method, the liner silicon dioxide layer with poor viscosity which is formed by the small temperature at the beginning of forming the liner oxidized layer can be avoided, so that the viscosity force of the liner silicon dioxide layer and the silicon sheet can be enhanced, the particle problem caused by the stripping of the liner silicon dioxide layer can be avoided, and finally the yield of the product can be improved.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, particularly relate to the method for a kind of HDP-CVD (high-density plasma chemical vapor deposition) technology deposit pad silicon dioxide layer.
Background technology
HDP-CVD technology is one of conventional process during semiconductor integrated circuit is made; Have the advantages that in deposit, to carry out etching; Therefore; Existing HDP-CVD technology generally is used to fill the gap with high depth-to-width ratio, as filling intermetallic dielectric layer (PMD), before-metal medium layer (IMD), the shallow trench isolation gap from (STI) with the silicon dioxide layer that HDP-CVD technology forms.
In the manufacture craft of existing STI; The deposit of the general HDP-CVD of employing technology forms pad silicon dioxide layer (Liner Oxide); In the method for existing HDP-CVD technology deposit pad silicon dioxide layer; Need under the low pressure condition, feed process gas during deposit, and just begin to grow after adding radio frequency (RF) source and producing high-density plasma; Wherein the flow of process gas is that (Mass Flow Controller MFC) controls, and process gas comprises silicon source such as silane, oxygen source such as oxygen and inert gas such as argon gas with mass flowmenter; Radio frequency can comprise source, top radio frequency, side source radio frequency and bias voltage radio frequency; Push up wherein that source radio frequency, side source radio frequency can provide a uniform electric magnetic field so that the high-density plasma that produces evenly distributes, the material that the bias voltage radio frequency can make high-density plasma is realized sputter to the surface transport of silicon chip and can be in deposit the time.Under 2 millitorrs～10 millitorr low pressure conditions, the ion concentration of the high-density plasma that is produced can reach 10
11CM
-3～10
12CM
-3Wherein said high-density plasma can make cavity (Chamber) and silicon chip (wafer) heat up, and it is all lower that the initial temperature of the cavity of HDP-CVD is set, and generally is set at 100 ℃～200 ℃; After the heating of said high-density plasma, the temperature of silicon chip can reach more than 600 ℃ during deposit, as 640 ℃～720 ℃.
Though existing HDP-CVD technology can realize the ability in the gap that good filling shallow trench isolation leaves; But the cavity of HDP-CVD intensification control, MFC open in its depositing step, the unlatching of radio frequency all needs certain response time; As wherein the temperature of the cavity of HDP-CVD will rise to 640 ℃～720 ℃ from 100 ℃～200 ℃; This can cause at the deposit initial stage promptly more weak at pad silicon dioxide layer and the adhesion between the said silicon chip that temperature formed in the lower response time; The pad silicon dioxide layer thickness that the deposit initial stage forms in the prior art is about
shown in Figure 1A and Figure 1B; On the edge of said silicon chip 1, all have lateral side regions 11, and all different length like lateral side regions 11 of the shape of the lateral side regions 11 of the silicon chip 1 of different vendor's production is all different with sharp-pointed degree.The character that is formed on the said pad silicon dioxide layer on the lateral side regions 11 of said silicon chip 1 can change; The adhesion that said pad silicon dioxide layer and silicon chip are 1 more a little less than; So being easy to generate, said pad silicon dioxide layer on the lateral side regions 11 that is formed on said silicon chip 1 peels off (Peeling), thus particle meeting that these oxide layers of peeling off form and then in the subsequent technique process, be brought to the said silicon chip 1 surperficial yield that influences product.
Shown in Fig. 1 C; For direction shown in the arrow from Figure 1B is observed the microphotograph that the employing prior art is formed at the said pad silicon dioxide layer on the said lateral side regions 11; Can find out that said pad silicon dioxide layer has produced peels off, and has formed numerous particles that peels off 2.
Shown in Fig. 1 D,, can find out that graphics field and the non-graphics field on silicon chip 1 all formed particle 3 for the electron micrograph on the surface of the silicon chip 1 that is formed with said pad silicon dioxide layer in the prior art.Said particle 3 is to be formed by the particle that peels off 2 in said lateral side regions 11 shown in Fig. 1 C takes said silicon chip 1 in subsequent technique surf zone.Said particle 3 finally can have influence on the graphics field, and the yield of product is reduced.
Summary of the invention
Technical problem to be solved by this invention provides a kind of method of HDP-CVD technology deposit pad silicon dioxide layer; Can strengthen pad silicon dioxide layer and silicon chip adhesion, avoid peeling off of pad silicon dioxide layer and the problem of the particle that causes, can improve the yield of product.
For solving the problems of the technologies described above, the present invention provides a kind of method of HDP-CVD technology deposit pad silicon dioxide layer, comprises that one preheats step, saidly preheats the previous step that step is the depositing step of pad silicon dioxide layer; The said step that preheats forms high-density plasma and utilizes said high-density plasma that silicon chip is heated in cavity, make the initial temperature rising of the temperature of said silicon chip from cavity; The said step said silicon chip final temperature afterwards that preheats is confirmed by the said technological parameter that preheats step.
Further improve and be; The said technological parameter that preheats step is set according to the technological parameter of said depositing step; Compare with said depositing step, the said technological parameter that preheats step has been removed said depositing step needed silicon source and has been removed said depositing step and carried out the needed bias voltage radio frequency of sputter.
Further improve is that the said step silicon chip final temperature afterwards that preheats is more than or equal to 400 degree and smaller or equal to the silicon temperature in the said depositing step.
Further improving is that the said silicon temperature in the said depositing step is 640 ℃～720 ℃.
Further improve and be, confirm by said said silicon chip final temperature and the inclined-plane pattern of said silicon chip that preheats after the step the said heating time that preheats step.
Further improving is that be 15 seconds to 90 seconds the said heating time that preheats step.
The inventive method through the said heating that preheats step after; The temperature of said silicon chip can be 100 ℃～200 ℃ from the initial temperature of said cavity and rise to more than 400 ℃; Can avoid before said depositing step begins owing to lower silicon temperature forms the relatively poor pad silicon dioxide layer of adhesion; Thereby can strengthen pad silicon dioxide layer and silicon chip adhesion, avoid peeling off of pad silicon dioxide layer and the problem of the particle that causes, finally can improve the yield of product.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Figure 1A is the sketch map of silicon chip in the prior art;
Figure 1B is the sketch map of the chamfered region of silicon chip in the prior art;
Fig. 1 C is that direction shown in the arrow from Figure 1B is observed the microphotograph that the employing prior art is formed at the cushion oxide layer on the lateral side regions;
Fig. 1 D is the electron micrograph on surface that is formed with the silicon chip of cushion oxide layer in the prior art;
Fig. 2 is the flow chart of embodiment of the invention method;
Fig. 3 is the comparison diagram of the granule number of the embodiment of the invention and prior art generation.
Embodiment
The flow chart of embodiment of the invention method as shown in Figure 2.The method of embodiment of the invention HDP-CVD technology deposit pad silicon dioxide layer comprises that one preheats step, saidly preheats the previous step that step is the depositing step of pad silicon dioxide layer; The said step that preheats forms high-density plasma and utilizes said high-density plasma that silicon chip is heated in cavity, make the initial temperature rising of the temperature of said silicon chip from cavity.The said technological parameter that preheats step is set according to the technological parameter of said depositing step; Compare with said depositing step, the said technological parameter that preheats step has been removed said depositing step needed silicon source and has been removed said depositing step and carried out the needed bias voltage radio frequency of sputter.The said step said silicon chip final temperature afterwards that preheats is confirmed that by the said technological parameter that preheats step the said step silicon chip final temperature afterwards that preheats is more than or equal to 400 degree and smaller or equal to the silicon temperature in the said depositing step.According to the difference of the technological parameter of said depositing step, the said silicon temperature in the said depositing step is 640 ℃～720 ℃.Confirm that by said said silicon chip final temperature and the inclined-plane pattern of said silicon chip that preheats after the step can be 15 seconds to 90 seconds the said heating time that preheats step the said heating time that preheats step.
In a preferred embodiment, the technological parameter of said depositing step comprises: the pressure of cavity is set to 5 millitorrs; The power setting that source, top radio-frequency power is set to 1300W, side source radio frequency is that 3100W and bias voltage radio frequency are 3200W; Process gas comprises: thereby the argon flow amount that the argon flow amount that flows into from the top of said cavity is the top of the said cavity of 110sccm to be flowed into is the flow in 110sccm, oxygen district is 126sccm; Silane is adopted in the silicon source, and the flow of silane is 120sccm.When adopting above-mentioned technological parameter to carry out deposit, after stablizing, the temperature of said cavity and said silicon chip is 680 ℃～700 ℃.Removed said depositing step needed silicon source and said depositing step carries out the needed bias voltage radio frequency of sputter corresponding to the said technological parameter that preheats step of the back of said depositing step; It is 60 seconds that setting preheats the step time; After adopting the above-mentioned said technological parameter that preheats step, the said said silicon chip final temperature that preheats step can arrive 400 ℃～420 ℃.
The technological parameter of depositing step described in the above-mentioned preferred embodiment can be adjusted according to the technology of the shallow trench of the STI of reality; After the adjustment of the technological parameter of said depositing step, the technological parameter of the said technological parameter that preheats step i.e. technological parameter except that heating time also will carry out corresponding adjustment.For then being the said heating time that preheats step that inclined-plane pattern by said said silicon chip final temperature that preheats step and said silicon chip is confirmed.After the said heating time that preheats step is elongated; The peeling off the particle that forms and to reduce that forms at said silicon chip surface owing to the silicon dioxide layer of the chamfered region of said silicon chip; As shown in Figure 3, be that above-mentioned particle that 0 second, 10 seconds, 30 seconds and 60 seconds form is that the mean value of HDP particle is followed successively by 177,3.4,0.7 and 0.3 heating time.By on can know, after prolonging heating time, can significantly reduce granule number, thereby improve the yield of product.
More than through specific embodiment the present invention has been carried out detailed explanation, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be regarded as protection scope of the present invention.
Claims (6)
1. the method for a HDP-CVD technology deposit pad silicon dioxide layer is characterized in that: comprise that one preheats step, saidly preheat the previous step that step is the depositing step of pad silicon dioxide layer; The said step that preheats forms high-density plasma and utilizes said high-density plasma that silicon chip is heated in cavity, make the initial temperature rising of the temperature of said silicon chip from cavity; The said step said silicon chip final temperature afterwards that preheats is confirmed by the said technological parameter that preheats step.
2. the method for HDP-CVD technology deposit pad silicon dioxide layer according to claim 1; It is characterized in that: the said technological parameter that preheats step is set according to the technological parameter of said depositing step; Compare with said depositing step, the said technological parameter that preheats step has been removed said depositing step needed silicon source and has been removed said depositing step and carried out the needed bias voltage radio frequency of sputter.
3. like the method for the said HDP-CVD technology of claim 2 deposit pad silicon dioxide layer, it is characterized in that: the said step silicon chip final temperature afterwards that preheats is more than or equal to 400 degree and smaller or equal to the silicon temperature in the said depositing step.
4. like the method for the said HDP-CVD technology of claim 3 deposit pad silicon dioxide layer, it is characterized in that: the said silicon temperature in the said depositing step is 640 ℃～720 ℃.
5. like the method for the said HDP-CVD technology of claim 3 deposit pad silicon dioxide layer, it is characterized in that: confirm by said said silicon chip final temperature and the inclined-plane pattern of said silicon chip that preheats after the step the said heating time that preheats step.
6. like the method for the said HDP-CVD technology of claim 5 deposit pad silicon dioxide layer, it is characterized in that: be 15 seconds to 90 seconds the said heating time that preheats step.
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| CN2011101704272A CN102842500A (en) | 2011-06-22 | 2011-06-22 | Method for depositing liner silicon dioxide layer by utilizing high density plasma chemical vapor deposition (HDP-CVD) process |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016029701A1 (en) * | 2014-08-29 | 2016-03-03 | 沈阳拓荆科技有限公司 | Device and method using front end module to pre-heat wafer |
| CN113969396A (en) * | 2020-07-22 | 2022-01-25 | 盛合晶微半导体(江阴)有限公司 | Preparation method of control wafer |
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| US20020187655A1 (en) * | 2001-05-11 | 2002-12-12 | Applied Materials, Inc. | HDP-CVD deposition process for filling high aspect ratio gaps |
| CN1861838A (en) * | 2005-05-09 | 2006-11-15 | 联华电子股份有限公司 | Chemical gaseous phase depositing process of avoiding reacting room particle pollution |
| US20100041245A1 (en) * | 2008-08-18 | 2010-02-18 | Macronix International Co., Ltd. | Hdp-cvd process, filling-in process utilizing hdp-cvd, and hdp-cvd system |
| US7727906B1 (en) * | 2006-07-26 | 2010-06-01 | Novellus Systems, Inc. | H2-based plasma treatment to eliminate within-batch and batch-to-batch etch drift |
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2011
- 2011-06-22 CN CN2011101704272A patent/CN102842500A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020187655A1 (en) * | 2001-05-11 | 2002-12-12 | Applied Materials, Inc. | HDP-CVD deposition process for filling high aspect ratio gaps |
| CN1861838A (en) * | 2005-05-09 | 2006-11-15 | 联华电子股份有限公司 | Chemical gaseous phase depositing process of avoiding reacting room particle pollution |
| US7727906B1 (en) * | 2006-07-26 | 2010-06-01 | Novellus Systems, Inc. | H2-based plasma treatment to eliminate within-batch and batch-to-batch etch drift |
| US20100041245A1 (en) * | 2008-08-18 | 2010-02-18 | Macronix International Co., Ltd. | Hdp-cvd process, filling-in process utilizing hdp-cvd, and hdp-cvd system |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016029701A1 (en) * | 2014-08-29 | 2016-03-03 | 沈阳拓荆科技有限公司 | Device and method using front end module to pre-heat wafer |
| CN113969396A (en) * | 2020-07-22 | 2022-01-25 | 盛合晶微半导体(江阴)有限公司 | Preparation method of control wafer |
| CN113969396B (en) * | 2020-07-22 | 2023-12-01 | 盛合晶微半导体(江阴)有限公司 | Preparation method of control wafer |
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Application publication date: 20121226 |