CN113964189B - Low-on-resistance super-junction VDMOS structure - Google Patents

Low-on-resistance super-junction VDMOS structure Download PDF

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CN113964189B
CN113964189B CN202111584948.2A CN202111584948A CN113964189B CN 113964189 B CN113964189 B CN 113964189B CN 202111584948 A CN202111584948 A CN 202111584948A CN 113964189 B CN113964189 B CN 113964189B
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super junction
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CN113964189A (en
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李吕强
陈辉
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Hangzhou Xinmai Semiconductor Technology Co ltd
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Hangzhou Xinmai Semiconductor Technology Co ltd
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Abstract

The invention provides a super junction VDMOS structure with low on-resistance, which comprises: the super junction structure is positioned on the first conduction type semiconductor drain region; the super junction structure includes a first conductivity type and a second conductivity type semiconductor pillar; replacing partial areas of the interface of two adjacent first-conductivity-type and second-conductivity-type semiconductor columns with a transverse HEMT structure formed by a heterojunction; the HEMT structure includes a first semiconductor material pillar and a second semiconductor material pillar. The HEMT structure is formed by arranging the heterojunction in the super junction area, the two-dimensional electron gas is introduced for conducting, the conduction resistance of the device is greatly reduced, the switching-off of the HEMT structure is controlled by the potential difference between the first conduction type semiconductor column and the second conduction type semiconductor column of the super junction structure, the two-dimensional electron gas can exist on the surface of the heterojunction under the condition of low leakage voltage between the source region and the drain region, and the conduction resistance of the device is effectively reduced; under the high leakage voltage between the source region and the drain region, the two-dimensional electron gas is exhausted, and the device can bear high voltage.

Description

Low-on-resistance super-junction VDMOS structure
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a super-junction VDMOS structure with low on-resistance.
Background
At present, the application field of the power semiconductor device is wider and wider, and the power semiconductor device can be widely applied to the fields of DC-DC converters, DC-AC converters, relays, motor drives and the like. Compared with a bipolar transistor, a vertical double-diffused metal oxide semiconductor field effect transistor (VDMOS) has the advantages of high switching speed, low loss, high input impedance, low driving power, good frequency characteristics, high transconductance linearity and the like, and thus becomes a novel power device which is most widely applied at present. The conventional VDMOS device also has its inherent disadvantage that the on-resistance leads to a sharp increase in power consumption with an increase in withstand voltage. The appearance of charge balance devices represented by a super-junction VDMOS improves the contradiction, reduces the restriction relation between on-resistance and voltage resistance, and can simultaneously realize low-state power consumption and high-cut-off voltage, so that the super-junction VDMOS can be rapidly applied to various high-energy-efficiency occasions, and the market prospect is very wide. The basic power super-junction VDMOS structure is characterized in that a P column and an N column which are mutually alternated are used for replacing an N drift region of a traditional power device, when the device is in a turn-off state, under reverse bias, due to the interaction of a transverse electric field (x direction) and a longitudinal electric field (y direction), the P column region and the N column region are completely depleted, and the longitudinal electric field distribution in the depletion region is nearly uniform, so that theoretically, the breakdown voltage only depends on the thickness of a voltage-resistant layer and is irrelevant to the doping concentration, the doping concentration of the voltage-resistant layer can be increased by nearly one order of magnitude, the on-resistance of the device is effectively reduced, and the on-power consumption is reduced.
However, the current super junction VDMOS is limited by materials, and the further reduction of the on-resistance of the device is limited by the migration rate of carriers in the semiconductor material and the trade-off relationship between the specific on-resistance and the withstand voltage of the device.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a low on-resistance super-junction VDMOS structure, which is used to solve the problems that the on-resistance of the super-junction VDMOS in the prior art cannot be further reduced due to material limitation, and the like.
To achieve the above and other related objects, the present invention provides a super junction VDMOS structure with low on-resistance, comprising:
the super junction structure comprises a first conduction type semiconductor drain region, a super junction structure, a second conduction type semiconductor body region, a first conduction type semiconductor source region and a grid structure, wherein the super junction structure is positioned on the first conduction type semiconductor drain region;
the super junction structure comprises first conductive type semiconductor columns and second conductive type semiconductor columns, the first conductive type semiconductor columns and the second conductive type semiconductor columns are transversely and alternately arranged, the second conductive type semiconductor columns are located below second conductive type semiconductor body regions, and the first conductive type semiconductor columns are located below the gate structures; the junction part of two adjacent first conduction type semiconductor columns and second conduction type semiconductor columns in the super junction structure is replaced by a transverse HEMT structure formed by a heterojunction;
the HEMT structure comprises a first semiconductor material column and a second semiconductor material column, wherein the first semiconductor material column is arranged at the interface of the first conduction type semiconductor column, the second semiconductor material column is arranged at the interface of the second conduction type semiconductor column, the HEMT structure is positioned on the surface of the first conduction type semiconductor drain region and is not in contact with the second conduction type semiconductor body region, two-dimensional electron gas is formed on the contact surface of the second conduction type semiconductor column and the second conduction type semiconductor column, and two-dimensional electron gas is formed on the contact surface of the first semiconductor material column and the second semiconductor material column.
Optionally, the materials of the first conductivity type semiconductor drain region, the super junction structure, the second conductivity type semiconductor body region and the first conductivity type semiconductor source region are SiC; in the HEMT structure, the first semiconductor material column is made of GaN, and the second semiconductor material column is made of AlGaN.
Further, the material of the first conductivity type semiconductor drain region, the super junction structure, the second conductivity type semiconductor body region and the first conductivity type semiconductor source region is 4H-SiC.
Optionally, the material of the first conductivity type semiconductor drain region, the super junction structure, the second conductivity type semiconductor body region and the first conductivity type semiconductor source region is Si; in the HEMT structure, the first semiconductor material column is made of GaAs, and the second semiconductor material column is made of AlGaAs.
Optionally, the first conductivity type is an N type, and the second conductivity type is a P type; or the first conduction type is P type, and the second conduction type is N type.
Optionally, the gate structure is a planar gate structure or a trench gate structure.
Optionally, the first conductivity type semiconductor drain region is in ohmic contact with a metal drain.
Further, the second conductivity type semiconductor body region is provided with a second conductivity type semiconductor ohmic contact layer.
Further, the second conductive type semiconductor ohmic contact layer and the first conductive type semiconductor source region are in ohmic contact with a metal source electrode.
As described above, in the low on-resistance super-junction VDMOS structure of the present invention, the HEMT structure is formed by disposing the heterojunction in the super-junction region, and the conduction is performed by introducing the two-dimensional electron gas, so that the on-resistance of the device is greatly reduced. The switching-off of the HEMT structure is controlled through the potential difference between the first conduction type semiconductor column and the second conduction type semiconductor column of the super junction structure, so that two-dimensional electron gas can exist on the surface of a heterojunction under the low leakage voltage between a source region and a drain region, and the on-resistance of a device is effectively reduced; under the high leakage voltage between the source region and the drain region, the two-dimensional electron gas is exhausted, and the device can bear high voltage. Therefore, the effect of effectively reducing the on-resistance can be achieved on the premise of ensuring the high voltage resistance of the VDMOS structure.
Drawings
Fig. 1 is a schematic cross-sectional view of a low on-resistance super junction VDMOS structure according to an example of the present invention, wherein the gate structure is a planar gate structure.
Fig. 2 is a schematic cross-sectional view of a low on-resistance super junction VDMOS structure according to another embodiment of the invention, wherein the gate structure is a trench gate structure.
Fig. 3 shows a schematic energy band diagram of materials in a low on-resistance super junction VDMOS structure according to an example of the present invention, wherein the schematic energy band diagram is a schematic energy band diagram of the materials before they are not in contact with each other.
Fig. 4 shows a schematic energy band diagram of materials in a low on-resistance super junction VDMOS structure according to an example of the present invention, where the schematic energy band diagram is an energy band diagram of the materials after contacting each other and when Vds = 0V.
Description of the element reference numerals
10 a first conductivity type semiconductor drain region, 11 a super junction structure, 111 a first conductivity type semiconductor column, 112 a second conductivity type semiconductor column, 12 a first semiconductor material column, 13 a second semiconductor material column, 14 a two-dimensional electron gas, 15 a second conductivity type semiconductor body region, 16 a first conductivity type semiconductor source region, 17 a gate structure, 18 a metal drain, 19 a second conductivity type semiconductor ohmic contact layer, 20 a metal source.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 4. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed according to actual needs, and the layout of the components may be more complicated.
As shown in fig. 1 and fig. 2, the present embodiment provides a super junction VDMOS structure with low on-resistance, including:
a first conductivity type semiconductor drain region 10, a super junction structure 11 located on the first conductivity type semiconductor drain region 10, a second conductivity type semiconductor body region 15 located on the super junction structure 11, a first conductivity type semiconductor source region 16, and a gate structure 17;
the super junction structure 11 includes first conductivity type semiconductor pillars 111 and second conductivity type semiconductor pillars 112, the first conductivity type semiconductor pillars 111 and the second conductivity type semiconductor pillars 112 are laterally arranged alternately, and the second conductivity type semiconductor pillars 112 are located below the second conductivity type semiconductor body region 15, the first conductivity type semiconductor pillars 111 are located below the gate structure 17; wherein, the interface partial area of two adjacent first conduction type semiconductor columns 111 and second conduction type semiconductor columns 112 in the super junction structure 11 is replaced by a lateral HEMT structure formed by heterojunction;
the HEMT structure includes a first semiconductor material column 12 and a second semiconductor material column 13, the first semiconductor material column 12 is disposed at an interface of the first conductive type semiconductor column 111, the second semiconductor material column 13 is disposed at an interface of the second conductive type semiconductor column 112, and the HEMT structure is located on the surface of the first conductive type semiconductor drain region 10 and does not contact with the second conductive type semiconductor body region 15, wherein a two-dimensional electron gas is formed on a contact surface of the second conductive type semiconductor column 112 and a contact surface of the first semiconductor material column 12 and the second semiconductor material column 13.
According to the super-junction VDMOS structure, the HEMT structure is formed by arranging the heterojunction in the super-junction area, and two-dimensional electron gas is introduced to conduct electricity, so that the on-resistance of a device is greatly reduced. The switching-off of the HEMT structure is controlled through the potential difference between the first conduction type semiconductor column and the second conduction type semiconductor column of the super junction structure, so that two-dimensional electron gas can exist on the surface of a heterojunction under the low leakage voltage between a source region and a drain region, and the on-resistance of a device is effectively reduced; under the high leakage voltage between the source region and the drain region, the two-dimensional electron gas is exhausted, and the device can bear high voltage. Therefore, the effect of effectively reducing the on-resistance can be achieved on the premise of ensuring the high voltage resistance of the VDMOS structure.
As a specific example, the body material of the super-junction VDMOS structure is SiC, and the material of the HEMT structure is GaN/AlGaN, that is, the materials of the first conductivity type semiconductor drain region 10, the super-junction structure 11, the second conductivity type semiconductor body region 15, and the first conductivity type semiconductor source region 16 are SiC, and here, 4H — SiC is preferable; in the HEMT structure, the first semiconductor material column 12 is made of GaN, the second semiconductor material column 13 is made of AlGaN, the first conductivity type is N-type, and the second conductivity type is P-type, so as to further explain the beneficial effects of the low on-resistance super-junction VDMOS structure. The 4H-SiC is a semiconductor material with a wide forbidden band, the forbidden band width of the semiconductor material is 3.26eV, the forbidden band width of the GaN is 3.4eV, and the forbidden band width of the AlGaN can be controlled between 3.4eV and 6.0eV by adjusting the concentration of Al. The GaN/AlGaN has different forbidden band widths and can form a heterojunction, electrons in the AlGaN flow to the GaN, so that a positive space charge area is formed in the AlGaN area, and a two-dimensional electron gas is formed on the surface of the GaN. As shown in fig. 3, it is a schematic diagram of energy bands of materials in the super junction structure and the HEMT structure before contact; when these materials come into contact, the energy band is bent, and as shown in fig. 4, the contact surface of the second semiconductor material column 13 with the second conductivity type semiconductor column 112 and the contact surface of the first semiconductor material column 12 with the second semiconductor material column 13, i.e., the P-SiC/AlGaN and AlGaN/GaN surfaces, form a two-dimensional electron gas 14. The super junction structure 11 makes the second conductivity type semiconductor column 112 equipotential with the first conductivity type semiconductor source region 16, and the first conductivity type semiconductor column 111 equipotential with the first conductivity type semiconductor drain region 10, so that the two-dimensional electron gas 14 exists in the device when the voltage difference Vds between the source region and the drain region = 0; when the VDMOS structure works, Vds is always more than 0 no matter the device is turned on or off, the potential difference can lower the potential of the second conductive type semiconductor column 112, namely the P-SiC side, and the potential of the first conductive type semiconductor column 111, namely the N-SiC side can rise, which is represented as the P-SiC side potential energy rise and the N-SiC side potential energy fall in the energy band diagram of FIG. 4, so that the two-dimensional electron gas can always receive the weakening effect of the depletion of the second conductive type semiconductor column 112/the first conductive type semiconductor column 111, the width and the concentration of AlGaN/GaN can be adjusted and controlled, the HEMT structure can be turned off by the P/N column potential difference of the super junction structure, for example, Vgs is more than 0 and Vds is more than 0 when the VDMOS structure is turned on, the depletion effect of the P/N column is not strong because Vds is smaller forward conducting voltage, and the two-dimensional electron gas still exists, the on-resistance will be greatly reduced; when the VDMOS structure is turned off, Vgs =0, Vds >0, and Vds is gradually increased, P-SiC and N-SiC above AlGaN/GaN are depleted first to bear partial withstand voltage, then Vds is increased continuously to enable a depletion region to be gradually widened and continuously deplete two-dimensional electron gas, and the two-dimensional electron gas is completely depleted under high leakage voltage, so that the device can bear high voltage, and the blocking voltage capability of the device can be further improved due to the fact that the GaN forbidden band width is wider. Therefore, the on-resistance can be effectively reduced under the condition of ensuring the high voltage endurance of the VDMOS structure, and the voltage endurance can be even further improved.
The above example is described by taking the first conductivity type as an N-type and the second conductivity type as a P-type. In practice, the first conductivity type may also be P-type, and the second conductivity type may also be N-type.
As an example, the host material of the super junction VDMOS structure may also be Si, and the material of the HEMT structure is GaAs/AlGaAs, that is, the materials of the first conductivity type semiconductor drain region 10, the super junction structure 11, the second conductivity type semiconductor body region 15, and the first conductivity type semiconductor source region 16 are Si; in the HEMT structure, the first semiconductor material pillar 12 is made of GaAs, and the second semiconductor material pillar 13 is made of AlGaAs.
As shown in fig. 1, as an example, the gate structure 17 in the super junction VDMOS structure may be an existing planar gate structure; as shown in fig. 2, the structure may be a conventional trench gate structure, which is not limited herein.
As shown in fig. 1 and 2, a metal drain 18 is disposed below the first conductive type semiconductor drain 10 to realize ohmic contact therebetween, and an electrode is drawn through the metal drain 18.
As shown in fig. 1 and 2, the second conductivity type semiconductor body 15 is provided with a second conductivity type semiconductor ohmic contact layer 19. Preferably, a metal source 20 in ohmic contact is formed on the second conductive type semiconductor ohmic contact layer 19 and the first conductive type semiconductor source region 16, so that electrode extraction is realized through the metal source 20.
As an example, the first conductivity-type semiconductor pillar 111 and the second conductivity-type semiconductor pillar 112 of the superjunction structure 11 may be complementary inclined pillars, that is, the first conductivity-type semiconductor pillar 111 and the second conductivity-type semiconductor pillar 112 are inclined in opposite directions to each other. However, the first conductivity-type semiconductor pillar 111 and the second conductivity-type semiconductor pillar 112 may also be epitaxial pillars without tilt, and the electric field in the middle region of the super junction structure 11 may be larger than that in the two end regions by setting the epitaxial pillars to a graded doping profile gradient from top to bottom.
In summary, the invention provides a super-junction VDMOS structure with low on-resistance, in which a heterojunction is disposed in a super-junction region to form a HEMT structure, and two-dimensional electron gas is introduced to conduct electricity, so as to greatly reduce the on-resistance of the device. The switching-off of the HEMT structure is controlled through the potential difference between the first conduction type semiconductor column and the second conduction type semiconductor column of the super junction structure, so that two-dimensional electron gas can exist on the surface of a heterojunction under the low leakage voltage between a source region and a drain region, and the on-resistance of a device is effectively reduced; under the high leakage voltage between the source region and the drain region, the two-dimensional electron gas is exhausted, and the device can bear high voltage. Therefore, the effect of effectively reducing the on-resistance can be achieved on the premise of ensuring the high voltage resistance of the VDMOS structure. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (9)

1. A low on-resistance super-junction VDMOS structure, comprising:
the super junction structure comprises a first conduction type semiconductor drain region, a super junction structure, a second conduction type semiconductor body region, a first conduction type semiconductor source region and a grid structure, wherein the super junction structure is positioned on the first conduction type semiconductor drain region;
the super junction structure comprises first conductive type semiconductor columns and second conductive type semiconductor columns, the first conductive type semiconductor columns and the second conductive type semiconductor columns are transversely and alternately arranged, the second conductive type semiconductor columns are located below second conductive type semiconductor body regions, and the first conductive type semiconductor columns are located below the gate structures; the junction part of two adjacent first conduction type semiconductor columns and second conduction type semiconductor columns in the super junction structure is replaced by a transverse HEMT structure formed by a heterojunction;
the HEMT structure comprises a first semiconductor material column and a second semiconductor material column, wherein the first semiconductor material column is arranged at the interface of the first conduction type semiconductor column, the second semiconductor material column is arranged at the interface of the second conduction type semiconductor column, the HEMT structure is positioned on the surface of the first conduction type semiconductor drain region and is not in contact with the second conduction type semiconductor body region, two-dimensional electron gas is formed on the contact surface of the second conduction type semiconductor column and the second conduction type semiconductor column, and two-dimensional electron gas is formed on the contact surface of the first semiconductor material column and the second semiconductor material column.
2. The low on-resistance superjunction VDMOS structure of claim 1, wherein: the first conduction type semiconductor drain region, the super junction structure, the second conduction type semiconductor body region and the first conduction type semiconductor source region are made of SiC; in the HEMT structure, the first semiconductor material column is made of GaN, and the second semiconductor material column is made of AlGaN.
3. The low on-resistance superjunction VDMOS structure of claim 2, wherein: the materials of the first conduction type semiconductor drain region, the super junction structure, the second conduction type semiconductor body region and the first conduction type semiconductor source region are 4H-SiC.
4. The low on-resistance superjunction VDMOS structure of claim 1, wherein: the first conduction type semiconductor drain region, the super junction structure, the second conduction type semiconductor body region and the first conduction type semiconductor source region are made of Si; in the HEMT structure, the first semiconductor material column is made of GaAs, and the second semiconductor material column is made of AlGaAs.
5. The low on-resistance superjunction VDMOS structure of claim 1, wherein: the first conductive type is an N type, and the second conductive type is a P type; or the first conduction type is P type, and the second conduction type is N type.
6. The low on-resistance superjunction VDMOS structure of claim 1, wherein: the gate structure is a planar gate structure or a trench gate structure.
7. The low on-resistance superjunction VDMOS structure of claim 1, wherein: the first conduction type semiconductor drain region is in ohmic contact with the metal drain electrode.
8. The low on-resistance superjunction VDMOS structure of claim 7, wherein: the second conductive type semiconductor body region is provided with a second conductive type semiconductor ohmic contact layer.
9. The low on-resistance superjunction VDMOS structure of claim 8, wherein: the second conductive type semiconductor ohmic contact layer and the first conductive type semiconductor source region are in ohmic contact with the metal source electrode.
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