CN217788401U

CN217788401U - 4H-SiC-based super-junction power field effect transistor device

Info

Publication number: CN217788401U
Application number: CN202221997977.1U
Authority: CN
Inventors: 谢速
Original assignee: Jiefang Semiconductor Shanghai Co ltd
Current assignee: Jiefang Semiconductor Shanghai Co ltd
Priority date: 2022-07-29
Filing date: 2022-07-29
Publication date: 2022-11-11
Anticipated expiration: 2032-07-29

Abstract

The utility model discloses a 4H-SiC-based super junction power field effect transistor device, which comprises a drain electrode, a source electrode and a gate electrode; the drain electrode is attached to the lower surface of the substrate area, a buffer area is arranged on the upper surface of one side of the substrate area, the height of the buffer area is larger than that of the substrate area, a first drift area is arranged on the buffer area, a second drift area is arranged on the upper surface of the other side of the substrate area, the thickness of the second drift area is larger than that of the first drift area, the source area and the source electrode are embedded into the source area side by side, the lower surface of the source area is in contact with the upper surface of the second drift area, the inner side of the lower surface of the source area extends to be in contact with the first drift area, the gate electrode, the gate area and the insulating layer are sequentially stacked above the first drift area from top to bottom, and the lower surface of the insulating layer is in contact with the upper surfaces of the first drift area, the source area and part of the source area. Effectively shortens the current path, reduces the specific on-resistance of the device, and improves the UIS avalanche tolerance capability of the MOSFET device.

Description

4H-SiC-based super-junction power field effect transistor device

Technical Field

The utility model relates to semiconductor power device technical field, concretely relates to 4H-SiC base surpasses knot power field effect transistor device.

Background

Super junction power MOSFETs, i.e., metal-oxide-semiconductor field effect transistors, are proposed to improve the contradiction between breakdown voltage and specific on-resistance in conventional power MOSFETs, and are widely used in medium-low power supply devices. However, the existing super junction power MOSFET device has the defects of long turn-off time and large switching power consumption. Therefore, how to further improve the current conducting capability of the device, reduce the switching power consumption of the device, and shorten the turn-off time becomes a new research direction.

Disclosure of Invention

The not enough to prior art, the utility model aims at providing a 4H-SiC base surpasses knot power field effect transistor device to improve the device and switch on current's ability, reduce the switching power consumption of device, shorten the turn-off time.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

the 4H-SiC-based super junction power field effect transistor device is characterized in that: the cell structure comprises a drain electrode, a source electrode, a gate electrode, a substrate region, a source body region, a gate region and an insulating layer; the drain electrode is attached to the lower surface of the substrate area, a buffer area is arranged on the upper surface of one side of the substrate area, the height of the buffer area is larger than that of the substrate area, a first drift area is arranged on the buffer area, a second drift area is arranged on the upper surface of the other side of the substrate area, the second drift area is partially located above the buffer area, the inner surface of the second drift area is in contact with the inner surface of the first drift area, the thickness of the second drift area is larger than that of the first drift area, the source area and the source electrode are embedded into the source area side by side, the upper surfaces of the source area and the source electrode are flush with the upper surface of the source area, the source area is located on the inner side of the source electrode, the lower surface of the source area is in contact with the upper surface of the second drift area, the inner side of the source area extends to be in contact with the first drift area, the gate electrode, the gate area and the insulating layer are sequentially stacked above the first drift area from top to bottom, and the lower surface of the insulating layer is in contact with the upper surfaces of the first drift area, the source area and the partial source area.

Furthermore, the doping types of the source region, the first drift region, the substrate region, the buffer region and the gate region are different from the doping types of the source body region and the second drift region, and when the doping types of the source region, the first drift region, the buffer region, the substrate region and the gate region are N-type, the doping types of the source body region and the second drift region are P-type; and when the doping types of the source region, the first drift region, the buffer region, the substrate region and the gate region are P-type, the doping types of the source body region and the second drift region are N-type.

Furthermore, the doping concentration of the buffer region is lower than that of the substrate region, and the doping concentration of the buffer region is higher than that of the first drift region.

Further, the area of the substrate region in contact with the second drift region is smaller than the area of the substrate region in contact with the buffer region.

Further, the source region, the first drift region, the substrate region, the source body region, the second drift region and the gate region are all made of semiconductor materials, and the drain electrode, the source electrode and the gate electrode are all made of metal materials.

Further, the semiconductor material is silicon, gallium arsenide, gallium nitride or silicon carbide.

The utility model discloses a show the effect and be: the source body region is sunk, and the source electrode is embedded in the sinking position, so that the current path is effectively shortened, the specific on-resistance of the device is reduced, the current conducting capacity of the device is improved, the cell size of the device is reduced, the area of the device is reduced, and the UIS avalanche tolerance capacity of the MOSFET device is improved; in addition, the softness of the reverse recovery current of the parasitic body diode is effectively improved through the arrangement of the buffer area, the reverse recovery characteristic is improved, the device is not easy to oscillate in the switching process, electromagnetic interference signals are restrained, and the device works more safely and reliably.

Drawings

Fig. 1 is a schematic structural diagram of the present invention.

Detailed Description

The following provides a more detailed description of the embodiments and the operation of the present invention with reference to the accompanying drawings.

As shown in fig. 1, a 4H-SiC based super junction power field effect transistor device is formed by mutually splicing a plurality of repeating cell structures, wherein each cell structure comprises a drain electrode 01, a source electrode 02, a gate electrode 03, a substrate region 12, a source region 10, a source body region 20, a gate region 30 and an insulating layer 40; the drain electrode 01 is attached to the lower surface of the substrate region 12, a buffer region 14 is arranged on the upper surface of one side of the substrate region 12, the height of the buffer region 14 is greater than that of the substrate region 12, a first drift region 11 is arranged on the buffer region 14, a second drift region 21 is arranged on the upper surface of the other side of the substrate region 12, the second drift region 21 is partially located above the buffer region 14, the inner surface of the second drift region 21 is in contact with the inner surface of the first drift region 11, the thickness of the second drift region 21 is greater than that of the first drift region 11, the source region 10 and the source electrode 02 are embedded in the source region 20 side by side, the upper surfaces of the source region 10 and the source electrode 02 are flush with the upper surface of the source region 20, the source region 10 is located inside the source electrode 02, the lower surface of the source region 20 is in contact with the upper surface of the second drift region 21, the inner side of the lower surface of the source region 20 extends to be in contact with the first drift region 11, the gate electrode 03, the gate region 30 and the insulating layer 40 are sequentially stacked above the first drift region 11, and the upper surface of the drift region 11 and the source region 10 and the lower surface of the drift region 11.

The cellular structure diagram of the 4H-SiC-based super junction power field effect transistor device is a voltage-withstanding layer consisting of a first drift region 11 of a first conductivity type and a second drift region 21 of a second conductivity type, wherein the first drift region 11 is flush with the lower surface of the second drift region 21, and the voltage-withstanding layer is provided with two surfaces; at least one source body region 20 of the second conductivity type is arranged in the upper surface, at least one heavily doped source region 10 of the first conductivity type is arranged in the source body region 20, and part of the source region 10 and part of the source body region 20 are connected through a conductor to form a source electrode 02 of the device; covering the surfaces of part of the source region 10, part of the source region 20 and part of the voltage-proof layer with an insulating layer 40, covering the insulating layer 40 with a heavily doped semiconductor polysilicon gate region 30 of a first conduction type as a gate electrode of the device, covering part of the surface of the gate region 30 with a conductor, and forming a gate electrode 03 of the device; a heavily doped semiconductor substrate region 12 of the first conductivity type is provided in the lower surface, and the surface of the substrate region 12 is covered with a conductor which serves as a drain electrode 01.

When the first conduction type is N type, the second conduction type is P type; when the first conductive type is P type, the second conductive type is N type.

In this example, the doping types of the source region 10, the first drift region 11, the substrate region 12, the buffer region 14 and the gate region 30 are different from the doping types of the source body region 20 and the second drift region 21, and when the doping types of the source region 10, the first drift region 11, the buffer region 14, the substrate region 12 and the gate region 30 are N-type, the doping types of the source body region 20 and the second drift region 21 are P-type; when the doping types of the source region 10, the first drift region 11, the buffer region 14, the substrate region 12 and the gate region 30 are P-type, the doping types of the source body region 20 and the second drift region 21 are N-type.

Preferably, the doping type of the buffer region 14 is the same as the substrate region 12, and the doping concentration thereof is lower than that of the substrate region 12, and the doping concentration of the buffer region 14 is higher than that of the first drift region 11.

Further, the area of the substrate region 12 in contact with the second drift region 21 is smaller than the area in contact with the buffer region 14.

Preferably, the source region 10, the first drift region 11, the substrate region 12, the buffer region 14, the source body region 20, the second drift region 21 and the gate region 30 are all made of a semiconductor material, and the drain electrode 01, the source electrode 02 and the gate electrode 03 are all made of a metal material. The semiconductor material is silicon, gallium arsenide, gallium nitride or silicon carbide.

In contrast to the conventional superjunction MOSFET structure, the second drift region 21 extends into the substrate region 12 in this embodiment. The extension portion accumulates a certain amount of non-equilibrium carriers when the body diode is turned on. In the reverse recovery process of the body diode, when the concentration of carriers at the part of the super-junction structure is suddenly reduced, the accumulated carriers are supplemented in time, so that the smooth attenuation of reverse recovery current is ensured, and the soft recovery is realized. The forward blocking characteristic of the transistor is closely related to the extension in the second drift region 21, the essential requirement being that in the second drift region 21 the width of the part surrounded by the substrate region 12 is smaller than the width of the part surrounded by the first drift region 11.

The most important point of this embodiment is that, on the premise of ensuring the softness of the parasitic body diode reverse recovery current and not increasing the specific on-resistance of the device, the source body region 20 is sunk and the source electrode 02 is embedded at the sinking position, so that the current path is effectively shortened, the cell size of the device is reduced, the area of the device is reduced, and the UIS avalanche tolerance capability of the MOSFET device is improved. In addition, the arrangement of the buffer area 14 effectively improves the softness of the reverse recovery current of the parasitic body diode and improves the reverse recovery characteristic, so that the device is not easy to generate oscillation in the switching process, electromagnetic interference signals are inhibited, and the device works more safely and reliably.

The technical scheme provided by the utility model is introduced in detail above. The principles and embodiments of the present invention have been explained herein using specific examples, and the above descriptions of the embodiments are only used to help understand the method and its core ideas of the present invention. It should be noted that, for those skilled in the art, without departing from the principle of the present invention, the present invention can be further modified and modified, and such modifications and modifications also fall within the protection scope of the appended claims.

Claims

1. A4H-SiC-based super junction power field effect transistor device is formed by mutually splicing a plurality of repeated cellular structures, wherein each cellular structure comprises a drain electrode, a source electrode and a gate electrode, and is characterized in that: the semiconductor device further comprises a substrate region, a source body region, a gate region and an insulating layer; the drain electrode is attached to the lower surface of the substrate area, a buffer area is arranged on the upper surface of one side of the substrate area, the height of the buffer area is larger than that of the substrate area, a first drift area is arranged on the buffer area, a second drift area is arranged on the upper surface of the other side of the substrate area, the second drift area is partially located above the buffer area, the inner surface of the second drift area is in contact with the inner surface of the first drift area, the thickness of the second drift area is larger than that of the first drift area, the source area and the source electrode are embedded into the source area side by side, the upper surfaces of the source area and the source electrode are flush with the upper surface of the source area, the source area is located on the inner side of the source electrode, the lower surface of the source area is in contact with the upper surface of the second drift area and the inner side of the source area extends to be in contact with the first drift area, the gate electrode, the gate area and the insulating layer are sequentially stacked and arranged above the first drift area from top to bottom, and the lower surface of the insulating layer is in contact with the upper surface of the first drift area, the source area and the source area.

2. The 4H-SiC-based superjunction power field effect transistor device of claim 1, wherein: the source region, the first drift region, the substrate region, the buffer region and the gate region are different from the source body region and the second drift region in doping type, and when the source region, the first drift region, the buffer region, the substrate region and the gate region are N-type, the source body region and the second drift region are P-type; and when the doping types of the source region, the first drift region, the buffer region, the substrate region and the gate region are P-type, the doping types of the source body region and the second drift region are N-type.

3. The 4H-SiC-based superjunction power field effect transistor device of claim 2, wherein: the doping concentration of the buffer region is lower than that of the substrate region, and the doping concentration of the buffer region is higher than that of the first drift region.

4. The 4H-SiC-based superjunction power field effect transistor device of claim 1, wherein: the area of the substrate region in contact with the second drift region is smaller than the area of the substrate region in contact with the buffer region.

5. The 4H-SiC-based superjunction power field effect transistor device of claim 1, wherein: the source region, the first drift region, the substrate region, the source body region, the second drift region and the gate region are all made of semiconductor materials, and the drain electrode, the source electrode and the gate electrode are all made of metal materials.

6. The 4H-SiC-based superjunction power field effect transistor device of claim 5, wherein: the semiconductor material is silicon, gallium arsenide, gallium nitride or silicon carbide.