CN113963669A - Power consumption-saving high-refresh panel driving circuit and design method - Google Patents

Abstract

The invention discloses a power consumption-saving high-refresh panel driving circuit and a design method thereof, wherein the power consumption-saving high-refresh panel driving circuit comprises a GIP input signal and a GIP output level transmission signal, a VGH high level and a VGL low level on the upper part of the driving circuit are respectively connected with a T1 device and a T7 device, a T1 device and a T7 device are respectively connected with Gn-4 and Gn +4, the T1 device and the T7 device on the upper part are connected with a Q point voltage bit, the Q point voltage bit is connected with a T4 device and a C2 capacitor, a C1 capacitor is connected between the T2 device and the T3 device, a CK clock signal is connected on a C1 capacitor, the T6 is connected with a C3 capacitor, an A point voltage bit is connected between the C2 capacitor and a C3 capacitor, the A point voltage bit is respectively connected with a T8 device and a T9 device, the T8 device is respectively connected with Gn-4 and Gn +3, and Gn +4 are respectively connected on the T9 device. Through the 2-level coupling scheme to Q point voltage bit, under the unchangeable condition of Q point voltage bit voltage, can reduce and drive the high level voltage of VGH, reduce and drive VGH voltage, can effectively reduce panel consumption.

Description

Power consumption-saving high-refresh panel driving circuit and design method

Technical Field

The invention belongs to the technical field of display devices, and particularly relates to a power-consumption-saving high-refresh panel driving circuit and a design method.

Background

For example, chinese patent application No. CN202110274341.8 discloses a front-end processing circuit coupled to and before a panel driving circuit. The front-end processing circuit comprises a sub-pixel rendering module and a compensation module. The sub-pixel rendering module is used for receiving the first signal, performing sub-pixel rendering processing on the first signal and outputting a second signal. The compensation module is respectively coupled with the sub-pixel rendering module and the panel driving circuit and is used for outputting a third signal to the panel driving circuit after the second signal is compensated.

However, the above scheme has the following disadvantages:

1. the circuit only solves the problem that the memory built in the panel driving circuit is not used, so the capacity of the memory needs to be additionally increased, but the display of the liquid crystal display panel is completed by controlling the in-plane pixel TFT, specifically, the on and off of the TFT is controlled by a transverse grid signal and the data to be displayed is written by a longitudinal source signal, wherein the grid signal is generated by the grid driving circuits on two sides of the panel, which is called as a GIP driving circuit for short; with the demand of people for display quality becoming higher and higher, the current TFT-LCD panel mainly develops towards high refresh and high resolution, so the power consumption of the panel also gradually increases, and for mobile devices, the power consumption is one of the most important parameters; with the increase of the refresh rate, a GIP circuit is lacked, which can save power consumption compared with the conventional GIP circuit.

Therefore, we propose a power consumption-saving high refresh panel driving circuit and design method to solve the above mentioned problems in the background art.

Disclosure of Invention

The present invention provides a power-saving high refresh panel driving circuit and a design method thereof, so as to solve the problems in the prior art.

In order to achieve the purpose, the invention provides the following technical scheme: a power-saving high-refresh panel driving circuit comprises a GIP input signal and a GIP output stage transmission signal, wherein the GIP input signal comprises a VGH high level, a VGL low level and a CK clock signal, the GIP output stage transmission signal comprises Gn-4, Gn +4 and Gn, a T2 device, a T3 device, a T6 device and a T5 device are sequentially connected to the VGL low level at the bottom of a driving circuit, preferably, the T2 device is connected with a T1 device and a T7 device at the upper part of the driving circuit, a T4 device is connected between a Q point voltage bit and the T5 device, and the T4 device is connected with the CK clock signal.

The upper portion of the driving circuit, the VGH high level and the VGL low level, are connected with a T1 device and a T7 device respectively, a T1 device and a T7 device are connected with Gn-4 and Gn +4 respectively, the upper portion of the T1 device and the T7 device are connected with a Q point voltage bit, the Q point voltage bit is connected with a T4 device and a C2 capacitor, a C1 capacitor is connected between the T2 device and the T3 device, a CK clock signal is connected on the C1 capacitor, the T6 is connected with a C3 capacitor, preferably, the T3 device and the T6 device are connected, the T4 device is connected with the T5 device, Gn is connected between the T4 device and the T5 device, and Gn is connected with the C2 device.

A point voltage position is connected between the C2 capacitor and the C3 capacitor, the point voltage position A is respectively connected with a T8 device and a T9 device, the T8 device is respectively connected with Gn-4 and Gn-3, and the T9 device is respectively connected with Gn +3 and Gn + 4.

A design method of a power-consumption-saving high-refresh panel driving circuit specifically comprises the following steps:

step one, a driving circuit time sequence comprises Gout n-4, Gout n-3, a voltage bit at a point Q, a voltage bit at a point A, Gout n +3 and Gout n +4, when Gout n-4 is High, the Q point is charged to VGH-Vth through a T1 device, meanwhile, the T8 device is also in an on state under the action of Gout n-4, Gout n-3 is in a low level, and the voltage bit at the point A is in a low level;

step two, converting the Gout n-3 from a low level to a high level, charging the voltage bit of the point A from 0V to VGH-Vth, and doubling the voltage bit of the point Q to VGH-Vth;

and step three, the CK clock signal is changed from low level to high level, the Gout n output is VGH high level, the T1 device, the T7 device, the T8 device and the T9 device are in an off state, the voltage bit at the A point is capacitively coupled to twice VGH-Vth by the C3, the voltage bit at the Q point is capacitively coupled to three times VGH-Vth by the C1, when the CK clock signal is changed from high level to low level, the clock signal at the Q point is twice VGH-Vth, when Gout n +4 is high level, the T7 device and the T9 device are turned on, and the voltage bit at the Q point and the voltage bit at the A point are reset to low level.

Compared with the prior art, the invention has the beneficial effects that: through the 2-level coupling scheme to Q point voltage bit, under the unchangeable condition of Q point voltage bit voltage, can reduce the high level voltage of drive VGH, the size of the high level voltage of VGH directly influences the consumption of panel, uses this GIP circuit at high refresh high resolution ratio panel, reduces the drive VGH voltage, can effectively reduce panel power consumption.

Drawings

FIG. 1 is a diagram of a conventional 7T2C GIP circuit design;

FIG. 2 is a timing diagram of the circuit of FIG. 1;

FIG. 3 is a GIP driver design architecture diagram of the present invention;

fig. 4 is a timing diagram of the circuit of fig. 3.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

With the conventional GIP circuit design of 7T2C, as shown in fig. 1 and 2:

VGH is high level, VGL is low level, CK is clock signal, Gn is output terminal, T1-T7 are TFT devices, C1 and C2 are capacitors.

VGH, VGL, CK are input signals of GIP, and Gn-4, Gn +4 and Gn are level transfer signals output by GIP, and are used for controlling in-plane pixel TFT.

In the conventional a-Si TFT LCD, during the driving process of normal display, the GIP is turned on step by step, each row of the G1-Gn control panel, the states of G1-Gn and the Q point are shown in the time sequence of FIG. 2;

under the driving framework, the charging voltage of the point Q is about 2 times of VGH, taking the common requirement on the voltage of the point Q as 30V as an example, the driving VGH voltage is about 15V, and as the panel develops towards high refresh and high resolution, the higher the VGH voltage is, the higher the power consumption of the panel is; therefore, a new GIP structure is provided, which can reduce the driving VGH voltage under the condition of meeting the Q point voltage; the Q point of the GIP circuit adopts 2-stage coupling, and the VGH voltage reaches 10V by adopting the method by taking the common requirement on the voltage of the Q point as 30V as an example, so that the power consumption can be effectively reduced.

To effectively reduce power consumption of a high refresh high resolution panel, we have conceived a power consumption saving high refresh panel driving circuit design as shown in fig. 3 and 4, according to the conventional 7T2C structure, including a GIP input signal including a VGH high level, a VGL low level, and a CK clock signal, and a GIP output stage transfer signal including Gn-4, Gn +4, and Gn.

The driving circuit bottom VGL is connected with a T2 device, a T3 device, a T6 device and a T5 device in sequence at a low level, the T2 device is connected with a T1 device and a T7 device on the driving circuit, a T4 device is connected between a Q point voltage bit and the T5 device, and the T4 device is connected with a CK clock signal.

The upper portion of the drive circuit, VGH high and VGL low, is connected to the T1 and T7 devices, respectively, and the T1 and T7 devices are connected to Gn-4 and Gn +4, respectively, and the upper portion of the T1 and T7 devices are connected to a Q-point voltage bit, which is capacitively connected to the T4 and C2 devices.

A C1 capacitor is connected between the T2 device and the T3 device, a CK clock signal is connected to the C1 capacitor, the T6 is connected with the C3 capacitor, the T3 device is connected with the T6 device, the T4 device is connected with the T5 device, and Gn is connected between the T4 device and the T5 device and is connected with the C2 device.

A point voltage position is connected between the C2 capacitor and the C3 capacitor, the point voltage position A is respectively connected with a T8 device and a T9 device, the T8 device is respectively connected with Gn-4 and Gn-3, and the T9 device is respectively connected with Gn +3 and Gn + 4.

A design method of a power-consumption-saving high-refresh panel driving circuit specifically comprises the following steps:

step one, a driving circuit time sequence comprises Gout n-4, Gout n-3, a voltage bit at a point Q, a voltage bit at a point A, Gout n +3 and Gout n +4, when Gout n-4 is High, the Q point is charged to VGH-Vth through a T1 device, meanwhile, the T8 device is also in an on state under the action of Gout n-4, Gout n-3 is in a low level, and the voltage bit at the point A is in a low level;

step two, converting the Gout n-3 from a low level to a high level, charging the voltage bit of the point A from 0V to VGH-Vth, and doubling the voltage bit of the point Q to VGH-Vth;

and step three, the CK clock signal is changed from low level to high level, the Gout n output is VGH high level, the T1 device, the T7 device, the T8 device and the T9 device are in an off state, the voltage bit at the A point is capacitively coupled to twice VGH-Vth by the C3, the voltage bit at the Q point is capacitively coupled to three times VGH-Vth by the C1, when the CK clock signal is changed from high level to low level, the clock signal at the Q point is twice VGH-Vth, when Gout n +4 is high level, the T7 device and the T9 device are turned on, and the voltage bit at the Q point and the voltage bit at the A point are reset to low level.

Finally, it should be noted that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments or portions thereof without departing from the spirit and scope of the invention.

Claims (4)

1. A power consumption-saving high refresh panel driving circuit, comprising a GIP input signal including a VGH high level, a VGL low level and a CK clock signal, and a GIP output stage transfer signal including Gn-4, Gn +4 and Gn, characterized in that: a T2 device, a T3 device, a T6 device and a T5 device are connected to a VGL low level at the bottom of the driving circuit in sequence, a VGH high level and a VGL low level at the upper part of the driving circuit are connected with the T1 device and the T7 device respectively, a T1 device and a T7 device are connected with Gn-4 and Gn +4 respectively, the T1 device and the T7 device at the upper part are connected with a Q point voltage bit, the Q point voltage bit is connected with the T4 device and a C2 capacitor, a C1 capacitor is connected between the T2 device and the T3 device, a CK clock signal is connected to the C1 capacitor, the T6 capacitor is connected with the C3 capacitor, an A point voltage bit is connected between the C2 capacitor and a C3 capacitor, the A point voltage bit is connected with the T8 device and the T9 device respectively, the T8 device is connected with the Gn-4 and the Gn +3 device respectively, and the T9 device is connected with the Gn + 4.

2. The power consumption-saving high refresh panel driving circuit according to claim 1, wherein: the T2 device is connected with a T1 device and a T7 device on the upper portion of the driving circuit, a T4 device is connected between the voltage bit of the point Q and the T5 device, and the T4 device is connected with a CK clock signal.

3. The power consumption-saving high refresh panel driving circuit according to claim 1, wherein: the T3 device is connected with the T6 device, the T4 device is connected with the T5 device, and the T4 device is connected with the T5 device, and Gn is connected with the C2 device.

4. A method of designing a power consumption saving high refresh panel driving circuit according to any one of claims 1 to 3, characterized in that: the method specifically comprises the following steps:

step one, a driving circuit time sequence comprises Gout n-4, Gout n-3, a voltage bit at a point Q, a voltage bit at a point A, Gout n +3 and Gout n +4, when Gout n-4 is High, the Q point is charged to VGH-Vth through a T1 device, meanwhile, the T8 device is also in an on state under the action of Gout n-4, Gout n-3 is in a low level, and the voltage bit at the point A is in a low level;

step two, converting the Gout n-3 from a low level to a high level, charging the voltage bit of the point A from 0V to VGH-Vth, and doubling the voltage bit of the point Q to VGH-Vth;

and step three, the CK clock signal is changed from low level to high level, the Gout n output is VGH high level, the T1 device, the T7 device, the T8 device and the T9 device are in an off state, the voltage bit at the A point is capacitively coupled to twice VGH-Vth by the C3, the voltage bit at the Q point is capacitively coupled to three times VGH-Vth by the C1, when the CK clock signal is changed from high level to low level, the clock signal at the Q point is twice VGH-Vth, when Gout n +4 is high level, the T7 device and the T9 device are turned on, and the voltage bit at the Q point and the voltage bit at the A point are reset to low level.

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