CN213519205U

CN213519205U - Novel dual-output GIP circuit

Info

Publication number: CN213519205U
Application number: CN202022045976.4U
Authority: CN
Inventors: 刘振东; 阮桑桑; 刘汉龙; 郭智宇; 钟慧萍; 郑聪秀
Original assignee: Fujian Huajiacai Co Ltd
Current assignee: Fujian Huajiacai Co Ltd
Priority date: 2020-09-17
Filing date: 2020-09-17
Publication date: 2021-06-22
Anticipated expiration: 2030-09-17

Abstract

The utility model relates to a GIP circuit technical field, in particular to novel dual output GIP circuit, including the pre-charge module, first output module, the second output module, go up the drop-down module, first drop-down module and second drop-down module, first output module respectively with the pre-charge module, the second output module, go up the drop-down module and first drop-down module electricity is connected, the drop-down module is connected with pre-charge module and first drop-down module electricity respectively, the second drop-down module respectively with first drop-down module, second output module and last drop-down module electricity are connected, this scheme passes through the pre-charge module, first output module, the second output module, first drop-down module, second drop-down module and the cooperation between the drop-down module, utilize two rows of pixels of one-level GIP circuit drive, under the same condition of every row of pixel charge rate of guarantee, the screen ratio of screen has been improved.

Description

Novel dual-output GIP circuit

Technical Field

The utility model relates to a GIP circuit technical field, in particular to novel dual output GIP circuit.

Background

The full-screen display device not only improves the color value of the product and enables the product to look more scientific and technological, but also enables the front area of the product to accommodate a larger screen and improves the visual experience of a user, so that the full-screen technology becomes a popular trend of the current display device; the current definition of the full screen refers to a display device which has an ultra-high screen ratio design and pursues a screen ratio close to 100%; however, due to the current technical limitation, products of the so-called full screen type in the industry do not have a screen occupation ratio of 100%, but have an ultra-narrow frame product with a high screen occupation ratio, and the design of the high screen occupation ratio has already formed a trend, and particularly, the popularization rate of the products in medium and high-end models is very high.

In order to improve the screen occupation ratio of the screen, reducing the frame of the screen has become an inevitable trend of the current technology development; in an Active Matrix Liquid Crystal Display (hereinafter, referred to as an Active Matrix Liquid Crystal Display), each pixel has a TFT (Thin Film Transistor), a Gate (Gate) of which is connected to a horizontal scanning line (also referred to as a scanning signal line), a Source (Drain) of which is connected to a vertical data line (also referred to as a Source line), and a Source (Source) of which is connected to a pixel electrode; if a positive voltage is applied to a certain scan line in the horizontal direction, all the TFTs on the line are turned on, and the pixel electrodes on the line are connected with the data lines in the vertical direction, so that the video signal voltage on the data lines is written into the pixels, and the transmittance of different liquid crystals is controlled, thereby achieving the effect of controlling color; when the scanning drive of the panel is designed, COF (Chip On Film, namely, a crystal grain soft Film packaging technology for fixing an integrated circuit On a flexible circuit board) and COG (Chip On Glass, namely, a Chip is directly bound On Glass) technologies adopted by the traditional technology are adopted, and the product obtained by the technology has large left and right frames and high cost; the other new gip (gate In Panel) technology is based on the concept that a gate driver of an LCD Panel (meaning of a Liquid Crystal Display Panel, the english of the LCD is called Liquid Crystal Display) is integrated on a glass substrate instead of an external silicon wafer technology, which not only saves cost and reduces frames, but also saves a process of binding In the gate direction, is very beneficial to improving productivity, and improves the integration level of the TFT-LCD Panel.

The GIP technology reduces the usage amount of a gate drive IC, reduces power consumption and cost, can reduce the frame of a display panel and realize the design of a narrow frame, and is a valued technology; however, the mainstream driving mode of the current GIP circuit technology is a Gate mode in which one stage of GIP drives one row of pixels, and the screen occupation ratio of the screen is not high.

SUMMERY OF THE UTILITY MODEL

The utility model discloses the technical problem that will solve is: the novel double-output GIP circuit is provided, and the screen occupation ratio of a screen is improved under the condition that the charging rate of each row of pixels is guaranteed to be the same.

In order to solve the technical problem, the utility model discloses a technical scheme be:

the utility model provides a novel dual output GIP circuit, includes pre-charge module, first output module, second output module, goes up drop-down module, first drop-down module and second drop-down module, first output module is connected with pre-charge module, second output module, goes up drop-down module and first drop-down module electricity respectively, go up the drop-down module and be connected with pre-charge module and first drop-down module electricity respectively, the second drop-down module is connected with first drop-down module, second output module and go up the drop-down module electricity respectively, first output module's output and scanning signal line G_nElectrically connected to the output end of the second output module and the scanning signal line G_n+2Electrically connected to the scanning signal line G_nAnd a scanning signal line G_n+2The parameters n in (2) are all positive integers greater than or equal to 2.

The beneficial effects of the utility model reside in that:

the pre-charging module is arranged to play a pre-charging role; the first output module and the second output module are arranged to play a role in outputting signals; the first pull-down module and the second pull-down module are arranged to play a role in pulling down an output electric signal; first drop-down module is the drop-down module of first output module, the second drop-down module is the drop-down module of second output module, this scheme is through the pre-charge module, first output module, second output module, first drop-down module, the second drop-down module and the cooperation between the drop-down module, utilize two rows of pixels of one-level GIP circuit drive, under the condition that guarantee every row of pixel charge rate is the same, not only make the figure of GIP reduce, the size of frame about the screen also reduces simultaneously, the screen that has improved the screen accounts for the ratio.

Drawings

Fig. 1 is a block diagram of a module connection for a novel dual output GIP circuit according to the present invention;

fig. 2 is a specific circuit schematic diagram of a novel dual output GIP circuit according to the present invention;

fig. 3 is a timing diagram of a novel dual output GIP circuit according to the present invention;

fig. 4 is a circuit diagram during pre-charge of a novel dual output GIP circuit in accordance with the present invention;

fig. 5 is a circuit diagram during the output of a novel dual output GIP circuit in accordance with the present invention;

fig. 6 is a circuit diagram during pulldown of a novel dual output GIP circuit in accordance with the present invention;

fig. 7 is a circuit diagram during pull-down hold period of a novel dual output GIP circuit according to the present invention;

fig. 8 is a diagram of the simulation result of a novel dual output GIP circuit according to the present invention;

fig. 9 is a diagram of the simulation result of a novel dual output GIP circuit according to the present invention;

description of reference numerals:

1. a pre-charging module; 2. a first output module; 3. a second output module; 4. a pull-up and pull-down module; 5. a first pull-down module; 6. and a second pull-down module.

Detailed Description

In order to explain the technical content, the objects and the effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.

Referring to fig. 1, the present invention provides a technical solution:

From the above description, the beneficial effects of the present invention are:

Further, the vertical pulling module includes a fet T2, a fet T3, a fet T8, a fet T9, a fet T10, a fet T11, a fet T12, and a fet T13, the drain of the fet T2 is electrically connected to the gate of the fet T3, the drain of the fet T8, the drain of the fet T10, the source of the fet T12, the source of the fet T13, the source of the fet T11, the first pull-down module, and the second pull-down module, the source of the fet T2 is electrically connected to the source of the fet T3, the source of the fet T10, the first pull-down module, and the second pull-down module, the gate of the fet T2 is electrically connected to the gate of the fet T12 and the precharge module, the gate of the fet T8 is electrically connected to the source of the fet T8, and the drain of the fet T12 is electrically connected to the drain of the fet T13, The drain electrode of the field effect transistor T9, the drain electrode of the field effect transistor T11, the first pull-down module and the second pull-down module are electrically connected, and the gate electrode of the field effect transistor T9 is electrically connected with the source electrode of the field effect transistor T9.

Further, the first output module includes a fet T4 and a capacitor C1, a gate of the fet T4 is electrically connected to one end of the capacitor C1, the precharge module and the second output module, respectively, and a source of the fet T4 is electrically connected to the other end of the capacitor C1, the first pull-down module and the scan signal line G_nAnd the drain of the field effect transistor T4 is electrically connected with a clock signal CK 1.

Further, the second output module includes a fet T14 and a capacitor C2, a gate of the fet T14 is electrically connected to one end of the capacitor C2, the precharge module and the first output module, respectively, and a source of the fet T14 is electrically connected to the other end of the capacitor C2, the second pull-down module and the scan signal line G_n+2And the drain of the field effect transistor T14 is electrically connected with a clock signal CK 3.

Further, the first pull-down module comprises a field effect transistor T5 and a field effect transistor T15, the gate of the field effect transistor T5 is electrically connected with the pull-up and pull-down module and the second pull-down module respectively, the source of the field effect transistor T5 is electrically connected with the pull-up and pull-down module and the second pull-down module respectively, the drain of the field effect transistor T5 is electrically connected with the drain of the field effect transistor T15 and the first output module respectively, the gate of the field effect transistor T15 is electrically connected with the pull-up and pull-down module and the second pull-down module respectively, and the source of the field effect transistor T15 is electrically connected with the pull-up and pull-down module and the second pull-down module respectively.

Further, the second pull-down module comprises a field effect transistor T6 and a field effect transistor T16, a gate of the field effect transistor T6 is electrically connected with the first pull-down module and the upper and lower pull-down modules respectively, a drain of the field effect transistor T6 is electrically connected with a drain of the field effect transistor T16 and the second output module respectively, and a source of the field effect transistor T6 is electrically connected with a source of the field effect transistor T16, the upper and lower pull-down modules and the first pull-down module respectively.

Further, the pre-charge module includes a field effect transistor T1 and a field effect transistor T7, a gate of the field effect transistor T1 and a scan signal line G_n-2The drain electrode of the field effect transistor T1 is respectively and electrically connected with the source electrode of the field effect transistor T7, the first output module, the second output module and the pull-up and pull-down module, and the grid electrode of the field effect transistor T7 is connected with the scanning signal line G_n+6Electrically connected to the scanning signal line G_n-2And a scanning signal line G_n+6The parameters n in (2) are all positive integers greater than or equal to 2.

Referring to fig. 1 to 9, a first embodiment of the present invention is:

referring to fig. 1, a novel dual-output GIP circuit includes a pre-charge module 1, a first output module 2, a second output module 3, a pull-up and pull-down module 4, a first pull-down module 5 and a second pull-down module 6, wherein the first output module 2 is electrically connected to the pre-charge module 1, the second output module 3, the pull-up and pull-down module 4 and the first pull-down module 5, the pull-up and pull-down module 4 is electrically connected to the pre-charge module 1 and the first pull-down module 5, the second pull-down module 6 is electrically connected to the first pull-down module 5, the second output module 3 and the pull-up and pull-down module 4, an output end of the first output module 2 is electrically connected to a scan signal line G_nElectrically connected with the output end of the second output module 3 and the scanning signal line G_n+2Electrically connected to the scanning signal line G_nAnd a scanning signal line G_n+2The parameters n in (2) are all positive integers greater than or equal to 2.

Referring to fig. 2, the pull-up/down module 4 includes a fet T2, a fet T3, a fet T8, a fet T9, a fet T10, a fet T11, a fet T12, and a fet T13, a drain of the fet T2 is electrically connected to a gate of the fet T3, a drain of the fet T8, a drain of the fet T10, a source of the fet T12, a source of the fet T13, a source of the fet T11, a first pull-down module 5, and a second pull-down module 6, a source of the fet T2 is electrically connected to a source of the fet T3, a source of the fet T10, the first pull-down module 5, and the second pull-down module 6, a gate of the fet T2 is electrically connected to a gate of the fet T12 and the precharge module 1, a gate of the fet T8 is electrically connected to a source of the fet T8, the drain of the field effect transistor T12 is electrically connected to the gate of the field effect transistor T13, the drain of the field effect transistor T9, the drain of the field effect transistor T11, the first pull-down module 5 and the second pull-down module 6, respectively, and the gate of the field effect transistor T9 is electrically connected to the source of the field effect transistor T9.

Referring to fig. 2, the first output module 2 includes a fet T4 and a capacitor C1, a gate of the fet T4 is electrically connected to one end of the capacitor C1, the precharge module 1 and the second output module 3, respectively, and a source of the fet T4 is electrically connected to the other end of the capacitor C1, the first pull-down module 5 and the scan signal line G_nAnd the drain of the field effect transistor T4 is electrically connected with a clock signal CK 1.

Referring to fig. 2, the second output module 3 includes a fet T14 and a capacitor C2, a gate of the fet T14 is electrically connected to one end of the capacitor C2, the precharge module 1 and the first output module 2, respectively, and a source of the fet T14 is electrically connected to the other end of the capacitor C2, the second pull-down module 6 and the scan signal line G_n+2And the drain of the field effect transistor T14 is electrically connected with a clock signal CK 3.

Referring to fig. 2, the first pull-down module 5 includes a fet T5 and a fet T15, a gate of the fet T5 is electrically connected to the pull-up and pull-down module 4 and the second pull-down module 6, a source of the fet T5 is electrically connected to the pull-up and pull-down module 4 and the second pull-down module 6, a drain of the fet T5 is electrically connected to a drain of the fet T15 and the first output module 2, a gate of the fet T15 is electrically connected to the pull-up and pull-down module 4 and the second pull-down module 6, and a source of the fet T15 is electrically connected to the pull-up and pull-down module 4 and the second pull-down module 6.

Referring to fig. 2, the second pull-down module 6 includes a fet T6 and a fet T16, a gate of the fet T6 is electrically connected to the first pull-down module 5 and the pull-up and pull-down module 4, a drain of the fet T6 is electrically connected to a drain of the fet T16 and the second output module 3, and a source of the fet T6 is electrically connected to a source of the fet T16, the pull-up and pull-down module 4, and the first pull-down module 5.

Referring to fig. 2, the pre-charge module 1 includes a fet T1 and a fet T7, the gate of the fet T1 and a scan signal line G_n-2The drain of the FET T1 is electrically connected with the source of the FET T7, the first output module 2, the second output module 3 and the pull-up and pull-down module 4, respectively, and the gate of the FET T7 is connected with the scanning signal line G_n+6Electrically connected to the scanning signal line G_n-2And a scanning signal line G_n+6The parameters n in (2) are all positive integers greater than or equal to 2.

The working principle of the novel double-output GIP circuit is as follows:

referring to fig. 3, in the timing chart, the timing chart is divided into four time periods, namely, a precharge period, an output period, a pull-down period and a pull-down sustain period, and the operating states of TFTs (Thin Film transistors) corresponding to each of the four time periods are different, specifically as follows:

referring to FIG. 4, a schematic diagram of a precharge period corresponding to time t1 of FIG. 3 is shown, wherein the scan signal line G is at this time_n-2The potential signal line FW and the potential signal line V1 are both high potential, and the corresponding field effect tube T1, the corresponding field effect tube T2, the corresponding field effect tube T4, the corresponding field effect tube T8, the corresponding field effect tube T11, the corresponding field effect tube T12 and the corresponding field effect tube T14 are all opened; scanning signal line G_n+6Potential signal line BW, clockThe signal CK1, the clock signal CK3 and the potential signal line V2 are all low potentials, and the corresponding field-effect tube T3, the corresponding field-effect tube T5, the corresponding field-effect tube T6, the corresponding field-effect tube T7, the corresponding field-effect tube T9, the corresponding field-effect tube T10, the corresponding field-effect tube T13, the corresponding field-effect tube T15 and the corresponding field-effect tube 16 are all closed; at this stage, the fet T1 is turned on, the FW signal line is at a high potential, the capacitor C1 and the capacitor C2 are charged, the potentials of the Q1 node, the Q2 node and the Q3 node rise to H, the fet T4 and the fet T14 are both turned on, and the CK1 and the CK3 are both at a low potential, so that the G signal line is scanned_nAnd a scanning signal line G_n+2The node P1 is pulled low by VGL because fet T2 is turned on, and the node P2 is pulled low because fet T11 and fet T12 are both turned on.

Referring to fig. 5, it is a schematic diagram of an output period, which corresponds to time T2 of fig. 3, when the clock signal CK1, the clock signal CK3, the voltage signal line FW, the voltage signal lines V1 and Q1 nodes, and the Q2 node and the Q3 nodes are all at high voltage, and the corresponding fets T2, T4, T8, T11, T12, and T14 are all turned on; scanning signal line G_n-2Scanning signal line G_n+6The potential signal line BW, the potential signal line V2, the node P1 and the node P2 are all low potentials, and the corresponding fet T1, fet T3, fet T5, fet T6, fet T7, fet T9, fet T10, fet T13, fet T15 and fet T16 are all turned off; at this stage, since the FET T4 and the FET T8 are both turned on, and the clock signal CK1 and the clock signal CK3 are both at high level, the GIP signal, i.e., the scanning signal line G, is outputted_nAnd a scanning signal line G_n+2Is high, and the Q1 node is coupled to the potential of 2H due to the coupling effect of the capacitor C1 and the capacitor C2, respectively, stabilizing the scanning signal line G_nAnd a scanning signal line G_n+2The turn-on of the fet T2 and the fet T12 is also stabilized, and the P1 node and the P2 node are pulled to the low potential by the VGL.

Referring to fig. 6, a schematic diagram of a pull-down period is shown, which corresponds to time t3 of fig. 3At this time, the signal line G is scanned_n+6The potential signal line FW and the potential signal line V1 are both high potential, and the corresponding field effect transistor T7, the corresponding field effect transistor T8 and the corresponding field effect transistor T11 are all opened; scanning signal line G_n-2The potential signal line BW, the clock signal CK1, the clock signal CK3 and the potential signal line V2 are all low potentials, and the corresponding fet T1, fet T2, fet T3, fet T4, fet T5, fet T6, fet T9, fet T10, fet T12, fet T13, fet T14, fet T15 and fet T16 are all turned off; at this stage, since the fet T7 is turned on, the potential signal line BW is low, and the Q1 node, the Q2 node, and the Q3 node are pulled low; since the potentials of the node Q1, the node Q2 and the node Q3 are lowered, the fet T2 is turned off, and the potentials of the node P1 and the node P2 are slowly raised.

Fig. 7 is a schematic diagram of a pull-down sustain period, which corresponds to time T4 of fig. 3, wherein the potential signal line FW and the potential signal line V1 are both at high potential, and correspond to the turn-on of the fets T8 and T9; scanning signal line G_n-2Scanning signal line G_n+6The potential signal line BW is low potential, the corresponding field effect transistor T1 and the corresponding field effect transistor T7 are closed, the node Q1, the node Q2 and the node Q3 are low potential at this time, the field effect transistor T2, the field effect transistor T4, the field effect transistor T12 and the field effect transistor T14 are closed, the node P1 is high potential, the field effect transistor T3, the field effect transistor T5 and the field effect transistor T6 are opened, and the opening of the TFTs stabilizes the node Q1, the node Q2, the node Q3 and the scanning signal line G6_nAnd a scanning signal line G_n+2Low potential of (c).

Please refer to fig. 8 and fig. 9, which are simulation result diagrams of the dual output GIP circuit according to the present invention: in the simulation result diagram, the output signal G of the GIP of each stage can be seen_nAnd G_n+2As a result, the potentials of the node Q1, the node Q2, the node Q3, the node P1 and the node P2 are normal, and the charging rates of the pixels at the upper and lower stages of the two Gout signals output by the same GIP are also the same (in this patent, the charging rates of the pixels of the adjacent output signals are 92% by taking a 6.8 inch a-Si HD product as an example for simulation). And is composed ofThe P1 node and the P2 node are charged by the TFTs, so that the high potentials of the P1 node and the P2 node are effectively maintained, and the influence of clock signals on the coupling action of the Q1 node, the Q2 node and the Q3 node through the off-state capacitances of the field effect transistor T4 and the field effect transistor T14 is prevented.

The waveform diagram in FIG. 8 is the scanning signal line G from top to bottom_n-2Output waveform diagrams of the clock signal CK1 and the clock signal CK 3;

the waveform diagram in FIG. 9 is an output waveform diagram of a Q node (Q1 node, Q2 node, and Q3 node have the same output waveform, and are indicated by Q node in the figure), CL 1 (gate output signal of field effect transistor T4), CL 3 (gate output signal of field effect transistor T14), and a P node (P1 node and P2 node have the same output waveform, and are indicated by P node in the figure) in sequence from top to bottom.

In summary, the novel dual-output GIP circuit provided by the utility model has a pre-charging function by arranging the pre-charging module; the first output module and the second output module are arranged to play a role in outputting signals; the first pull-down module and the second pull-down module are arranged to play a role in pulling down an output electric signal; first drop-down module is the drop-down module of first output module, the second drop-down module is the drop-down module of second output module, this scheme is through the pre-charge module, first output module, second output module, first drop-down module, the second drop-down module and the cooperation between the drop-down module, utilize two rows of pixels of one-level GIP circuit drive, under the condition that guarantee every row of pixel charge rate is the same, not only make the figure of GIP reduce, the size of frame about the screen also reduces simultaneously, the screen that has improved the screen accounts for the ratio.

The above mentioned is only the embodiment of the present invention, and not the limitation of the patent scope of the present invention, all the equivalent transformations made by the contents of the specification and the drawings, or the direct or indirect application in the related technical field, are included in the patent protection scope of the present invention.

Claims

1. A novel double-output GIP circuit is characterized by comprising a pre-charging module, a first output module and a second outputThe module comprises a module, an upper pull-down module, a lower pull module, a first pull-down module and a second pull-down module, wherein the first output module is respectively and electrically connected with a pre-charging module, the second output module, the upper pull-down module and the first pull-down module, the upper pull-down module is respectively and electrically connected with the pre-charging module and the first pull-down module, the second pull-down module is respectively and electrically connected with the first pull-down module, the second output module and the upper pull-down module, and the output end of the first output module is connected with a scanning signal line G_nElectrically connected to the output end of the second output module and the scanning signal line G_n+2Electrically connected to the scanning signal line G_nAnd a scanning signal line G_n+2The parameters n in (2) are all positive integers greater than or equal to 2.

2. The novel dual output GIP circuit as claimed in claim 1, wherein said pull-up and pull-down modules comprise FET T2, FET T3, FET T8, FET T9, FET T10, FET T11, FET T12 and FET T13, said FET T2 has its drain electrically connected to gate of FET T3, drain of FET T8, drain of FET T10, source of FET T12, source of FET T13, source of FET T11, first pull-down module and second pull-down module, respectively, said FET T2 has its source electrically connected to source of FET T3, source of FET T10, first pull-down module and second pull-down module, said FET T2 has its gate electrically connected to gate of FET T12 and precharge module, said FET T8 has its gate electrically connected to source of FET T8, the drain of the field effect transistor T12 is electrically connected with the gate of the field effect transistor T13, the drain of the field effect transistor T9, the drain of the field effect transistor T11, the first pull-down module and the second pull-down module respectively, and the gate of the field effect transistor T9 is electrically connected with the source of the field effect transistor T9.

3. The novel dual-output GIP circuit as claimed in claim 1, wherein said first output module comprises a FET T4 and a capacitor C1, the gate of said FET T4 is connected to one terminal of the capacitor C1, the pre-charge module and the fourth output module respectivelyThe two output modules are electrically connected, and the source electrode of the field effect transistor T4 is respectively connected with the other end of the capacitor C1, the first pull-down module and the scanning signal line G_nAnd the drain of the field effect transistor T4 is electrically connected with a clock signal CK 1.

4. The novel dual-output GIP circuit as claimed in claim 1, wherein said second output module comprises a FET T14 and a capacitor C2, a gate of said FET T14 is electrically connected to one end of the capacitor C2, the pre-charge module and the first output module, respectively, a source of said FET T14 is electrically connected to the other end of the capacitor C2, the second pull-down module and the scan signal line G, respectively_n+2And the drain of the field effect transistor T14 is electrically connected with a clock signal CK 3.

5. The novel dual-output GIP circuit of claim 1, wherein said first pull-down module comprises a FET T5 and a FET T15, said FET T5 has a gate electrically connected to said pull-up and pull-down modules and said second pull-down module, respectively, said FET T5 has a source electrically connected to said pull-up and pull-down modules and said second pull-down module, said FET T5 has a drain electrically connected to said FET T15 and said first output module, said FET T15 has a gate electrically connected to said pull-up and pull-down modules and said second pull-down module, respectively, and said FET T15 has a source electrically connected to said pull-up and pull-down modules and said second pull-down module, respectively.

6. The novel dual-output GIP circuit of claim 1, wherein said second pull-down module comprises a FET T6 and a FET T16, a gate of said FET T6 is electrically connected to said first pull-down module and said pull-up and pull-down module, respectively, a drain of said FET T6 is electrically connected to said drain of said FET T16 and said second output module, respectively, a source of said FET T6 is electrically connected to said source of said FET T16, said pull-up and pull-down modules, and said first pull-down module, respectively.

7. The novel dual output GIP circuit of claim 1, wherein saidThe pre-charging module comprises a field effect transistor T1 and a field effect transistor T7, wherein the grid electrode of the field effect transistor T1 is connected with a scanning signal line G_n-2The drain electrode of the field effect transistor T1 is respectively and electrically connected with the source electrode of the field effect transistor T7, the first output module, the second output module and the pull-up and pull-down module, and the grid electrode of the field effect transistor T7 is connected with the scanning signal line G_n+6Electrically connected to the scanning signal line G_n-2And a scanning signal line G_n+6The parameters n in (2) are all positive integers greater than or equal to 2.