CN113962186A

CN113962186A - Chip layout method and device, terminal equipment and computer readable storage medium

Info

Publication number: CN113962186A
Application number: CN202111262352.0A
Authority: CN
Inventors: 涂宏斌; 刘雨芃; 郑文耀; 李�杰; 赵瑞敏; 徐任玉; 于明; 尹立一; 王昊天
Original assignee: Hunan Great Wall Science And Technology Information Co ltd; China Great Wall Technology Group Co ltd
Current assignee: Hunan Great Wall Science And Technology Information Co ltd; China Great Wall Technology Group Co ltd
Priority date: 2021-10-28
Filing date: 2021-10-28
Publication date: 2022-01-21

Abstract

The application is applicable to the technical field of data processing, and provides a chip layout method, a chip layout device, terminal equipment and a computer-readable storage medium, wherein the chip layout method comprises the following steps: obtaining a plurality of candidate layouts of a chip on a target circuit board; constructing a graph model corresponding to each of the multiple candidate layouts, wherein nodes in the graph model are chips on a target circuit board, edges between two nodes in the graph model represent that signal interaction exists between the chips represented by the two nodes, and weights on the edges between the two nodes in the graph model are determined by distances between the chips represented by the two nodes on the target circuit board; predicting the circuit power consumption corresponding to each of the multiple candidate layouts according to the graph model and a preset power consumption prediction model; and determining the candidate layout corresponding to the minimum value in the circuit power consumption corresponding to the various candidate layouts as the target layout. By the method, the intelligent degree of chip layout can be improved, and the optimality of final layout can be ensured.

Description

Chip layout method and device, terminal equipment and computer readable storage medium

Technical Field

The present application belongs to the technical field of data processing, and in particular, to a chip layout method, apparatus, terminal device, and computer-readable storage medium.

Background

The design of an integrated circuit layout includes placement and routing. Layout refers to the process of determining the placement of each logic module or chip of a circuit to be designed on a circuit board. Wiring refers to the process of determining the order of electrical connections between logic modules or chips.

The layout methods commonly used in the prior art include manual layout and automatic layout. Wherein, the manual layout efficiency is lower, and the professional requirement to the designer is higher. Most automatic layout methods require manual intervention, have low intelligence degree and cannot ensure the optimality of final layout.

Disclosure of Invention

The embodiment of the application provides a chip layout method, a chip layout device, terminal equipment and a computer readable storage medium, which can improve the intelligence degree of chip layout and ensure the optimality of final layout.

In a first aspect, an embodiment of the present application provides a chip layout method, including:

obtaining a plurality of candidate layouts of a chip on a target circuit board;

constructing a graph model corresponding to each of the plurality of candidate layouts, wherein nodes in the graph model are chips on the target circuit board, edges between two nodes in the graph model represent that signal interaction exists between the chips represented by the two nodes, and weights on the edges between the two nodes in the graph model are determined by distances of the chips represented by the two nodes on the target circuit board;

predicting the circuit power consumption corresponding to each of the multiple candidate layouts according to the graph model and a preset power consumption prediction model;

and determining the candidate layout corresponding to the minimum value in the circuit power consumption corresponding to the various candidate layouts as a target layout.

In the embodiment of the application, the signal interaction relation among chips in the candidate layout is described through a graph model, the power consumption of a circuit of the candidate layout is predicted according to the graph model and a power consumption prediction model, and the target layout is determined from a plurality of candidate layouts according to the power consumption of the circuit. By the method, the signal interaction relation among the chips in each layout is considered in the layout process, and the circuit power consumption corresponding to each layout is considered, so that the target layout with the minimum circuit power consumption can be obtained, and the optimality of the target layout is guaranteed. In addition, the method in the embodiment of the application does not need manual intervention, and the intelligent degree of chip layout is greatly improved.

In a possible implementation manner of the first aspect, the obtaining multiple candidate layouts of a chip on a target circuit board includes:

randomly acquiring N initial solutions, wherein each initial solution represents a layout of a chip on the target circuit board, and N is a positive integer greater than 1;

calculating target solutions corresponding to the N initial solutions according to a simulated annealing algorithm;

determining the layout of the chip on the target circuit board represented by each target solution as one of the candidate layouts.

In a possible implementation manner of the first aspect, the calculating, according to a simulated annealing algorithm, a target solution corresponding to each of the N initial solutions includes:

optimizing initial parameters of the simulated annealing algorithm based on a Bayesian optimization algorithm to obtain optimized initial parameters;

and calculating target solutions corresponding to the N initial solutions according to the optimized initial parameters and the simulated annealing algorithm.

In one possible implementation manner of the first aspect, the power consumption prediction model includes a graph neural network and a long-term memory network;

the predicting the circuit power consumption corresponding to each of the candidate multi-clock layouts according to the graph model and a preset power consumption prediction model comprises the following steps:

respectively inputting the graph models corresponding to the candidate layouts into the graph neural network to obtain first feature information of the candidate layouts, wherein the first feature information represents correlation features of chips in the candidate layouts on the space;

inputting the first feature information of each of the multiple candidate layouts into the long-time memory network respectively to obtain second feature information of each of the multiple candidate layouts, wherein the second feature information represents the associated feature of each chip in the candidate layouts in terms of time;

and predicting the circuit power consumption of each candidate layout according to the second characteristic information of each candidate layout.

In a possible implementation manner of the first aspect, after determining, as the target layout, the candidate layout corresponding to the minimum value of the circuit power consumptions corresponding to the respective candidate layouts, the method further includes:

and iteratively searching a target wiring sequence meeting the target layout based on a particle swarm algorithm, wherein the particle position in the particle swarm algorithm represents the wiring sequence of the chip on the target circuit board, and the particle speed is used for updating the particle position.

In a possible implementation manner of the first aspect, the iteratively searching for the target wiring order satisfying the target layout based on the particle swarm algorithm includes:

in the process of each iterative search, calculating the fitness variance of the current population;

if the fitness variance is smaller than a preset threshold value, performing chaotic variation processing on part of particles in the current population to obtain a processing population;

calculating a local optimal solution and a global optimal solution of the processing population;

updating the particle position and the particle speed of each particle in the processing population according to the local optimal solution and the global optimal solution of the processing population to obtain the updated particle position and particle speed;

if the current iteration times reach preset times, determining the target wiring sequence according to the global optimal solution of the processing population;

and if the current iteration times do not reach the preset times, continuing the next iteration search according to the updated particle position and particle speed.

In a possible implementation manner of the first aspect, if the fitness variance is smaller than a preset threshold, performing chaotic variation processing on part of the particles in the current population to obtain a processed population, including:

calculating the particle fitness of each particle in the current population;

selecting a first sub-population from the current population according to the particle fitness, wherein the first sub-population comprises M particles, and M is a positive integer greater than 1;

transforming the positions of H particles in the first sub-population to obtain a transformed first sub-population, wherein H is more than or equal to 1 and less than or equal to M;

and constructing the processing population according to a second sub-population and the transformed first sub-population, wherein the second sub-population is a population except the first sub-population in the current population.

In a second aspect, an embodiment of the present application provides a chip wiring device, including:

an acquisition unit configured to acquire a plurality of candidate layouts of a chip on a target circuit board;

a building unit, configured to build a graph model corresponding to each of the multiple candidate layouts, where a node in the graph model is a chip on the target circuit board, an edge between two nodes in the graph model indicates that there is signal interaction between the chips represented by the two nodes, and a weight on the edge between the two nodes in the graph model is determined by a distance between the chips represented by the two nodes on the target circuit board;

the prediction unit is used for predicting the circuit power consumption corresponding to each of the candidate layouts according to the graph model and a preset power consumption prediction model;

and the layout unit is used for determining the candidate layout corresponding to the minimum value in the circuit power consumption corresponding to each of the candidate layouts as the target layout.

In a third aspect, an embodiment of the present application provides a terminal device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor, when executing the computer program, implements the chip layout method according to any one of the first aspect.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, and the embodiment of the present application provides a computer-readable storage medium, where a computer program is stored, where the computer program, when executed by a processor, implements the chip layout method according to any one of the above first aspects.

In a fifth aspect, an embodiment of the present application provides a computer program product, which, when running on a terminal device, causes the terminal device to execute the chip layout method according to any one of the above first aspects.

It is understood that the beneficial effects of the second aspect to the fifth aspect can be referred to the related description of the first aspect, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a schematic flowchart of a chip layout method according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a graphical model provided by an embodiment of the present application;

FIG. 3 is a schematic diagram of a power consumption prediction model provided by an embodiment of the present application;

fig. 4 is a block diagram of a chip wiring device provided in an embodiment of the present application;

fig. 5 is a schematic structural diagram of a terminal device according to an embodiment of the present application.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It will be understood that the terms "comprises" and/or "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

As used in this specification and the appended claims, the term "if" may be interpreted contextually as "when.. or" upon "or" in response to a determination "or" in response to a detection ".

Furthermore, in the description of the present application and the appended claims, the terms "first," "second," "third," and the like are used for distinguishing between descriptions and not necessarily for describing or implying relative importance.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise.

Referring to fig. 1, which is a schematic flow chart of a chip layout method provided in an embodiment of the present application, by way of example and not limitation, the method may include the following steps:

s101, obtaining a plurality of candidate layouts of the chip on the target circuit board.

In one embodiment, a simulated annealing algorithm may be employed to obtain the candidate layouts. Specifically, S101 may include: randomly acquiring N initial solutions, wherein each initial solution represents a layout of a chip on a target circuit board, and N is a positive integer greater than 1; calculating target solutions corresponding to the N initial solutions according to a simulated annealing algorithm; the layout of the chip on the target circuit board represented by each target solution is determined as a candidate layout.

In the embodiment of the application, the idea of optimizing the basic problem by the simulated annealing algorithm is as follows: and considering the temperature T as an objective function f, calculating the objective function f from the initial solution, generating a new solution, calculating the objective function value again, comparing the objective function value with the objective function value calculated in the previous step, and judging whether to accept the new solution. And repeating the processes until the control parameter is attenuated to zero, and finally obtaining the approximate optimal solution of the optimization problem.

In the simulated annealing algorithm, a new solution is accepted probabilistically, a good solution is accepted hundreds of percent, a bad solution is accepted with a certain probability, and the probability of accepting the new solution is as follows:

wherein, T_iTo solve for the global maximum temperature, T, corresponding to i_i-T_jK is the boltzmann constant, which is the change of the global maximum temperature. If T_j≤T_iThen accept the new solution j; if T_j>T_iWhen the probability p is equal to exp [ (T)_i-T_j)/KT]And when the random number is within the interval of [0,1), accepting a new solution j, and otherwise, keeping the solution i.

The set of all the arrangement modes of the chips on the integrated circuit board is defined as a solution space X, each layout of the chips belongs to the solution space, and assuming that n chips exist on the current board, the general form of the board chip layout solution is X ═ X₁,x₂,x₃,…,x_nIn which x₁,x₂,x₃,…,x_nRespectively representing n chips, x₁,x₂,x₃,…,x_nThe respective numerical values indicate the positions of the chips on the board. Thus, the solution x in vector form corresponds one-to-one to the layout of the chip.

There are typically one or more core chips on an actual integrated circuit board, and the location of the chips is also typically limited. The power heat load is usually the largest of all the chips, and the upper limit of the temperature of the chip also determines the upper limit of the temperature of the whole plate. Because some electronic components have different functions, different powers, different shapes and different materials, the chips also have special requirements on the distribution of positions, if the position of the device is given and unchanged, the position layout of other electronic components can be changed, and the positions of other electronic components can be matched with the changed positions. In this case, the thermal layout of the entire component is optimized by fixing the position of one or more components and then optimizing the layout of those components that can be changed in position. Therefore, the positions of some core chips on the integrated circuit board are fixed by increasing constraint conditions, and then the simulated annealing algorithm is adopted to enable other chips on the integrated circuit board to surround the core chips for conditional thermal layout optimization.

Defining the fixed chip as g, if the fixed number is m, the fixed constraint condition is g ═ g₁,g₂,g₃,…,g_mAnd indicates that the positions of m chips are fixed when the algorithm generates a new solution iteration. For example, if m is 1, g₁By 5, it is meant that the 5 th chip at a given initial solution is fixed. And similarly, the positions of a plurality of chips can be fixed at the same time, and the positions of other chips are adjusted during calculation to optimize the thermal layout.

Because the thermal layout optimization of the chip is conditional thermal layout optimization, the core chip with constraint conditions has larger heating power, and the common highest temperature is the position of the maximum power chip, the global highest temperature t of the chip on board during working is realized_maxAs an objective function of the present algorithm, T ═ T (T) is defined₁,t₂,t₃,…,t_n)＝t_max。

The steps of the simulated annealing algorithm are as follows:

1. and initializing parameters. Setting a sufficiently large initial temperature T, fixing the serial number g of the chip and the iteration number L. Randomly generating an initial solution: x is the number of⁰＝{x₁,x₂,x₃,…,x_nRepresents a random layout of the chip. Get the global maximum temperature t of the chip during operation_maxAs the target temperature value for the present algorithm. The initial solution is stored as the current solution, and the objective function value is the highest temperature t of all chips_max。

2. The current solution x is transposed to { x using a binary method (i.e., any two of the current solutions are transposed)₁,x₂,…,x_u,…x_v,…,x_nPerforming an element transformation yields a new solution x ═ x₁,x₂,…,x_v,…x_u,…,x_n}. Element x_uAnd x_vNone of which belong to elements in the fixed constraint, otherwise a new solution is regenerated.

3. Solving the objective function value T' of the new solution generated in step 2 (global in the current state)The highest temperature) and then compared to the current solution objective function value to yield the objective function value difference between the two solutions, Δ T ═ T' -T. And judging the new solution according to the acceptance probability. When T'<When T is reached, the new solution is accepted as the current solution calculated in the next step, and the layout corresponding to the new solution is stored as the new layout; otherwise by formula

The calculated probability accepts a new solution; and if the new solution is refused to be accepted, taking the current solution as the current solution of the next step, and taking the objective function value as the objective function value calculated in the previous step.

4. Judging whether the calculation reaches a termination condition, and if so, outputting the current solution as a global optimal layout; if the termination condition is not met, judging whether the iteration times are met, and if the iteration times are not met, jumping to the step 2; and if the iteration times are reached, outputting the current solution as the global optimal layout.

Wherein, the judgment of the termination condition comprises the following steps: and if the iteration is continuously carried out for a plurality of times, the new solution is refused to be accepted in the step 4, and the current solution is reserved as the new solution, the algorithm is terminated.

As described above, the simulated annealing algorithm has the following three parameter problems:

problem one, initial value setting problem of temperature T

The initial value setting of the temperature T is one of important factors influencing the global search performance of the simulated annealing algorithm, and if the initial temperature is high, the possibility of searching the global optimal solution is high, but a large amount of calculation time is consumed; conversely, computation time may be saved, but global search performance may be affected.

Problem two, annealing speed problem, i.e. number of iterations per value of T

The global search performance of the simulated annealing algorithm is also closely related to the annealing speed. In general, a "full" search at the same temperature is quite necessary, but this also requires calculation time. An increase in the number of loops entails an increase in computational overhead.

Problem three, temperature management problem

The temperature management problem is also one of the problems that the simulated annealing algorithm is difficult to handle. In practical application, practical feasibility of computational complexity must be considered.

In the application, a Bayesian optimization algorithm is adopted to optimally select the initial value of the simulated annealing algorithm, the annealing speed and the parameters of temperature management.

In one embodiment, the step of calculating a target solution corresponding to each of the N initial solutions according to the simulated annealing algorithm may include: optimizing initial parameters of a simulated annealing algorithm based on a Bayesian optimization algorithm to obtain optimized initial parameters; and calculating target solutions corresponding to the N initial solutions according to the optimized initial parameters and the simulated annealing algorithm.

The Bayesian optimization algorithm is based on the Bayesian theorem as a theoretical basis, and the theorem is expressed as follows:

wherein f is a parameter in the model (such as initial temperature T and iteration number L in the simulated annealing algorithm), D_1:t＝{(x₁,y₁),(x₂,y₂),…,(x_t,y_t) Is the set of evaluated points (e.g., x when f represents temperature₁Corresponding to y₁Temperature T1), x_tAs a decision vector, y_tAs an observed value, p (D)_1:tIf) is y_tLikelihood distribution of p (D)_1:t) Marginal likelihood distribution of f, p (f) prior probability of f, p (f | D)_1:t) Is the posterior probability of f. The posterior probability distribution is the confidence of the parameters in the parametric model after the priors are modified by the set of evaluated points. The Bayesian optimization algorithm uses a probability agent model to fit a real objective function, and selects the next evaluation point according to the collection function.

The probabilistic proxy model of the gaussian process is used in this process. The gaussian process is a normalization of multivariate gaussian probability distribution and is composed of a mean function and a semi-positive covariance function, namely:

t_t＝gp(m(x_t),k(x_t,x′_t))

where m () is the mean function and k () is the covariance function. Using a Gaussian process to pair a series of discrete data pairs (x)_t,y_t) A function fit is made, m () is typically set to 0,

wherein r is x_tAnd x_t' Euler distance, σ_fIs a characteristic deviation, σ_lIs a characteristic length, σ_fAnd σ_lWill automatically vary with the Gaussian process fit, σ_lHas an initial value of x_iStandard deviation of (a)_fHas an initial value of y_iIs divided by the standard deviation of

The acquisition function constructed based on the strategy of the lifting probability and the lifting amount is as follows:

wherein alpha is_t(x；D_1:t) For the acquisition function, v^*For the current value of the optimum function,

is a standard normal distribution cumulative density function, mu_t(x) And σ_t(x) Mean and standard deviation, respectively.

For D_1:t＝{(x₁,y₁),(x₂,y₂),…,(x_t,y_t) In this, a new x is selected_t+1So that

x_t+1＝argmaxα(x_t+1,D_t)；

α is the acquisition function above. Then x is put_t+1Substitution of y_t＝gp(m(x_t),k(x_t,x_t')) to obtain y_t+1Updating the data set D_1:t+1＝{D_1:t,(x_t+1,y_t+1)}. And finally, updating the probability distribution of the parameters and repeating iterative computation. And finally outputting the result of the parameters as the optimal set parameter value in the simulated annealing algorithm.

S102, constructing graph models corresponding to the candidate layouts.

Fig. 2 is a schematic diagram of a graph model provided in an embodiment of the present application. As shown in fig. 2, the node in the graph model is a chip A, B on the target circuit board, an edge between two nodes in the graph model indicates that there is signal interaction between chips respectively represented by the two nodes, and a weight on the edge between the two nodes in the graph model is determined by a distance between the chips respectively represented by the two nodes on the target circuit board. n is_A,BThe calculation formula is as follows:

in the formula: l_A,BIs the distance of 2 chips on the plate, R_hTo be just off the threshold. When composing a picture, only the distance is calculated to be less than R_hConsidering that the chips are not completely and orderly arranged, the adoption of Euclidean distance measurement can introduce wrong prior knowledge, so that the relevance between elements is measured by adopting the Manhattan distance.

And S103, predicting the circuit power consumption corresponding to each of the multiple candidate layouts according to the graph model and a preset power consumption prediction model.

In one embodiment, the power consumption prediction model includes a graph neural network and a long-term memory network.

Accordingly, S103 may include:

respectively inputting the graph models corresponding to the various candidate layouts into a graph neural network to obtain first feature information of the various candidate layouts, wherein the first feature information represents the correlation features of chips in the candidate layouts on the space; respectively inputting the first characteristic information of each of the multiple candidate layouts into a long-term memory network to obtain second characteristic information of each of the multiple candidate layouts, wherein the second characteristic information represents the correlation characteristics of each chip in the candidate layouts in terms of time; and predicting the circuit power consumption of each of the candidate layouts according to the second characteristic information of each of the candidate layouts.

Alternatively, a sliding time window may be used to obtain the local maps in the map model, and then the local maps are input into the map neural network respectively.

Referring to fig. 3, a schematic diagram of a power consumption prediction model provided in the embodiment of the present application is shown. As shown in fig. 3, for the local graph corresponding to each time window, the node attribute (including the power consumption data and the temperature data at the previous time) of each node in the local graph is obtained, the node attribute and the weight on the edge in the local graph are input into the graph neural network, and then the output information of the graph neural network (GCN shown in fig. 3) is used as the input of the long-time and short-time memory network (LSTM shown in fig. 3). Wherein, the LSTM behind the GCN is the encoding LSTM, and the last LSTM is the decoding LSTM.

Performing graph convolution calculation on a local graph in a graph neural network, wherein a specific calculation formula is as follows:

in the formula:

i.e. the adjacency matrix of the graph model plus self-loops (each node starts from itself and points to itself again). The values in the adjacency matrix represent the connection conditions between elements, and the adjacency matrix in this scenario takes the weights on the edges into account when calculating. D is a transition matrix, H^(l)The characteristics of the nodes at the l layer; w^(l)The weight of the l layer is used for carrying out normalization processing on the matrix; σ is the activation function.

After the completion of the convolution operation, the updated signals for each chip may be time-sequenced into a sequence { X }¹,X²,…X^τinThe sequence is sent into the code LSTM,and obtaining the coding vector of each chip. The LSTM is an improved sequence modeling neural network provided for solving the problem of RNN gradient disappearance, and the modeling of the long-term dependence of a sequence is realized by introducing a door mechanism with multiple functions into a mold. The specific calculation process is as follows:

i^t＝tanh(W_ix^t+U_ih^t-1+b_i)；

f^t＝tanh(W_fx^t+U_fh^t-1+b_f)；

0^t＝tanh(W_ox^t+U_oh^t-1+b_o)；

c^t＝f^t o c^t+1+i^t o tanh(W_cx^t+U_ch^t-1+b_c)；

h^t＝0^t o tanh(c^t)；

in the formula: tan h is the activation function, i^tTo the input gate, f^tTo forget the door, c^tIs the cell state at the current time, h^tIs the final output. W_i、U_i、W_f、U_f、W_o、U_o、W_cAnd U_cTo learn parameters, b_i、b_f、b_o、b_cFor the bias vector, o represents the Hadamard product.

Encoding LSTM to obtain an output value h^τinAs the encoding vector of the chip, it is used to initialize the decoding LSTM. Decoding the LSTM and inputting the hidden state of each step into a multi-layer perception (MLP), wherein the final output result is power consumption prediction data after chip layout.

In the training process, a loss function is defined as a Mean Square Error (MSE), and a specific calculation method is as follows:

in the formula: tau is_ouFor predicting step sizeAnd k is a chip power consumption data value,

and predicting the power consumption data of the chip.

And S104, determining the candidate layout corresponding to the minimum value in the circuit power consumption corresponding to each of the plurality of candidate layouts as the target layout.

The wiring work on the board is started after the layout of the chips is completed. The wiring of the circuit board is currently done manually to a large extent by a professional. With the continuous improvement of the integration level of the circuit board devices, the number of the device pins is increased on a large scale, and manual wiring is completely completed manually by a designer, which has high requirements on the designer and takes time. A particle swarm based wiring algorithm is adopted to solve the problem of wiring among chipsets after layout is completed.

In one embodiment, after determining the target layout in S104, the method further includes: and iteratively searching a target wiring sequence meeting the target layout based on a particle swarm algorithm, wherein the positions of the particles in the particle swarm algorithm represent the wiring sequence of the chip on the target circuit board, and the particle speed is used for updating the positions of the particles.

Optionally, the step of each iterative search of the particle swarm algorithm includes:

calculating a local optimal solution and a global optimal solution of the current population; updating the particle position and the particle speed of each particle in the current population according to the local optimal solution and the global optimal solution of the current population to obtain the updated particle position and particle speed; if the current iteration times reach the preset times, determining a target wiring sequence according to the global optimal solution of the current population; and if the current iteration times do not reach the preset times, continuing the next iteration search according to the updated particle position and particle speed.

The Particle Swarm Optimization (PSO) algorithm is a Swarm intelligence Optimization algorithm and can well solve the problem of chip wiring sequence planning. In the iteration process of the basic PSO algorithm, the speed and position updating formula is as follows:

wherein:

represents the position of the particle i at time t;

the position of particle i at time t + 1. In chip wiring sequence planning, the positions of the particles represent the wiring sequence.

Which represents the velocity of the particle i at the time t, when t is 0,

where n is the number of chip sets,

is any integer between 1 and n, and

represents the velocity of particle i at time t + 1; ω is the non-negative inertial weight; c1 and c2 are non-negative learning factors; r1 and r2 are random numbers which are independent of each other and obey uniform distribution; p_bestFor the optimal position found by a particle at the current moment, i.e. the most reasonable wiring order found by a particle iteration to the current moment, G_bestThe best position found for the whole particle swarm at the current moment, i.e. the most reasonable wiring sequence found by all particles from iteration to the current moment.

The chip wiring sequence planning is an integer discretization problem, and the position and the speed of the basic particle swarm algorithm are real-value calculation and are not suitable for line chip wiring. Therefore, in the embodiment of the present application, the basic particle swarm algorithm is discretized, and the positions and the speeds of the particles and the updating operation and the operation among the particles are redefined.

Definition 1, particle position. The positions of the particles indicate the arrangement between chip numbers, and the position of the ith particle is X_i＝(x_i1,x_i2,…,x_id,…,x_in) Wherein x is_idE {1,2, …, n } is the chip number.

Definition 2, particle velocity. The arrangement between chip numbers is updated by the particle velocity. The velocity vector of the ith particle in the population is V_i＝(v_i1,v_i2,…,v_id,…,v_in) In which V is_idE {1,2, …, n }, which is the d-th dimension element of the velocity vector of particle i, and represents x in particle i_idThe corresponding speed. When V is_idWhen not equal to 0, it indicates chip x_idAt X_iThe arrangement position in (1) needs to be changed.

Definition 3, addition of particle position and velocity. Redefining

The sum of (1):

if it is

Then is at

Is found in

Equal elements

And exchange

In

And

the position of (a); if it is

Is not changed

In

The position of (a). After all operations are completed, the

Is assigned to

Define 4, subtraction of particle positions. Subtracting the two particle positions to generate a new velocity, let X₁＝(x₁₁，x₁₂,…,x_1d,…,x_1n)，X₂＝(x₂₁，x₂₂,…,x_2d,…,x_2n) Then define

Wherein V_iIs the updated speed. The solving method comprises the following steps: if x_1d＝x_2dThen V is_id0; if x_1d≠x_2dThen v is_id＝x_2d。

Definition 5, addition of particle velocity. Addition of redefined particle velocity

Wherein V_kThe solving method of (2) is as follows:

in the formula r₃Is distributed in [0, 1]]Random number of intervals.

Define 6, multiplication of particle velocity. Redefined particle velocity multiplication

c∈[0 1],V_jThe value of the expression is:

in the formula r₄Is distributed in [0, 1]]Random number of intervals.

Definition 7, particle position and velocity update. Redefine particle position and velocity updates:

wherein c1, c2, r1 and r2 are random numbers distributed in the interval of [0,1 ].

In the iterative optimization process of the PSO algorithm, other particles in the particle swarm can approach to a particle with the current optimal position, and when the particle finds that the current optimal position is not the global optimal position, namely the local optimal solution, the particle swarm can not continue to search in the solution space because of inertia, so that the algorithm is trapped in the local optimal position and premature occurs. Aiming at the problem, in the embodiment of the application, on the basis of a basic particle swarm algorithm, the particles are interfered and varied in the algorithm so as to improve the optimizing capability of the particles and avoid the premature phenomenon of the algorithm.

Firstly, generating different chaotic variables by using a chaotic search mechanism to interfere particles, and generating new particles so as to improve the search precision of an algorithm; then, mutation operation is carried out on the new particles with a certain probability by using a mutation mechanism, so that the algorithm is prevented from falling into local optimization too early.

(1) Particle interference based on chaotic search mechanism

The chaotic variables are generated by adopting logical mapping, different new solutions can be generated by each iteration of the chaos, and the generated chaotic variables are distributed in the whole solution space and have great randomness. The Logistic mapping function is defined as follows:

in the formula: r is 2 (i.e., two chaotic variables are randomly generated);

alternatively to this, the first and second parts may,

eta is 4 (when 3.5699456 is less than or equal to eta is less than or equal to 4, the chaotic character is obtained).

(2) Variation of microparticles

The general steps of the particle mutation procedure are:

solving variables by using two chaotic variables generated by a chaotic search mechanism, wherein a particle variation formula is as follows

Where n is the number of chips and "rounded up" is the symbol.

② finding out serial number in the particles

And the positions of the two chips are exchanged.

By calculating the population adaptive variance σ²Whether the algorithm is premature or not can be judged better. For a population with a population capacity of M, defining the variance of the population fitness

In the formula: f. of_iIs the fitness value of the ith particle; f. of_avgAnd the current population average fitness value is obtained.

f_i＝0.45N_nci+0.55N_ccl；

Wherein N is_nciFor number of times of path coincidence of wiring sequences, p_iWhen the wiring is simulated in the wiring sequence, the paths of the non-wiring chips in the wiring process are overlapped with the paths of the wiring once p times_i＝1。N_cclIs the wiring length. In the chip wiring sequence, the first wiring stub should be followedWiring is carried out according to the principle of wiring long wires; l is_iThe length comparison between two adjacent wiring devices in the wiring sequence is performed. If l_i＞l_i+1Then L is_iWhen the number of times of the wiring is not equal to 1, it is indicated that the wiring sequence has an unreasonable number of times of the wiring by summing the wiring sequences. The larger Nclc, the more unreasonable routing times of the routing sequence, indicating that the routing sequence is to be improved.

Population fitness variance σ²Can reflect the aggregation degree and the population diversity of the population, sigma²The larger, the greater the population diversity, σ²The smaller the population diversity. When sigma is²0, indicating that the diversity of the population disappears, and the population falls into the local optimum or finds the global optimum solution; when sigma is²<g_m(g_mA certain theoretical threshold), it means that the particle swarm falls into local optimum, and a perturbation variation operation should be performed.

Exemplarily, the chaos variation processing of the particles is added in each iterative search step of the particle swarm optimization, and the chaos variation processing specifically comprises the following steps:

step 1, initialization. Setting algorithm parameter omega_max、ω_minC1, c2, maximum number of iterations T_maxNumber of chaotic iterations G_cmaxGroup capacity M and theoretical threshold g_m. Wherein, ω is_minIs an initial weight, ω_maxIs the weight at maximum number of iterations.

Step 2, initializing a population speed V, a population position P and initializing population iteration times T₁＝1。

Step 3, calculating the fitness f of each particle in the population_iGroup average fitness value f_avgAnd the variance σ of population fitness²。

Step 4, judging the fitness variance sigma²And a theoretical threshold value g_mThe size of (2). If σ²<g_mTurning to the step 5; otherwise go to step 11.

And 5, selecting 0.2 xM particles with poor adaptability values from the initialized population as a new population N of chaotic variation, wherein the number of initialized chaotic iterations g is 1.

Step 6, randomly generating two variables

By using

To pair

And

respectively carrying out chaotic variation to generate chaotic variables

Step 7, order

Where n is the number of chips on the integrated circuit board.

Step 8, exchanging all particles in the population N

Position and calculate the fitness value of each particle in the new population

Step 9, comparing the fitness of the new particles

Value f of adaptability to original particle_iThe size of (2). If it is

Replacing the original particles with new particles; if it is

The original particles are used.

Step 10, let G be G +1, judge G and G_cmaxThe size of (2). If g is<G_cmaxThen the procedure returns to step 6, otherwise, the procedure goes to step 11.

Step 11, finding out the optimal value P of individuals in the population_bestAnd global optimal solution G_best。

Step 12, calculating the minimum fitness value f of the new population_minMaximum fitness value f_maxAnd the average fitness value f_avgAnd updating the inertia weight omega according to a formula.

The inertia weight value is to distinguish the emphasis on the global search and the local search. The update formula of the inertia weight is as follows:

where k is the current iteration number, T_maxIs the maximum number of iterations.

Step 13, according to the formula

And

the particle position and velocity are updated.

Step 14, determining k and T, wherein the number of times k of population iteration is k +1_maxIs a size of (c), if k<T_maxTurning to step 3; otherwise, go to step 15.

And step 15, outputting the optimal wiring sequence and the optimal fitness value, and finishing the algorithm.

Finally, according to the optimal wiring sequence and the adaptability value of the chip finally output (the position of the particle with the optimal adaptability value is the finally required wiring sequence, namely the last G_best) And carrying out chip wiring operation.

It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

Fig. 4 is a block diagram of a chip wiring device provided in the embodiment of the present application, which corresponds to the chip layout method described in the above embodiment, and only the relevant parts of the embodiment of the present application are shown for convenience of description.

Referring to fig. 4, the apparatus includes:

an obtaining unit 41 is used for obtaining a plurality of candidate layouts of the chip on the target circuit board.

A constructing unit 42, configured to construct a graph model corresponding to each of the multiple candidate layouts, where a node in the graph model is a chip on the target circuit board, an edge between two nodes in the graph model indicates that there is signal interaction between the chips represented by the two nodes, and a weight on the edge between the two nodes in the graph model is determined by a distance between the chips represented by the two nodes on the target circuit board.

And the predicting unit 43 is configured to predict the circuit power consumption corresponding to each of the multiple candidate layouts according to the graph model and a preset power consumption prediction model.

A layout unit 44, configured to determine, as a target layout, a candidate layout corresponding to a minimum value of the circuit power consumptions corresponding to the multiple candidate layouts.

Optionally, the obtaining unit 41 is further configured to:

randomly acquiring N initial solutions, wherein each initial solution represents a layout of a chip on the target circuit board, and N is a positive integer greater than 1; calculating target solutions corresponding to the N initial solutions according to a simulated annealing algorithm; determining the layout of the chip on the target circuit board represented by each target solution as one of the candidate layouts.

Optionally, the obtaining unit 41 is further configured to:

optimizing initial parameters of the simulated annealing algorithm based on a Bayesian optimization algorithm to obtain optimized initial parameters; and calculating target solutions corresponding to the N initial solutions according to the optimized initial parameters and the simulated annealing algorithm.

Optionally, the power consumption prediction model includes a graph neural network and a long-term and short-term memory network.

Accordingly, the prediction unit 43 is further configured to:

respectively inputting the graph models corresponding to the candidate layouts into the graph neural network to obtain first feature information of the candidate layouts, wherein the first feature information represents correlation features of chips in the candidate layouts on the space; inputting the first feature information of each of the multiple candidate layouts into the long-time memory network respectively to obtain second feature information of each of the multiple candidate layouts, wherein the second feature information represents the associated feature of each chip in the candidate layouts in terms of time; and predicting the circuit power consumption of each candidate layout according to the second characteristic information of each candidate layout.

Optionally, the apparatus 4 further comprises:

a wiring unit 45, configured to iteratively search a target wiring sequence satisfying a target layout based on a particle swarm algorithm after determining a candidate layout corresponding to a minimum value in circuit power consumption corresponding to each of the plurality of candidate layouts as the target layout, where a particle position in the particle swarm algorithm represents a wiring sequence of a chip on the target circuit board, and a particle speed is used to update the particle position.

Optionally, the wiring unit 45 is further configured to:

calculating the particle fitness of each particle in the current population;

It should be noted that, for the information interaction, execution process, and other contents between the above-mentioned devices/units, the specific functions and technical effects thereof are based on the same concept as those of the embodiment of the method of the present application, and specific reference may be made to the part of the embodiment of the method, which is not described herein again.

The chip wiring device shown in fig. 4 may be a software unit, a hardware unit, or a combination of software and hardware unit built in the existing terminal device, may be integrated into the terminal device as a separate pendant, or may exist as a separate terminal device.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

Fig. 5 is a schematic structural diagram of a terminal device according to an embodiment of the present application. As shown in fig. 5, the terminal device 5 of this embodiment includes: at least one processor 50 (only one shown in fig. 5), a memory 51, and a computer program 52 stored in the memory 51 and executable on the at least one processor 50, wherein the processor 50 implements the steps of any of the various chip placement method embodiments described above when executing the computer program 52.

The terminal device can be a desktop computer, a notebook, a palm computer, a cloud server and other computing devices. The terminal device may include, but is not limited to, a processor, a memory. Those skilled in the art will appreciate that fig. 5 is only an example of the terminal device 5, and does not constitute a limitation to the terminal device 5, and may include more or less components than those shown, or combine some components, or different components, such as an input-output device, a network access device, and the like.

The Processor 50 may be a Central Processing Unit (CPU), and the Processor 50 may be other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 51 may in some embodiments be an internal storage unit of the terminal device 5, such as a hard disk or a memory of the terminal device 5. The memory 51 may also be an external storage device of the terminal device 5 in other embodiments, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, which are provided on the terminal device 5. Further, the memory 51 may also include both an internal storage unit and an external storage device of the terminal device 5. The memory 51 is used for storing an operating system, an application program, a Boot Loader (Boot Loader), data, and other programs, such as program codes of the computer programs. The memory 51 may also be used to temporarily store data that has been output or is to be output.

The embodiments of the present application further provide a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the computer program implements the steps in the above-mentioned method embodiments.

The embodiments of the present application provide a computer program product, which when running on a terminal device, enables the terminal device to implement the steps in the above method embodiments when executed.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, all or part of the processes in the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium and can implement the steps of the embodiments of the methods described above when the computer program is executed by a processor. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer readable medium may include at least: any entity or device capable of carrying computer program code to an apparatus/terminal device, recording medium, computer Memory, Read-Only Memory (ROM), Random-Access Memory (RAM), electrical carrier wave signals, telecommunications signals, and software distribution medium. Such as a usb-disk, a removable hard disk, a magnetic or optical disk, etc. In certain jurisdictions, computer-readable media may not be an electrical carrier signal or a telecommunications signal in accordance with legislative and patent practice.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other ways. For example, the above-described embodiments of the apparatus/terminal device are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. A method for chip layout, comprising:

obtaining a plurality of candidate layouts of a chip on a target circuit board;

2. The chip placement method as claimed in claim 1, wherein said obtaining a plurality of candidate placements of chips on a target circuit board comprises:

3. The chip layout method according to claim 2, wherein said calculating a target solution corresponding to each of the N initial solutions according to a simulated annealing algorithm comprises:

4. The chip placement method of claim 1, wherein the power consumption prediction model comprises a graph neural network and an on-time and off-time memory network;

5. The chip layout method according to claim 1, wherein after determining, as the target layout, the candidate layout corresponding to the minimum value among the circuit power consumptions corresponding to the respective plural kinds of candidate layouts, the method further comprises:

6. The chip placement method according to claim 5, wherein said iteratively searching for a target wiring order satisfying said target placement based on a particle swarm algorithm comprises:

7. The chip layout method according to claim 6, wherein if the fitness variance is smaller than a preset threshold, performing chaotic variation processing on part of the particles in the current population to obtain a processing population, includes:

calculating the particle fitness of each particle in the current population;

8. A chip wiring device, comprising:

the calculation unit is used for determining the candidate layout corresponding to the minimum value in the circuit power consumption corresponding to the various candidate layouts as a target layout;

and the wiring unit is used for determining the target wiring sequence of the chips on the target circuit board according to the target layout.

9. A terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the method according to any of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1 to 7.