CN114528799B - Chip multi-terminal collaborative design method and system based on cloud platform - Google Patents
Chip multi-terminal collaborative design method and system based on cloud platform Download PDFInfo
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Abstract
The invention provides a cloud platform-based chip multi-terminal collaborative design method and a cloud platform-based chip multi-terminal collaborative design system, wherein the cloud platform-based chip multi-terminal collaborative design method comprises the following steps: distributing a design task for each chip design end, wherein each chip design end respectively lays out the modules according to the design task, and regularly uploads a layout result to the cloud platform; the cloud platform solves the optimal layout result based on the layout results of all the chip design ends received each time, calculates the re-layout cost index of the design task and the design capability index of each chip design end according to the layout result and the optimal layout result of each chip design end, and distributes the design task with high re-layout cost index to the chip design end with high design capability index when the next design task is distributed. The invention can reduce the design period of the complex chip, reduce the design error, improve the design efficiency of the chip and reduce the dependence degree of the chip design on the technical capability and the working experience.
Description
Technical Field
The invention relates to the field of big data analysis and chip design, in particular to a cloud platform-based chip multi-terminal collaborative design method and system.
Background
At present, the demand for chips is increasing, the complexity of the chips is increasing, and the design of the chips has a relatively high requirement. However, the existing chip design has many problems, the design period of a complex chip is long, the technical difficulty is high, and outstanding talents are rare, so that the design cost of the chip is high, and enterprises with the capability of designing the chip have few results.
The existing chip design needs a plurality of engineers to work in a division and cooperation mode, but the existing design process has the problems of low cooperation efficiency, more reworking times, uneven technical ability and work experience among the engineers and the like, and the efficiency of chip design is greatly reduced.
Disclosure of Invention
In order to solve the above problems, the present invention provides a cloud platform-based chip multi-end collaborative design method, which includes:
distributing a design task for each chip design end, wherein each chip design end carries out layout on the modules according to the design task, and regularly uploads a layout result to the cloud platform; the module comprises an IO unit, a macro unit and a standard unit placing unit; the layout result comprises a laid module and an un-laid module;
the cloud platform solves the optimal layout result based on the layout results of all the chip design ends received each time, calculates the re-layout cost index of the design task and the design capability index of each chip design end according to the layout result and the optimal layout result of each chip design end, and distributes the design task with high re-layout cost index to the chip design end with high design capability index when the next design task is distributed.
Obtaining a plurality of optimized layout results according to the layout results of all chip design ends, and using an automatic layout method to layout all the optimized layout results to obtain an optimal layout result; the method for acquiring the plurality of optimized layout results comprises the following steps:
step a, obtaining a pseudo-optimal layout result of the layout result of each chip design end, wherein each pseudo-optimal layout result corresponds to a first graph network; fusing the first graph networks corresponding to the layout result of each chip design end to obtain a second graph network, dividing the second graph network into sub-graph networks, wherein the number of the sub-graph networks is more than that of the first graph networks, and obtaining an optimized layout result based on the first graph networks and the sub-graph networks;
step b, deleting the modules existing in the optimized layout result from the layout result of the chip design end;
and c, taking the layout result of the chip design end obtained in the step b as the input of the step a, and iteratively executing the steps a and b until the layout result of each chip design end does not include a module.
Constructing an experience graph network based on the existing chip design big data, wherein a module in the experience graph network is connected with a module through a connecting edge, and the connecting edge corresponds to an edge weight; the method for each pseudo-optimal layout result to correspond to one first graph network comprises the following steps: for each module in the pseudo-optimal layout result, searching an experience module connected with the module based on the edge weight value in an experience graph network, wherein each experience module exists in the layout result of a certain chip design end; and fusing all the modules in the pseudo-optimal layout result and all the searched experience modules to obtain a first graph network, wherein the occurrence frequency of each experience module is counted during fusion, and the representation value of each module in the first graph network is the occurrence frequency of the module.
The method for obtaining the optimized layout result based on the first graph network and the subgraph network comprises the following steps: calculating the accuracy of each sub-graph network, wherein the greater the accuracy is, the more proper the modules in the sub-graph network are put together; calculating the first similarity between any first graph network and any subgraph network, and obtaining the characteristic point P based on the accuracy and the first similarity mn ＝(β m ,γ mn )，β m Indicating the accuracy of the mth sub-graph network, gamma mn The method comprises the steps of representing the first similarity of an mth sub-graph network and an nth first graph network, obtaining a plurality of first classes after carrying out first classification on feature points, carrying out second classification on the feature points in the first classes based on the corresponding first graph networks to obtain a plurality of second classes, calculating the importance degree of each second class, fusing the first graph networks and the sub-graph networks corresponding to all feature points in the second classes with the maximum importance degree, and then carrying out graph cutting processing to obtain an optimized layout result.
The second classification of the feature points in the first category specifically includes: if the first category only comprises one characteristic point, the characteristic point corresponds to a second category; if the number of the feature points in the first category is larger than 1, judging whether the sub-graph networks corresponding to the feature points are existed or not, if not, each feature point is corresponding to one second category, if so, the feature points corresponding to the same sub-graph network are classified into one set and the feature points in the set are classified for the second time based on the second similarity between the first graph networks corresponding to the feature points in the set, and the feature points corresponding to other different sub-graph networks are corresponding to different second categories respectively.
The method for calculating the importance of each first category comprises the following steps: calculating an average accuracy value based on the accuracy and the first similarity of all feature points in the category
The first mean similarity is
Then
Is the importance of the category in which, among other things,
the mean value of the second similarity between any two first graph networks in the first graph networks corresponding to all the feature points in the category; calculating the integrity of the first graph network corresponding to each feature point in the category,
is the average of the integrity; acquiring a first graph network corresponding to each feature point in the category, calculating the optimizability degree of the pseudo-optimal layout result corresponding to each first graph network,
is the average value of the optimizable degree corresponding to all the characteristic points in the category.
The method for calculating the integrity of the first graph network comprises the following steps: acquiring a pseudo-optimal layout result corresponding to the first graph network, wherein modules which belong to the first graph network and do not belong to the pseudo-optimal layout result form a module set, and calculating the integrity of the first graph network according to the ratio of the number of the modules in the module set to the number of the modules in the first graph network;
the calculation method of the optimization degree of the pseudo-optimal layout result corresponding to the first graph network comprises the following steps: the pseudo-optimal layout result corresponds to an initial graph network, the average value of the edge weights between any two modules after each module in the module set is fused into the initial graph network is the corresponding acceptable degree of the module, and when the corresponding acceptable degree of the module is smaller than the acceptable degree of the initial graph network, the corresponding acceptable degree value of the module is changed into 0; multiplying the acceptable degree corresponding to each module in the module set by the characteristic value of the module in the first graph network to obtain a numerical value, wherein the sum of all numerical values is the optimizable degree of the pseudo-optimal layout result.
And calculating a side weight value based on the shortest winding distance and the connection distance between the two modules, wherein the connection distance is the number of the standard units connected in series between the two modules, and if the number of the standard units connected in series between the two modules is 0, the connection distance is 1.
The calculation method of the re-layout cost index of the design task comprises the following steps: integrating the layout results of all chip design ends to obtain an initial layout, obtaining an optimal layout according to the optimal layout result, and sequentially inputting the initial layout and the optimal layout into a neural network to obtain two reasonable values; calculating the overlapping area of each module in the initial layout diagram, the voltage domain in the optimal layout diagram and the power line, and calculating the redistribution cost index of each module based on the difference value of the two reasonable values and the overlapping area; calculating a re-layout cost index of the design task according to the re-layout cost index of each module; the design task comprises a module or a pseudo-optimal layout result;
the method for calculating the design capability index of each chip design end comprises the following steps: and calculating the design capability index of the chip design end based on the acceptable degree, the optimizable degree and the re-layout cost index of the pseudo-optimal layout result obtained from the layout result of the chip design end.
In addition, the invention also provides a chip multi-end collaborative design system based on the cloud platform, which comprises:
a module layout subsystem: distributing a design task for each chip design end, wherein each chip design end respectively lays out the modules according to the design task, and regularly uploads a layout result to the cloud platform; the module comprises an IO unit, a macro unit and a standard unit placing unit; the layout result comprises a laid module and an un-laid module;
task reassignment subsystem: the cloud platform solves the optimal layout result based on the layout results of all the chip design ends received each time, calculates the re-layout cost index of the design task and the design capability index of each chip design end according to the layout result and the optimal layout result of each chip design end, and distributes the design task with high re-layout cost index to the chip design end with high design capability index when the next design task is distributed.
The invention has the beneficial effects that:
1. according to the invention, through multi-terminal collaborative design and big data analysis, the design cycle of a complex chip is reduced, the design error is reduced, the design efficiency of the chip is improved, and the degree of dependence of the chip design on the technical capability and the working experience is reduced.
2. According to the invention, by dynamically distributing the design tasks for each chip design end, each chip design end is reasonably utilized based on the capability of each chip design end, and the design efficiency is improved.
3. The invention firstly judges which modules are properly placed together, and then utilizes an automatic layout method to layout a plurality of modules, thereby reducing the workload of an automatic layout algorithm.
Drawings
FIG. 1 is a flow chart of the method of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, the following detailed description will be given with reference to the accompanying examples.
The main flow of the current chip design comprises INIT, floorplan, place, CTS, route, ECO and the like; the FloorPlan is one of important flows, is a top-level design step and has high requirements on technical capability and working experience, and comprises the processes of IO/Core Plan, macro Plan, block Plan, power Plan and the like. The invention only aims at the Floorpan flow to carry out multi-end collaborative design, and multi-end collaborative design of other flows is not considered. In addition, the invention is only directed to complex chips and is not suitable for simple chip design which can be completed by one engineer.
The method disclosed by the invention is mainly used for realizing the collaborative design of top-level design in chip design, the implementation flow of the method disclosed by the invention is shown in figure 1, tasks are dynamically allocated to each designed end through data processing and big data analysis of a cloud platform, and the design efficiency is improved.
The first embodiment is as follows:
the embodiment provides a chip multi-end collaborative design method based on a cloud platform, which comprises the following specific steps:
acquiring data files designed at the front end of a chip, wherein the data files reflect various parameters of a designed chip gate-level netlist circuit, acquiring the area of the chip and data of a corresponding standard cell, a Macro cell (Macro) and the like according to the parameters, then determining the number of engineers needing to participate in the design, wherein each engineer is a chip design end, when the tasks are distributed for the first time, the cloud platform distributes tasks for all chip design ends according to the chip gate-level netlist circuit, each chip design end respectively uploads a layout result to the cloud platform in a timing mode, the cloud platform verifies the integrity and effectiveness of the data after receiving the data of all chip design ends, and prompts are given for some obvious design errors, such as overlapping of Macro placement areas; in addition, the cloud platform integrates the layout result of each chip design end and reads the information of macro, IO, standard cell placement unit and Power of the layout result, including the position information, the number of occupied layers and the pin positions of macro cells, the position, the aspect ratio and the shape characteristics of standard cell placement units, the position and the functional action of IO cells, the Power domain position and the Power supply path of Power and the like. It should be noted that the present invention includes a plurality of IO cells, a plurality of macro cells, and one or more standard cell placement cells.
The cloud platform solves an optimal layout result based on the layout result of each chip design end received each time, specifically:
the layout result of each chip design end corresponds to a matching degree graph network, a module in the matching degree graph network is connected with the module, a connecting side corresponds to a side weight value, it needs to be noted that in the embodiment, IO units, macro units and standard unit placing units which can change positions are collectively called as the module, wherein a pair of IO units and macro units which have a connection relation are obtained, for each pin of the macro, the shortest winding distance and the connection distance between the pin and the IO unit are calculated, the matching value corresponding to the pin is obtained based on the shortest winding distance and the connection distance, and then the sum of the matching values corresponding to all the pins is the matching degree between the IO units and the macro; the matching degree of macro and macro, IO and IO can be calculated in the same way; and if the number of the standard cells connected in series between the two modules is 0, the connection distance is 1.
The specific matching value obtained based on the shortest winding distance and the connection distance and corresponding to the pin is as follows: the product of the shortest winding distance and the connection distance is x, then e -x Is a matching value, e is a natural constant; the matching degree is normalized to be the edge weight.
The solving method of the optimal layout result comprises the following steps:
step a, a layout result of each chip design end comprises a laid module and a non-laid module, a pseudo-optimal layout result is obtained based on the layout result of each chip design end, specifically, some module areas with the maximum matching degree are obtained in a matching degree graph network corresponding to each chip design end, the modules are called pseudo-optimal layout results, and the modules in the pseudo-optimal layout results only indicate that the modules are placed together with the best matching degree, namely are suitable for being placed together, and do not represent the best placement positions of the modules.
The specific method for acquiring the pseudo-optimal layout result comprises the following steps: for each matching degree graph network, setting an edge weight value with the edge weight value smaller than a first threshold value to be 0 in the matching degree graph network, then carrying out graph cutting processing on the matching degree graph network to obtain a plurality of sub-matching degree graph networks, eliminating the sub-matching degree graph networks with the number of modules being 1, and carrying out the following processing on each remaining sub-matching degree graph network: obtaining the degree of each module in the sub-matching degree graph network, solving the mean value of the degrees of all modules in the sub-matching degree graph network, and if the solved mean value is smaller than a second threshold value, rejecting the sub-matching degree graph network; each sub-matching degree graph network which is finally remained after the processing is a pseudo-optimal layout result; the degree of each module is the sum of the edge weights of all the connecting edges connected with the module.
Each pseudo-optimal layout result corresponds to a first graph network, and the method for acquiring the first graph network comprises the following steps:
firstly, constructing an experience graph network based on the existing chip design, wherein a module in the experience graph network is connected with a module through a connecting edge, and the connecting edge corresponds to an edge weight; the construction method of the experience graph network comprises the following steps: obtaining a plurality of designed chips, obtaining a pseudo-optimal layout result based on each chip, wherein each pseudo-optimal layout result corresponds to one matching degree graph network, the matching degree graph networks corresponding to each chip are fused, if the same connecting edges exist, the same modules are combined into one module, the connecting edges are combined, the edge weights corresponding to the same connecting edges are added to be used as the edge weights of the combined connecting edges, and the experience graph network is obtained after fusion; in the empirical graph network, there may be multiple paths between any two modules, and the edge weight between any two modules is the product of the edge weights of the corresponding connection edges of the shortest path between two modules.
Secondly, for each pseudo-optimal layout result, all modules in the pseudo-optimal layout result are obtained, for each module in the pseudo-optimal layout result, K experience modules connected with the laid module are searched in an experience graph network according to the sequence of edge weights from large to small, and each experience module in the K experience modules exists in the layout result of a certain chip design end; all modules in the pseudo-optimal layout result and K experience modules respectively corresponding to each module in the pseudo-optimal layout result are fused to obtain a first graph network, the occurrence frequency of each experience module is counted during fusion, the representation value of each module in the first graph network is the occurrence frequency of the module, the edge weight values among the modules are determined according to the experience graph network, and the value of K in the embodiment is 6.
Thus, a plurality of first graph networks can be obtained.
And fusing the first graph networks corresponding to the pseudo-optimal layout result to obtain a second graph network, dividing the second graph network into sub-graph networks, wherein the number of the sub-graph networks is more than that of the first graph networks, and the sub-graph networks are obtained by the following steps: and respectively taking each module in the second graph network as a center, searching L modules connected with the module in the second graph network according to the order of the edge weight values from large to small for each module, and forming a sub-graph network by the module and the selected L modules, wherein the L value in the embodiment is 9.
Obtaining an optimized layout result based on the first graph network and the subgraph network:
calculating the accuracy of each sub-graph network: the product of the number of modules in the sub-graph network and the acceptable degree and the smooth degree of the sub-graph network is the accuracy of the sub-graph network; the method for acquiring the smoothness degree comprises the following steps: obtaining a Laplace matrix of a sub-graph network, obtaining a characteristic value of the Laplace matrix, and constructing a first vector U1 according to the obtained characteristic value; performing Fourier transform on the sub-graph network, specifically, forming a second vector by the occurrence times of each module in the sub-graph network, performing orthogonal decomposition on the second vector by taking a characteristic vector of a Laplace matrix as a base vector to obtain a third vector U2, wherein elements in the third vector are the projection lengths of the second vector on each characteristic vector, and the dimensions of the first vector and the third vector are the same; the degree of smoothing is then:
wherein T is the vector dimension, U1 t 、U2 t The t-th elements in the vectors U1 and U2, respectively.
The accuracy characterizes whether all modules in the subgraph network are optimally and most appropriately arranged together, and the more accuracy indicates that the modules are more appropriately arranged together, i.e. the modules are more desirably arranged together.
The smoothness represents the difference between topological characteristics and occurrence times of all modules in the sub-graph network, and the smaller the smoothness is, the larger the difference between the local layouts of the modules is when the modules are laid out together is, and the less the modules are laid out together; the larger the smoothness is, the smaller the difference between the local layouts of the modules is when the modules are laid out together, and the better the layout result is.
Calculating the first similarity of any first graph network and any subgraph network: let any first graph network be E, any sub-graph network be F, and modules existing in E, F form set V 1 Set V of 1 The sum of the occurrence times of all the modules in the series is compared with the sum of the occurrence times of all the modules in E, F to obtain a ratio I; set V is removed in E, F 1 Get the set V after the module in 2 、V 3 In sets V, respectively 2 、V 3 Selecting one module, searching a shortest path between the two modules in the empirical graph network based on the size of the edge weight, and obtaining the product of the edge weights corresponding to the shortest path as the edge weight between the two modules; because the edge weights between the two modules are different due to the difference of the selected modules, an edge weight set can be obtained, the edge weights in the edge weight set are sequenced from large to small, the average value of the first H edge weights is taken to obtain a value J, and the first similarity is I x J.
Obtaining a plurality of feature points P based on accuracy and a first similarity mn ＝(β m ,γ mn )，β m Indicating the accuracy of the mth sub-graph network, gamma mn Representing the first similarity between the mth sub-graph network and the nth first graph network, carrying out first classification on the feature points by using a mean shift clustering algorithm to obtain a plurality of first classes, carrying out second classification on the feature points in the first classes based on the first graph network corresponding to the feature points in the first classes to obtain a plurality of second classes, specifically: if the first category only comprises one characteristic point, the characteristic point corresponds to a second category; if the number of the feature points in the first category is more than 1, judging whether the feature points correspond to the same sub-graph network or not, if not, each feature point corresponds to a second category, and if so, corresponding to the same sub-graph networkThe feature points are classified into one set, the feature points in the set are classified for the second time based on the second similarity between the first graph networks corresponding to the feature points in the set, and the feature points corresponding to other different sub-graph networks respectively correspond to different second classes. Note that the method of calculating the second similarity is the same as the method of calculating the first similarity.
Calculating the importance of each second category, for each second category:
calculating an average accuracy value based on the accuracy and the first similarity of all feature points in the category
Mean value of first similarity
Obtain the importance of the category
Wherein:
the integrity of the first graph network corresponding to each feature point in the category is calculated,
the average value of the integrity, wherein the method for calculating the integrity of the first graph network comprises the following steps: obtaining a pseudo-optimal layout result corresponding to the first graph network, wherein modules which belong to the first graph network and do not belong to the pseudo-optimal layout result form a module set, and the ratio of the number of the modules in the module set to the number of the modules in the first graph network is y, e -y Is the integrity of the first graph network;
obtaining the first graph networks corresponding to all the feature points in the category, and calculating the optimization of the pseudo-optimal layout result corresponding to each first graph networkThe degree of the neutralization is determined by the degree of neutralization,
the method is the average value of the optimizability degrees corresponding to all feature points in the category, wherein the optimizability degree of the pseudo-optimal layout result corresponding to the first graph network is calculated by the following steps: the pseudo-optimal layout result corresponds to an initial graph network, the initial graph network is obtained based on a matching degree graph network corresponding to a design end where the pseudo-optimal layout result is located, specifically, the matching degree graph network can be obtained by graph cutting, the initial graph network comprises all modules in the pseudo-optimal layout result, the average value of edge weights between any two modules after each module in a module set is respectively fused into the initial graph network is an acceptable degree corresponding to the module, and when the acceptable degree corresponding to the module is smaller than that of the initial graph network, the acceptable degree value corresponding to the module becomes 0; and multiplying the acceptable degree corresponding to each module in the module set by the characteristic value of the module in the first graph network to obtain a numerical value, wherein the sum of all numerical values is the optimizable degree of the pseudo-optimal layout result.
It should be noted that the acceptable degree of the sub-graph network and the initial graph network is the average value of the edge weights between any two modules in the sub-graph network and the initial graph network, respectively, and the acceptable degree of the initial graph network is the acceptable degree of the corresponding pseudo-optimal layout result.
The second categories are sorted according to the importance degrees of the second categories, the second categories with similar importance degrees are merged to obtain the second category with the maximum importance degree value, the first graph network and the sub-graph network corresponding to all feature points in the second category with the maximum importance degree are merged and then graph cutting processing is carried out to obtain an optimized layout result, and the merging method comprises the following steps: the same modules are combined into one, the edge weights corresponding to the same connecting edges are added and then normalized, the fused network obtained after fusion is subjected to image cutting processing, a plurality of sub-fused networks are obtained, the sub-fused networks with small number of modules are removed, and each remaining sub-fused network corresponds to an optimized layout result.
It should be noted that the importance degree of the new second category obtained after merging the second categories with similar importance degrees is the average of the importance degrees corresponding to all the merged second categories. The specific pattern cutting method is well known, and the detailed description of the invention is omitted.
Step b, deleting the modules existing in the optimized layout result from the layout result of the chip design end;
and c, taking the layout result of the chip design end obtained in the step b as the input of the step a, and iteratively executing the steps a and b until the layout result of each chip design end does not include a module.
Thus, a plurality of optimized layout results can be obtained.
The invention can obtain a plurality of optimized layout results based on the pseudo-optimal layout result, gives the optimal layout suggestion while disturbing the original layout as much as possible, assists the chip design end to complete the chip design, and enables the chip design end with insufficient design capability to complete the chip layout.
The obtained optimized layout result indicates that the modules in the optimized layout result are properly placed together, and an automatic layout method is also needed to be used for laying out the optimized layout result and the modules in each optimized layout result to obtain the optimal layout result.
Calculating a re-layout cost index of the design task and a design capability index of each chip design end according to the layout result and the optimal layout result of each chip design end, and distributing the design task with high re-layout cost index to the chip design end with high design capability index when the next design task is distributed; the calculation method of the re-layout cost index of the design task comprises the following steps:
integrating the layout result of each chip design end to obtain an initial layout, obtaining an optimal layout according to the optimal layout result, sequentially inputting the initial layout and the optimal layout into a neural network to obtain two reasonable values, subtracting the reasonable value corresponding to the initial layout from the reasonable value corresponding to the optimal layout to obtain a difference value A, assigning the difference value to be 0 when the obtained difference value is less than 0, wherein the greater the difference value is, the higher the rationality representing the optimal layout is than that of the initial layout, namely, the higher the cost paid by re-layout is, the higher the difference value is(ii) a Calculating the overlapping area B of each module in the initial layout diagram and the voltage domain and the power line in the optimal layout diagram, wherein the smaller the overlapping area is, the longer the time spent for rearranging the initial voltage source and the initial power line is, the higher the rearranging cost is; it should be noted that the voltage source and the power line are also laid out by using an automatic layout method; calculating a rearrangement cost index of each module based on the difference value and the overlapping area, wherein the rearrangement cost index of each module is e A-B (ii) a And calculating the re-layout cost index of the design task according to the re-layout cost index of each module, wherein the design task comprises modules or a pseudo-optimal layout result, and the re-layout cost index corresponding to the pseudo-optimal layout result is the mean value of the re-layout cost index of each module in the pseudo-optimal layout result.
The difference value A is a scaling coefficient, so that the difficulty degree of rearrangement can be integrally evaluated, and the rearrangement cost index of each module is more reliable.
The concrete acquisition method of the reasonable value comprises the following steps: and obtaining a binary initial layout mask and an optimal layout mask according to the initial layout map and the optimal layout map, wherein the area of the module in the mask is white, and the other areas are black, and sequentially inputting the initial layout mask and the optimal layout mask into the DNN network to obtain two reasonable values.
The method for calculating the design capability index of each chip design end comprises the following steps: calculating the design capability index of the chip design end based on the acceptable degree, the optimizable degree and the re-layout cost index of all the pseudo-optimal layout results obtained from the layout result of the chip design end; specifically, the method comprises the following steps: obtaining a pseudo-optimal layout result according to the layout result of each chip design end, obtaining the acceptable degree and the optimized degree corresponding to the pseudo-optimal layout result based on each pseudo-optimal layout result, and obtaining the mean value c of the acceptable degrees of all the pseudo-optimal layout results corresponding to each chip design end 1 Average value c of the optimizable degree 2 And the mean value c of the redistribution cost indexes of all the pseudo-optimal layout results corresponding to each chip design end 3 Then the chip design end has a design capability index of
Thus, a redistribution cost index and a design capability index are obtained.
And distributing the design tasks with high redistribution cost indexes to the chip design ends with high design capability indexes when the next design task is distributed, namely distributing the design tasks with high difficulty to the chip design ends with high design capability indexes.
Based on the same inventive concept as the method embodiment, the embodiment of the present invention further provides a cloud platform-based chip multi-port collaborative design system, which includes:
a module layout subsystem: distributing a design task for each chip design end, wherein each chip design end respectively lays out the modules according to the design task, and regularly uploads a layout result to the cloud platform; the module comprises an IO unit, a macro unit and a standard unit placing unit; the layout result comprises a laid module and an un-laid module;
task reassignment subsystem: the cloud platform solves the optimal layout result based on the layout results of all the chip design ends received each time, calculates the re-layout cost index of the design task and the design capability index of each chip design end according to the layout result and the optimal layout result of each chip design end, and distributes the design task with high re-layout cost index to the chip design end with high design capability index when the next design task is distributed.
As for the system embodiment, since it is basically similar to the method embodiment, it is relatively simple to describe, and the relevant points can be referred to the partial description of the method embodiment; the foregoing is intended to provide those skilled in the art with a better understanding of the invention, and is not intended to limit the invention to the particular forms disclosed, since modifications and variations can be made without departing from the spirit and scope of the invention.
Claims (2)
1. A chip multi-end collaborative design method based on a cloud platform is characterized by comprising the following steps:
distributing a design task for each chip design end, wherein each chip design end respectively lays out the modules according to the design task, and regularly uploads a layout result to the cloud platform; the module comprises an IO unit, a macro unit and a standard unit placing unit; the layout result comprises a laid module and an un-laid module;
the cloud platform solves an optimal layout result based on the layout results of all the chip design ends received each time, calculates a re-layout cost index of the design task and a design capability index of each chip design end according to the layout result and the optimal layout result of each chip design end, and allocates the design task with a high re-layout cost index to the chip design end with a high design capability index when the next design task is allocated;
obtaining a plurality of optimized layout results according to the layout results of all chip design ends, and performing layout on all the optimized layout results by using an automatic layout method to obtain an optimal layout result; the method for acquiring the plurality of optimized layout results comprises the following steps:
step a, obtaining a pseudo-optimal layout result of the layout result of each chip design end, wherein each pseudo-optimal layout result corresponds to a first graph network; fusing the first graph networks corresponding to the layout result of each chip design end to obtain a second graph network, dividing the second graph network into sub-graph networks, wherein the number of the sub-graph networks is more than that of the first graph networks, and obtaining an optimized layout result based on the first graph networks and the sub-graph networks;
step b, deleting the modules existing in the optimized layout result from the layout result of the chip design end;
step c, the layout result of the chip design end obtained in the step b is used as the input of the step a, and the steps a and b are executed in an iterative mode until the layout result of each chip design end does not comprise a module;
constructing an experience graph network based on the existing chip design big data, wherein a module in the experience graph network is connected with a module through a connecting edge, and the connecting edge corresponds to an edge weight; the method for each pseudo-optimal layout result to correspond to one first graph network comprises the following steps: for each module in the pseudo-optimal layout result, searching an experience module connected with the module based on the edge weight value in an experience graph network, wherein each experience module exists in the layout result of a certain chip design end; fusing all modules in the pseudo-optimal layout result and all searched experience modules to obtain a first graph network, and counting the occurrence times of each experience module during fusion, wherein the representation value of each module in the first graph network is the occurrence times of the module;
the method for obtaining the optimized layout result based on the first graph network and the subgraph network comprises the following steps: calculating the accuracy of each sub-graph network, wherein the greater the accuracy is, the more appropriate the modules in the sub-graph network are put together; calculating the first similarity between any first graph network and any subgraph network, and obtaining the characteristic point P based on the accuracy and the first similarity mn ＝(β m ,γ mn )，β m Indicating the accuracy of the mth sub-graph network, gamma mn Representing the first similarity between the mth sub-graph network and the nth first graph network, carrying out first classification on the feature points to obtain a plurality of first classes, carrying out second classification on the feature points in the first classes based on the corresponding first graph networks to obtain a plurality of second classes, calculating the importance degree of each second class, fusing the first graph networks and the sub-graph networks corresponding to all the feature points in the second classes with the maximum importance degree, and carrying out graph cutting processing to obtain an optimized layout result;
the second classification of the feature points in the first category specifically includes: if the first category only comprises one characteristic point, the characteristic point corresponds to a second category; if the number of the feature points in the first category is larger than 1, judging whether the feature points correspond to the same sub-graph network or not, if not, judging that each feature point corresponds to one second category respectively, if so, classifying the feature points corresponding to the same sub-graph network into one set and carrying out secondary classification on the feature points in the set based on a second similarity between the first graph networks corresponding to the feature points in the set, and otherwise, respectively corresponding to different sub-graph networks, wherein the feature points in the first category correspond to different second categories;
the method for calculating the importance of each first category comprises the following steps: calculating an average accuracy value based on the accuracy and the first similarity of all feature points in the category
The first mean similarity is
Then the
Is the importance of the category in which, among other things,
the mean value of the second similarity between any two first graph networks in the first graph networks corresponding to all the feature points in the category; the integrity of the first graph network corresponding to each feature point in the category is calculated,
is the average of the integrity; acquiring a first graph network corresponding to each feature point in the category, calculating the optimizability degree of the pseudo-optimal layout result corresponding to each first graph network,
the average value of the optimizable degree corresponding to all the feature points in the category;
the method for calculating the integrity of the first graph network comprises the following steps: acquiring a pseudo-optimal layout result corresponding to the first graph network, wherein modules which belong to the first graph network and do not belong to the pseudo-optimal layout result form a module set, and calculating the integrity of the first graph network according to the ratio of the number of the modules in the module set to the number of the modules in the first graph network;
the calculation method of the optimization degree of the pseudo-optimal layout result corresponding to the first graph network comprises the following steps: the pseudo-optimal layout result corresponds to an initial graph network, the average value of the edge weights between any two modules after each module in the module set is fused into the initial graph network is the corresponding acceptable degree of the module, and when the corresponding acceptable degree of the module is smaller than the acceptable degree of the initial graph network, the corresponding acceptable degree value of the module is changed into 0; multiplying the acceptable degree corresponding to each module in the module set by the characteristic value of the module in the first graph network to obtain a numerical value, wherein the sum of all the numerical values is the optimizable degree of the pseudo-optimal layout result;
calculating a side weight value based on the shortest winding distance and a connection distance between the two modules, wherein the connection distance is the number of the standard units connected in series between the two modules, and if the number of the standard units connected in series between the two modules is 0, the connection distance is 1;
the calculation method of the re-layout cost index of the design task comprises the following steps: integrating the layout results of all chip design ends to obtain an initial layout, obtaining an optimal layout according to the optimal layout result, and sequentially inputting the initial layout and the optimal layout into a neural network to obtain two reasonable values; calculating the overlapping area of each module in the initial layout diagram and the voltage domain and the power line in the optimal layout diagram, and calculating the redistribution cost index of each module based on the difference value and the overlapping area of the two reasonable values; calculating a re-layout cost index of the design task according to the re-layout cost index of each module; the design task comprises a module or a pseudo-optimal layout result;
the method for calculating the design capability index of each chip design end comprises the following steps: and calculating the design capability index of the chip design end based on the acceptable degree, the optimizable degree and the re-layout cost index of the pseudo-optimal layout result obtained from the layout result of the chip design end.
2. A chip multi-end collaborative design system based on a cloud platform is characterized by comprising:
a module layout subsystem: distributing a design task for each chip design end, wherein each chip design end respectively lays out the modules according to the design task, and regularly uploads a layout result to the cloud platform; the module comprises an IO unit, a macro unit and a standard unit placing unit; the layout result comprises a laid module and an un-laid module;
the task redistribution subsystem: the cloud platform solves an optimal layout result based on the layout results of all the chip design ends received each time, calculates a re-layout cost index of the design task and a design capability index of each chip design end according to the layout result and the optimal layout result of each chip design end, and allocates the design task with a high re-layout cost index to the chip design end with a high design capability index when the next design task is allocated;
obtaining a plurality of optimized layout results according to the layout results of all chip design ends, and performing layout on all the optimized layout results by using an automatic layout method to obtain an optimal layout result; the method for acquiring the plurality of optimized layout results comprises the following steps:
step a, obtaining a pseudo-optimal layout result of the layout result of each chip design end, wherein each pseudo-optimal layout result corresponds to a first graph network; fusing the first graph networks corresponding to the layout result of each chip design end to obtain a second graph network, dividing the second graph network into sub-graph networks, wherein the number of the sub-graph networks is more than that of the first graph networks, and obtaining an optimized layout result based on the first graph networks and the sub-graph networks;
step b, deleting the modules existing in the optimized layout result from the layout result of the chip design end;
step c, the layout result of the chip design end obtained in the step b is used as the input of the step a, and the steps a and b are executed in an iterative mode until the layout result of each chip design end does not comprise a module;
constructing an experience graph network based on the existing chip design big data, wherein a module in the experience graph network is connected with a module through a connecting edge, and the connecting edge corresponds to an edge weight; the method for each pseudo-optimal layout result to correspond to one first graph network comprises the following steps: for each module in the pseudo-optimal layout result, searching an experience module connected with the module based on the edge weight value in an experience graph network, wherein each experience module exists in the layout result of a certain chip design end; fusing all modules in the pseudo-optimal layout result and all searched experience modules to obtain a first graph network, and counting the occurrence times of each experience module during fusion, wherein the representation value of each module in the first graph network is the occurrence times of the module;
the method for obtaining the optimized layout result based on the first graph network and the subgraph network comprises the following steps: calculating the accuracy of each sub-graph network, wherein the greater the accuracy is, the more proper the modules in the sub-graph network are put together; calculating the first similarity between any first graph network and any subgraph network, and obtaining the characteristic point P based on the accuracy and the first similarity mn ＝(β m ,γ mn )，β m Indicating the accuracy of the mth sub-graph network, gamma mn Representing the first similarity between the mth sub-graph network and the nth first graph network, carrying out first classification on the feature points to obtain a plurality of first classes, carrying out second classification on the feature points in the first classes based on the corresponding first graph networks to obtain a plurality of second classes, calculating the importance degree of each second class, fusing the first graph networks and the sub-graph networks corresponding to all the feature points in the second classes with the maximum importance degree, and carrying out graph cutting processing to obtain an optimized layout result;
the second classification of the feature points in the first category specifically includes: if the first category only comprises one characteristic point, the characteristic point corresponds to a second category; if the number of the feature points in the first category is more than 1, judging whether the feature points correspond to the same sub-graph network or not, if not, each feature point corresponds to a second category, if so, classifying the feature points corresponding to the same sub-graph network into a set and performing secondary classification on the feature points in the set based on a second similarity between the first graph networks corresponding to the feature points in the set, and enabling the feature points corresponding to different sub-graph networks to correspond to different second categories respectively;
the method for calculating the importance of each first category comprises the following steps: calculating an average accuracy value based on the accuracy and the first similarity of all feature points in the category
First degree of similarityMean value of
Then
To the extent of importance of the category, wherein,
the mean value of the second similarity between any two first graph networks in the first graph networks corresponding to all the feature points in the category; calculating the integrity of the first graph network corresponding to each feature point in the category,
is the average of the integrity; acquiring a first graph network corresponding to each feature point in the category, calculating the optimizability degree of the pseudo-optimal layout result corresponding to each first graph network,
the average value of the optimizable degrees corresponding to all the feature points in the category;
the method for calculating the integrity of the first graph network comprises the following steps: acquiring a pseudo-optimal layout result corresponding to the first graph network, wherein modules which belong to the first graph network and do not belong to the pseudo-optimal layout result form a module set, and calculating the integrity of the first graph network according to the ratio of the number of the modules in the module set to the number of the modules in the first graph network;
the calculation method of the optimization degree of the pseudo-optimal layout result corresponding to the first graph network comprises the following steps: the pseudo-optimal layout result corresponds to an initial graph network, the average value of the edge weight between any two modules after each module in the module set is merged into the initial graph network is the corresponding acceptable degree of the module, and when the corresponding acceptable degree of the module is smaller than the acceptable degree of the initial graph network, the corresponding acceptable degree value of the module is changed into 0; multiplying the acceptable degree corresponding to each module in the module set by the characteristic value of the module in the first graph network to obtain a numerical value, wherein the sum of all the numerical values is the optimizable degree of the pseudo-optimal layout result;
calculating a side weight value based on the shortest winding distance and the connection distance between the two modules, wherein the connection distance is the number of the standard units connected in series between the two modules, and if the number of the standard units connected in series between the two modules is 0, the connection distance is 1;
the calculation method of the re-layout cost index of the design task comprises the following steps: integrating the layout results of all chip design ends to obtain an initial layout, obtaining an optimal layout according to the optimal layout result, and sequentially inputting the initial layout and the optimal layout into a neural network to obtain two reasonable values; calculating the overlapping area of each module in the initial layout diagram, the voltage domain in the optimal layout diagram and the power line, and calculating the redistribution cost index of each module based on the difference value of the two reasonable values and the overlapping area; calculating a re-layout cost index of the design task according to the re-layout cost index of each module; the design task comprises a module or a pseudo-optimal layout result;
the method for calculating the design capability index of each chip design end comprises the following steps: and calculating the design capability index of the chip design end based on the acceptable degree, the optimizable degree and the re-layout cost index of the pseudo-optimal layout result obtained from the layout result of the chip design end.
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