CN115993943A - Memory characterization method, chip design method, medium and device - Google Patents
Memory characterization method, chip design method, medium and device Download PDFInfo
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Abstract
Embodiments of the present disclosure provide a memory characterization method, a chip design method, a storage medium, and an electronic device. The memory characterization method includes: determining initial time sequence power consumption characteristic data corresponding to a memory according to preset temperature, voltage and process deviation conditions; determining a corresponding feature prediction model according to the relation between the initial time sequence power consumption feature data and the basic feature data of the memory; determining corresponding target time sequence power consumption characteristic data under the conditions of target temperature, voltage and process deviation according to the characteristic prediction model; and determining a memory characteristic data packet according to the target time sequence power consumption characteristic data and the initial time sequence power consumption characteristic data. The technical scheme of the embodiment of the disclosure can improve the accuracy of the memory characterization and reduce the time for the characterization.
Description
Technical Field
Embodiments of the present disclosure relate to the field of integrated circuit technology, and more particularly, to a memory characterization method, a chip design method, a storage medium, and an electronic device.
Background
This section is intended to provide a background or context to the embodiments of the disclosure recited in the claims. The description herein is not admitted to be prior art by inclusion in this section.
Memory characterization (Memory Characterization) is a very important element in SRAM (Static Random-Access Memory) compiler design, and the time required for characterization is about one third of the SRAM compiler design period.
With the continuous progress of the process size, the deviation of the process parameters in the process manufacture is more and more serious, so that the accuracy requirement of the memory characterization is higher and longer.
Disclosure of Invention
For this reason, a new memory characterization method is highly needed to improve the accuracy of memory characterization and reduce the time spent on characterization.
In this context, embodiments of the present disclosure desire to provide a memory characterization method, a chip design method, a storage medium, and an electronic device.
In a first aspect of embodiments of the present disclosure, there is provided a memory characterization method, comprising: determining initial time sequence power consumption characteristic data corresponding to a memory according to preset temperature, voltage and process deviation conditions; determining a corresponding feature prediction model according to the relation between the initial time sequence power consumption feature data and the basic feature data of the memory; determining corresponding target time sequence power consumption characteristic data under the conditions of target temperature, voltage and process deviation according to the characteristic prediction model; and determining a memory characteristic data packet according to the target time sequence power consumption characteristic data and the initial time sequence power consumption characteristic data.
In some embodiments of the disclosure, the determining the corresponding feature prediction model according to the relationship between the initial time-series power consumption feature data and the basic feature data of the memory includes: and determining a feature prediction model according to the difference between the feature data contained in the initial time sequence power consumption feature data and the feature data contained in the basic feature data.
In some embodiments of the disclosure, the determining the feature prediction model according to the dissimilarity between the feature data included in the initial time-series power consumption feature data and the feature data included in the base feature data includes: and determining a first prediction model as the characteristic prediction model when the characteristic data contained in the initial time sequence power consumption characteristic data is only part or all of the basic characteristic data.
In some embodiments of the present disclosure, the first predictive model includes errors in timing power consumption parameters and temperature, voltage, and process bias parameters, and a first penalty term; wherein the first penalty term is the product of the penalty factor and the parameter to be estimated.
In some embodiments of the disclosure, the determining the feature prediction model according to the dissimilarity between the feature data included in the initial time-series power consumption feature data and the feature data included in the base feature data includes: and determining a second type of prediction model as the feature prediction model when the initial time sequence power consumption feature data not only comprises the basic feature data but also comprises the extended feature data.
In some embodiments of the present disclosure, the second predictive model includes errors in timing power consumption parameters and temperature, voltage, and process bias parameters, and a second penalty term; wherein the second penalty term is the product of the penalty factor and the square of the parameter to be estimated.
In some embodiments of the present disclosure, the penalty factor is a sum of a timing parameter and a normalized power consumption parameter in the initial timing power consumption characteristic data.
In some embodiments of the present disclosure, the error of the timing power consumption parameter from the temperature, voltage, and process bias parameters includes: the square of the linear difference of the time-series power consumption parameter and the temperature, voltage and process deviation parameter.
In some embodiments of the present disclosure, the base characteristic data includes: the clock rising edge width, the clock falling edge width, the chip select signal setup time, the chip select signal hold time, the write enable signal setup time, the write enable signal hold time, the address setup time, the address hold time, the data setup time, the data hold time, the read clock frequency, the write clock frequency, the data read delay, the output data hold time, the write enable setup time by bit, the write enable hold time by bit, the power leakage when the clock is varied, the power leakage when the clock is stationary, the read cycle dynamic power consumption, and at least a portion of the write cycle dynamic power consumption.
In a second aspect of embodiments of the present disclosure, there is provided a chip design method, including: obtaining memory characteristic data packets corresponding to a plurality of memories according to the memory characteristic method; and determining a target memory corresponding to the chip according to the memory characteristic data packets and the target performance characteristics of the chip.
In a third aspect of the disclosed embodiments, a storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the above-described method.
In a second aspect of embodiments of the present disclosure, there is provided an electronic device, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the above-described method via execution of the executable instructions.
According to the memory characterization method of the embodiment of the disclosure, on one hand, after initial time sequence power consumption characteristic data corresponding to the memory are determined according to preset temperature, voltage and process deviation conditions, a corresponding characteristic prediction model is determined according to the relation between the initial time sequence power consumption characteristic data and basic characteristic data of the memory, time sequence data and power consumption data under the other temperature, voltage and process deviation conditions can be predicted through the characteristic prediction model, and the time sequence data and the power consumption data under the other temperature, voltage and process deviation conditions are not required to be obtained through a simulation mode, so that the efficiency of determining the time sequence data and the power consumption data can be improved, and the time spent for characterizing the memory is reduced. On the other hand, in the process of determining the feature prediction model, the feature prediction model is determined according to the relation between the initial time sequence power consumption feature data and the basic feature data of the memory, and different relations correspond to different prediction models, so that the prediction precision of the established feature prediction model can be improved. In another aspect, the time sequence data and the power consumption data of the existing determining memory are respectively determined, and the exemplary embodiment of the disclosure can integrate the time sequence data and the power consumption data to predict, so that the steps of the memory characterization processing are simplified, and the time of the memory characterization processing is further saved.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present disclosure are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which:
FIG. 1 schematically illustrates a flow chart of a memory characterization method according to an exemplary embodiment of the present disclosure;
FIG. 2 schematically illustrates a schematic diagram of a speed fluctuation range of a transistor according to an exemplary embodiment of the present disclosure;
FIG. 3 schematically illustrates a timing comparison result graph of a memory characterization scheme versus actual measurements according to an exemplary embodiment of the present disclosure;
FIG. 4 schematically illustrates a graph of power consumption versus actual measured values for a memory characterization scheme according to an exemplary embodiment of the present disclosure;
FIG. 5 schematically illustrates a flow chart of steps of a memory characterization method provided in accordance with an exemplary embodiment of the present disclosure;
FIG. 6 schematically illustrates a flow chart of a chip design method according to an exemplary embodiment of the present disclosure;
fig. 7 schematically illustrates a block diagram of an electronic device according to an exemplary embodiment of the present disclosure.
In the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
Detailed Description
The principles and spirit of the present disclosure will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are presented merely to enable one skilled in the art to better understand and practice the present disclosure and are not intended to limit the scope of the present disclosure in any way. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Those skilled in the art will appreciate that embodiments of the present disclosure may be implemented as a system, apparatus, device, method, or computer program product. Accordingly, the present disclosure may be embodied in the following forms, namely: complete hardware, complete software (including firmware, resident software, micro-code, etc.), or a combination of hardware and software.
According to an embodiment of the disclosure, a memory characterization method and a chip design method are provided.
Any number of elements in the figures are for illustration and not limitation, and any naming is used for distinction only, and not for any limiting sense.
The principles and spirit of the present disclosure are explained in detail below with reference to several representative embodiments thereof.
A memory characterization method according to an exemplary embodiment of the present disclosure is described below with reference to fig. 1.
Fig. 1 schematically illustrates a flow chart of a memory characterization method according to an exemplary embodiment of the present disclosure. Referring to fig. 1, a memory characterization method according to an exemplary embodiment of the present disclosure may include the steps of:
s12, determining initial time sequence power consumption characteristic data corresponding to the memory according to preset temperature, voltage and process deviation conditions.
The memory compiler is a unit module (such as SRAM, flash, etc.) for designing a complete set of memory. The memory compiler design comprises a plurality of memory unit modules with different sizes, and the design aim is to optimize the speed and the area of the unit modules as much as possible. Memory characterization (Memory Characterization) is a very important element in SRAM compiler design, and the time required for characterization is approximately one third of the SRAM compiler design cycle. Optimizing the memory characterization can realize the shortening of the design period of the SRAM compiler.
In practical applications, the memory characterization is mainly to extract timing information and power consumption information. In general, different temperatures and voltages have different effects on the timing information and the power consumption information, for example, the timing of the memory under the low temperature condition is different from the timing of the memory under the high temperature condition, and the power consumption of the memory under the low temperature condition and the power consumption under the high temperature condition may be different; in addition, under different voltage conditions, the timing and power consumption of the memory may also vary, resulting in differences. Therefore, in extracting the timing information and the power consumption information of the memory, the influence of temperature and voltage variations on the timing power consumption information must be considered.
In addition, as process dimensions continue to advance, process parameters that occur during process fabrication become more and more biased. For example, the circuit performance exhibited by MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor) is very different between different wafers of the same lot and different wafers of different lots, and the circuit performance difference of different transistors necessarily results in different timing information and power consumption information of their corresponding memories. That is, in addition to considering the influence of temperature and voltage on the memory characterization, it is necessary to consider the influence of process variation on the corresponding timing information and power consumption information of the memory. Thus, in exemplary embodiments of the present disclosure, the determination of memory characterization is accomplished under a combination of temperature, voltage, and process variations to obtain variations in timing and power consumption of the memory under a variety of different conditions.
In practical applications, process variations, i.e. variations in Process parameters occurring during the actual Process manufacturing Process, can be measured by the Process Corner (Process Corner). The process corner limits the speed fluctuation range of the NMOS and PMOS transistors to a range determined by four corners according to the fluctuation speed of the transistors, as shown in fig. 2. The four corners are respectively: fast NMOSFET and fast PMOSFET (FF), slow NMOSFET and slow PMOSFET (SS), fast NMOSFET and slow PMOSFET (FS), slow NMOSFET and fast PMOSFET (SF). Only memory chips falling within the range defined by the four corners are good.
The naming of the process corner is a two letter combination, the former letter representing the process corner of the NMOS and the latter letter representing the process corner of the PMOS. The types of process corners are typically: fast (Fast), slow (Slow) and normal (normal), wherein TT represents a normal-speed NMOS tube and a normal-speed PMOS tube.
The speed of the MOS transistor refers to the level of the threshold voltage, the fast corresponding threshold value is low, the slow corresponding threshold value is high, and the corresponding reflection has a score of speed in time sequence.
Based on this, the exemplary embodiments of the present disclosure employ a combination of temperature, voltage and process deviation conditions, i.e., a combination of temperature, voltage and process corner conditions, when acquiring the initial time-series power consumption characteristic data. And, can obtain the initial time sequence power consumption characteristic data of the corresponding memory under the temperature, voltage and technological deviation condition of multiunit presets. The initial time sequence power consumption characteristic data refer to corresponding time sequence data and power consumption data under the combined conditions of temperature, voltage and process angle.
In practical applications, the specific temperature, voltage and process angle can be determined according to practical conditions. For example, the temperature may be any value between-50 ℃ and 50 ℃, the voltage may be any value between 0.5V and 0.8V, and the process angle may be any value among FF, SS, TT.
In the case of a specific combination of temperature, voltage and process angle, multiple sets of combination conditions may be set, for example, the temperature, voltage and process angle conditions of three sets of combination conditions may be set, respectively: (-50 ℃, 0.5V, SS), (0 ℃, 0.65V, TT), and (50 ℃, 0.8V, FF), the time series data and the power consumption data under the three sets of combined conditions can be acquired in the initial time series power consumption characteristic data acquisition process.
Further, when a plurality of sets of temperature, voltage and process deviation conditions are set, a plurality of sets of temperature, voltage and process deviation conditions of an equilibrium distribution may be set, and a specific equilibrium manner may be determined according to practical situations, for example, as shown in the above example, which is not particularly limited by the exemplary embodiments of the present disclosure.
In practical application, when determining the initial time sequence power consumption characteristic data, a small amount of time sequence data and power consumption data corresponding to preset temperature, voltage and process deviation conditions can be determined. Since it is small, it can be realized in a simulation manner in determining the required initial timing power consumption characteristic data.
The simulation of the memory characterization is mainly to obtain a circuit structure netlist through integrated circuit design and layout design, then simulate the circuit structure netlist, bring corresponding temperature, voltage and process deviation conditions into the simulation process, and obtain time sequence data and partial power consumption data among all ports.
In practical applications, after acquiring the time-series data and the power consumption data, a data preprocessing operation needs to be performed on the acquired time-series data and power consumption data, and the specific data preprocessing operation can be determined according to practical situations, for example, performing de-duplication and data filling on the data. In general, the data may be used as initial timing power consumption characteristic data after a preprocessing operation is performed on the data.
S14, determining a corresponding feature prediction model according to the relation between the initial time sequence power consumption feature data and the basic feature data of the memory.
In the exemplary embodiment of the disclosure, after the initial time sequence power consumption characteristic data is determined, a characteristic prediction model can be established according to the initial time sequence power consumption characteristic data, and the time sequence data and the power consumption data under the conditions of other temperatures, voltages and process deviations are predicted through the characteristic prediction model without being obtained in a simulation mode, so that the determination efficiency of the time sequence data and the power consumption data can be improved, and the time for characterizing the memory is reduced.
In an exemplary embodiment of the present disclosure, in order to improve the accuracy of the prediction of the established feature prediction model, in determining the feature prediction model, the feature prediction model is determined according to the relationship between the initial time-series power consumption feature data and the basic feature data of the memory.
Specifically, in the process of determining the corresponding feature prediction model according to the relation between the initial time sequence power consumption feature data and the basic feature data of the memory, the feature prediction model is determined mainly according to the difference between the feature data contained in the initial time sequence power consumption feature data and the feature data contained in the basic feature data.
In an exemplary embodiment of the present disclosure, when the feature data included in the initial time-series power consumption feature data is only part or all of the feature data in the basic feature data, determining the first type of prediction model as the feature prediction model; when the initial time-series power consumption characteristic data includes not only the basic characteristic data, that is, also the extended characteristic data other than the basic characteristic data, the second prediction model is determined as the characteristic prediction model. The extended feature data may be different according to the types of the memories, for example, if the memories are added with redundancy column functions, the extended feature data includes redundancy column control, address, timing related to data signals, and the like, and the exemplary embodiments of the present disclosure are not particularly limited to specific extended feature data.
In an exemplary embodiment of the present disclosure, the first predictive model includes errors in the timing power consumption parameter and the temperature, voltage, and process bias parameters, and a first penalty term; the first penalty term is the product of the penalty factor and the parameter to be estimated. The formula for the first predictive model can be referred to as follows:
in the formula (1), lambda is a penalty factor,
for training samples from the basic feature dataset, beta is the parameter to be estimated, and the first penalty term is the product of the penalty factor lambda and the absolute value of the parameter to be estimated beta.
In practical applications, the penalty factor λ is generally a real number, and a user may set a value of about 10 according to actual needs, which may lose the practical meaning of the penalty factor λ. In the exemplary embodiment of the disclosure, according to the characteristics of the memory time sequence and the power consumption, the penalty factor lambda is set as the sum of the time sequence parameter and the normalized power consumption parameter in the initial time sequence power consumption characteristic data, so that the penalty factor lambda has practical significance, and the accuracy of estimating the parameter beta to be estimated can be improved.
It should be noted that, when the initial time sequence power consumption characteristic data is a plurality of sets of characteristic data corresponding to a plurality of sets of preset temperature, voltage and process deviation conditions, the value of the penalty factor λ may be determined by selecting the initial time sequence power consumption characteristic data corresponding to the most middle set of preset temperature, voltage and process deviation conditions.
For the parameter β to be estimated, since only one parameter β to be estimated exists in the formula (1), the optimal solution can be found by performing first-order derivation on the formula (1). Aiming at the situation that the first penalty term is absolute value and is not led to be led to the zero point, a partial derivative is required to be calculated on one variable, and other n-1 variables are kept unchanged, so that the first penalty term is led along the direction of the coordinate axis. And then, respectively solving partial derivatives of other n-1 variables, so that the partial derivative of each variable is 0, and defaulting the point to be the point of the minimum value of the function definition domain, thereby obtaining the parameter beta to be estimated.
In an exemplary embodiment of the present disclosure, the second predictive model includes errors in the timing power consumption parameter and the temperature, voltage, and process bias parameters, and a second penalty term; wherein the second penalty term is the product of the penalty factor and the square of the parameter to be estimated. The formula for the second predictive model can be referred to as follows:
in the formula (2), lambda is a penalty factor,
for training samples from the basic feature dataset, beta is the parameter to be estimated, and the second penalty term is the product of the penalty factor lambda and the square of the parameter to be estimated beta.
In practical applications, the penalty factor λ is generally a real number, and a user may set a value of about 10 according to actual needs, which may lose the practical meaning of the penalty factor λ. In the exemplary embodiment of the disclosure, according to the characteristics of the memory time sequence and the power consumption, the penalty factor lambda is set as the sum of the time sequence parameter and the normalized power consumption parameter in the initial time sequence power consumption characteristic data, so that the penalty factor lambda has practical significance, and the accuracy of estimating the parameter beta to be estimated can be improved.
It should be noted that, when the initial time sequence power consumption characteristic data is a plurality of sets of characteristic data corresponding to a plurality of sets of preset temperature, voltage and process deviation conditions, the value of the penalty factor λ may be determined by selecting the initial time sequence power consumption characteristic data corresponding to the most middle set of preset temperature, voltage and process deviation conditions.
For the parameter β to be estimated, since only one parameter β to be estimated exists in the formula (2), the optimal solution can be found by performing first-order derivation on the formula (2). Aiming at the situation that the second penalty term is absolute value and is not led to be led to the zero point, a partial derivative is required to be calculated on one variable, and other n-1 variables are kept unchanged, so that the direction of the coordinate axis is led. And then, respectively solving partial derivatives of other n-1 variables, so that the partial derivative of each variable is 0, and defaulting the point to be the point of the minimum value of the function definition domain, thereby obtaining the parameter beta to be estimated.
As can be seen by combining equation (1) and equation (2), the errors of the time series power consumption parameter and the temperature, voltage and process deviation parameters include: the square of the linear difference of the time series power consumption parameter and the temperature, voltage and process deviation parameters. In practical applications, the error between the time sequence power consumption parameter and the temperature, voltage and process deviation parameter can be constructed by using a least square method or the like besides using the square of the linear difference, and the exemplary embodiment of the disclosure is not limited in particular.
Further, in the exemplary embodiment of the present disclosure, when determining the feature prediction model according to the relationship between the initial time-series power consumption feature data and the basic feature data of the memory, the feature prediction model may also be determined according to the amount of feature data included in the initial time-series power consumption feature data and the basic feature data of the memory. For example, when the number of feature data included in the initial time-series power consumption feature data is less than or equal to the number of feature data included in the base feature data, determining the first predictive model as a feature predictive model; and determining the second type of prediction model as a feature prediction model when the number of feature data contained in the initial time sequence power consumption feature data is larger than the number of feature data contained in the basic feature data. The number of the basic feature data may be determined according to the actual situation, and may be 20 or 30, for example.
In practical applications, the initial time sequence power consumption characteristic data contained in memories with different functions are different, but the inventor finds that the memories with different functions almost all have at least part of the following basic characteristic data: the clock rising edge width Thpw, the clock falling edge width Tlpw, the chip select signal set-up time Tces, the chip select signal hold time Tceh, the write enable signal set-up time Tws, the write enable signal hold time Twh, the address set-up time Tas, the address hold time Tah, the data set-up time Tds, the data hold time Tdh, the read clock frequency Trc, the write clock frequency Twc, the data read delay Tcq, the output data hold time Toh, the bit-by-bit write enable set-up time Twbs, the bit-by-bit write enable hold time Twbh, the leakage amount Dcck at the time of clock fluctuation, the leakage amount Dcnock at the time of clock inactivity, the read cycle dynamic power consumption Acr, and the write cycle dynamic power consumption Acw. The meaning of each basic feature data is not described in detail herein.
The time sequence data and the power consumption data of the existing determined memory are respectively determined, and the time sequence data and the power consumption data can be integrated and predicted according to the embodiment of the disclosure, so that the steps of the memory characterization processing are simplified, and the time of the memory characterization processing is further saved. Because of the correlation between the time sequence and the power consumption data, by adding the first penalty term or the second penalty term, the prediction speed is ensured, and meanwhile, the better prediction accuracy is achieved, and the comparison result of the memory characterization scheme and the actual measured value provided by the exemplary embodiment of the disclosure is shown with reference to fig. 3 and 4, so that the predicted time sequence and the predicted power consumption value of the scheme are very close to the actual measured value.
S16, determining corresponding target time sequence power consumption characteristic data under the conditions of target temperature, voltage and process deviation according to the characteristic prediction model.
In the exemplary embodiment of the disclosure, after the parameter β to be estimated is determined, the first prediction model or the second prediction model may be used to predict the corresponding target time-series power consumption characteristic data under the conditions of the target temperature, the voltage and the process deviation, which is very simple and convenient. Specifically, the target temperature, the voltage and the process angle are taken as X values to be put into a first prediction model or a second prediction model, and the obtained Y values are the target time sequence power consumption characteristic data.
S18, determining a memory characteristic data packet according to the target time sequence power consumption characteristic data and the initial time sequence power consumption characteristic data.
After determining the target time sequence power consumption characteristic data, packaging the initial time sequence power consumption characteristic data corresponding to the preset temperature, voltage and process deviation conditions determined in the step S12 with the target time sequence power consumption characteristic data to obtain a memory characteristic data packet, wherein the memory characteristic data packet can be a data packet containing all time sequence power consumption characteristic data.
In practical applications, the target timing power consumption characteristic data may be timing power consumption characteristic data of a temperature, a voltage, and a process deviation condition other than the preset temperature, voltage, and process deviation condition.
In the overall design of integrated circuits such as chips, a large number of memories of various sizes, shapes and functions are required, and these memories are generally compiled by a memory compiler, and the timing and power consumption of the appropriate memories need to be modeled to integrate them into the overall chip design and analysis flow. Prior to modeling, it is necessary to screen from time-series power consumption data under a variety of temperature, voltage and process bias conditions. That is, after the memory feature data packet is acquired, the corresponding chip design can be performed according to the memory feature data packet.
Referring to fig. 5, a flowchart of steps of a memory characterization method provided by an exemplary embodiment of the present disclosure is shown. Firstly, initial data acquisition and data preprocessing are carried out, namely a circuit structure netlist is obtained through integrated circuit design and layout design, and then simulation is carried out on the circuit structure netlist, so that initial time sequence power consumption characteristic data can be obtained; then, the second step is data feature screening, namely feature screening is carried out on the initial time sequence power consumption feature data subjected to data preprocessing, and feature data with larger influence on a prediction result is selected to obtain screened feature data; thirdly, determining a model, namely judging whether the screened initial time sequence power consumption characteristic data only contains basic characteristic data, and if so, determining the first type of prediction model as a characteristic prediction model; if the second prediction model not only contains basic feature data but also contains extended feature data, determining the second prediction model as a feature prediction model; and fourthly, model prediction is carried out, and target time sequence power consumption characteristic data is obtained through prediction of the first type of prediction model or the second type of prediction model so as to obtain all time sequence power consumption data and form a memory characteristic data packet.
According to the memory characterization method of the embodiment of the disclosure, on one hand, after initial time sequence power consumption characteristic data corresponding to the memory are determined according to preset temperature, voltage and process deviation conditions, a corresponding characteristic prediction model is determined according to the relation between the initial time sequence power consumption characteristic data and basic characteristic data of the memory, time sequence data and power consumption data under the other temperature, voltage and process deviation conditions can be predicted through the characteristic prediction model, and the time sequence data and the power consumption data under the other temperature, voltage and process deviation conditions are not required to be obtained through a simulation mode, so that the efficiency of determining the time sequence data and the power consumption data can be improved, and the time spent for characterizing the memory is reduced. On the other hand, in the process of determining the feature prediction model, the feature prediction model is determined according to the relation between the initial time sequence power consumption feature data and the basic feature data of the memory, and different relations correspond to different prediction models, so that the prediction precision of the established feature prediction model can be improved. On the other hand, according to the characteristics of the time sequence and the power consumption of the memory, the penalty factor lambda is set as the sum of the time sequence parameter and the normalized power consumption parameter in the initial time sequence power consumption characteristic data, so that the penalty factor lambda has practical significance, the accuracy of the estimation of the parameter beta to be estimated can be improved, and due to the relevance between the time sequence and the power consumption data, the prediction speed is ensured and meanwhile, the prediction accuracy is better by adding the first penalty term or the second penalty term. In another aspect, the time sequence data and the power consumption data of the existing determining memory are respectively determined, and the exemplary embodiment of the disclosure can integrate the time sequence data and the power consumption data to predict, so that the steps of the memory characterization processing are simplified, and the time of the memory characterization processing is further saved.
A chip design method according to an exemplary embodiment of the present disclosure is described below with reference to fig. 6.
Fig. 6 schematically shows a flowchart of a chip design method according to an exemplary embodiment of the present disclosure. Referring to fig. 6, a chip design method according to an exemplary embodiment of the present disclosure may include the steps of:
s61, obtaining memory characteristic data packets corresponding to the memories according to the memory characteristic method.
The specific method for acquiring the memory feature data packet may refer to an exemplary method one, which is not described herein.
S63, determining a target memory corresponding to the chip according to the memory characteristic data packets and the target performance characteristics of the chip.
In the chip design process, the chip needs to be simulated according to the memory characteristic data packet to determine a target memory meeting the target performance characteristic of the chip as a preferred memory of the chip to be used in the chip. In this case, the specific chip simulation process may refer to the prior art, and the exemplary embodiments of the present disclosure are not described in detail.
As can be seen from the second exemplary method, the obtained memory feature data packet can be used in the chip design, so that the memory which can best meet the target performance feature of the chip can be selected as the target memory of the chip in the chip design process.
Having introduced the memory characterization method and the chip design method of the exemplary embodiments of the present disclosure, the electronic device of the exemplary embodiments of the present disclosure will be described next.
Those skilled in the art will appreciate that the various aspects of the present disclosure may be implemented as a system, method, or program product. Accordingly, various aspects of the disclosure may be embodied in the following forms, namely: an entirely hardware embodiment, an entirely software embodiment (including firmware, micro-code, etc.) or an embodiment combining hardware and software aspects may be referred to herein as a "circuit," module "or" system.
In some possible embodiments, an electronic device according to the present disclosure may include at least one processing unit, and at least one storage unit. Wherein the storage unit stores program code which, when executed by the processing unit, causes the processing unit to perform steps according to various exemplary embodiments of the disclosure described in the "methods" section of the specification above.
An electronic device 700 according to such an embodiment of the present disclosure is described below with reference to fig. 7. The electronic device 700 shown in fig. 7 is merely an example and should not be construed to limit the functionality and scope of use of embodiments of the present disclosure in any way.
As shown in fig. 7, the electronic device 700 is embodied in the form of a general purpose computing device. Components of electronic device 700 may include, but are not limited to: the at least one processing unit 710, the at least one storage unit 720, a bus 730 connecting the different system components (including the storage unit 720 and the processing unit 710), and a display unit 740.
Wherein the storage unit stores program code that is executable by the processing unit 710 such that the processing unit 710 performs steps according to various exemplary embodiments of the present disclosure described in the above-described "exemplary methods" section of the present specification. For example, the processing unit 710 may perform step S12 as shown in fig. 1: determining initial time sequence power consumption characteristic data corresponding to a memory according to preset temperature, voltage and process deviation conditions; step S14: determining a corresponding feature prediction model according to the relation between the initial time sequence power consumption feature data and the basic feature data of the memory; step S16: determining corresponding target time sequence power consumption characteristic data under the conditions of target temperature, voltage and process deviation according to the characteristic prediction model; step S18: and determining a memory characteristic data packet according to the target time sequence power consumption characteristic data and the initial time sequence power consumption characteristic data. The processing unit 710 may further perform step S61 as shown in fig. 6: obtaining memory characteristic data packets corresponding to a plurality of memories according to the memory characteristic method; step S63: and determining a target memory corresponding to the chip according to the plurality of memory characteristic data packets and the target performance characteristic of the chip.
The memory unit 720 may include readable media in the form of volatile memory units, such as Random Access Memory (RAM) 7201 and/or cache memory 7202, and may further include Read Only Memory (ROM) 7203.
The storage unit 720 may also include a program/utility 7204 having a set (at least one) of program modules 7205, such program modules 7205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment.
The electronic device 700 may also communicate with one or more external devices 770 (e.g., keyboard, pointing device, bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device 700, and/or any device (e.g., router, modem, etc.) that enables the electronic device 700 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 750. Also, electronic device 700 may communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN) and/or a public network, such as the Internet, through network adapter 760. As shown, network adapter 760 communicates with other modules of electronic device 700 over bus 730. It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with electronic device 700, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.
In some possible implementations, the various aspects of the disclosure may also be implemented in the form of a program product comprising program code for causing a terminal device to perform the steps of the memory characterization method or the audio processing model training method according to the various exemplary embodiments of the disclosure described in the "method" section of the present specification, when the program product is run on the terminal device, for example, the terminal device may perform the steps 12 to 18 as described in fig. 1, or the terminal device may perform the steps 61 to 63 as described in fig. 6.
The program product may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical disk, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In addition, as technology advances, readable storage media should also be interpreted accordingly.
Program code for carrying out operations of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server. In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).
It should be noted that while several modules or sub-modules in the above-described apparatus are mentioned in the above detailed description, such partitioning is merely exemplary and not mandatory. Indeed, the features and functions of two or more modules described above may be embodied in one module in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module described above may be further divided into a plurality of modules to be embodied.
Furthermore, although the operations of the methods of the present disclosure are depicted in the drawings in a particular order, this is not required to or suggested that these operations must be performed in this particular order or that all of the illustrated operations must be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform.
While the spirit and principles of the present disclosure have been described with reference to several particular embodiments, it is to be understood that this disclosure is not limited to the particular embodiments disclosed nor does it imply that features in these aspects are not to be combined to benefit from this division, which is done for convenience of description only. The disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
Claims (12)
1. A method of characterizing a memory, comprising:
determining initial time sequence power consumption characteristic data corresponding to a memory according to preset temperature, voltage and process deviation conditions;
determining a corresponding feature prediction model according to the relation between the initial time sequence power consumption feature data and the basic feature data of the memory;
determining corresponding target time sequence power consumption characteristic data under the conditions of target temperature, voltage and process deviation according to the characteristic prediction model;
and determining a memory characteristic data packet according to the target time sequence power consumption characteristic data and the initial time sequence power consumption characteristic data.
2. The method of claim 1, wherein determining the corresponding feature prediction model based on the relationship between the initial time-series power consumption feature data and the base feature data of the memory comprises:
and determining a feature prediction model according to the difference between the feature data contained in the initial time sequence power consumption feature data and the feature data contained in the basic feature data.
3. The memory characterization method according to claim 2, wherein the determining the feature prediction model according to the dissimilarity between the feature data contained in the initial time-series power consumption feature data and the feature data contained in the base feature data comprises:
and determining a first prediction model as the characteristic prediction model when the characteristic data contained in the initial time sequence power consumption characteristic data is only part or all of the basic characteristic data.
4. The memory characterization method of claim 3 wherein the first predictive model includes errors in timing power consumption parameters and temperature, voltage, and process bias parameters, and a first penalty term;
wherein the first penalty term is the product of the penalty factor and the parameter to be estimated.
5. The memory characterization method according to claim 2, wherein the determining the feature prediction model according to the dissimilarity between the feature data contained in the initial time-series power consumption feature data and the feature data contained in the base feature data comprises:
and determining a second type of prediction model as the feature prediction model when the initial time sequence power consumption feature data not only comprises the basic feature data but also comprises the extended feature data.
6. The memory characterization method of claim 5 wherein the second predictive model includes errors in timing power consumption parameters and temperature, voltage, and process bias parameters, and a second penalty term;
wherein the second penalty term is the product of the penalty factor and the square of the parameter to be estimated.
7. The memory characterization method according to claim 4 or 6, wherein the penalty factor is a sum of a timing parameter and a normalized power consumption parameter in the initial timing power consumption characteristic data.
8. The memory characterization method according to claim 4 or 6, wherein the error of the time series power consumption parameter with temperature, voltage and process deviation parameters comprises: the square of the linear difference of the time-series power consumption parameter and the temperature, voltage and process deviation parameter.
9. The memory characterization method of claim 1 wherein the base characterization data comprises: the clock rising edge width, the clock falling edge width, the chip select signal setup time, the chip select signal hold time, the write enable signal setup time, the write enable signal hold time, the address setup time, the address hold time, the data setup time, the data hold time, the read clock frequency, the write clock frequency, the data read delay, the output data hold time, the write enable setup time by bit, the write enable hold time by bit, the power leakage when the clock is varied, the power leakage when the clock is stationary, the read cycle dynamic power consumption, and at least a portion of the write cycle dynamic power consumption.
10. A chip design method, comprising:
the memory characterization method according to any one of claims 1 to 9, wherein memory characterization data packets corresponding to a plurality of memories are acquired;
and determining a target memory corresponding to the chip according to the memory characteristic data packets and the target performance characteristics of the chip.
11. A storage medium having stored thereon a computer program, which when executed by a processor, implements the method of any of claims 1 to 10.
12. An electronic device, comprising:
a processor; and
a memory for storing executable instructions of the processor;
wherein the processor is configured to perform the method of any one of claims 1 to 10 via execution of the executable instructions.
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