CN113937019A - Wafer level packaging method and packaging structure - Google Patents

Wafer level packaging method and packaging structure Download PDF

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Publication number
CN113937019A
CN113937019A CN202010673274.2A CN202010673274A CN113937019A CN 113937019 A CN113937019 A CN 113937019A CN 202010673274 A CN202010673274 A CN 202010673274A CN 113937019 A CN113937019 A CN 113937019A
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chip
interconnection
electrode
wafer
bonding
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CN202010673274.2A
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黄河
刘孟彬
向阳辉
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Smic Ningbo Co ltd Shanghai Branch
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Smic Ningbo Co ltd Shanghai Branch
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Priority to CN202010673274.2A priority Critical patent/CN113937019A/en
Priority to PCT/CN2021/105824 priority patent/WO2022012474A1/en
Publication of CN113937019A publication Critical patent/CN113937019A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies

Abstract

A wafer level packaging method and a packaging structure are provided, the method comprises the following steps: providing a first device wafer formed with a plurality of first chips, wherein each first chip comprises a first surface and a second surface which are opposite, and the first surface is provided with a first interconnection electrode and an external electrode; providing a plurality of second chips, wherein the surfaces of the second chips are provided with second interconnection electrodes; bonding a second chip on the first surface by using a bonding layer, wherein a second interconnection electrode is opposite to the first interconnection electrode in the vertical direction to form a cavity, and the second chip exposes out of the external electrode; and after bonding, forming an electroplating interconnection structure filled in the cavity and an electroplating interconnection bump protruding out of the surface of the external electrode. The invention improves the packaging efficiency and the packaging reliability and reduces the packaging cost while realizing wafer-level packaging.

Description

Wafer level packaging method and packaging structure
Technical Field
The embodiment of the invention relates to the technical field of semiconductor packaging, in particular to a wafer level packaging method and a packaging structure.
Background
With the trend of very large scale integrated circuits, the feature size of the integrated circuits is continuously decreasing, and the requirements of people on the packaging technology of the integrated circuits are also increasing correspondingly. Conventional packaging technologies include Ball Grid Array (BGA), Chip Scale Package (CSP), Wafer Level Package (WLP), three-dimensional package (3D), and System In Package (SiP).
At present, in order to meet the objectives of lower cost, more reliability, faster performance and higher density of integrated circuit packaging, an advanced packaging method mainly adopts wafer level package in package (WLPSIP) in a three-dimensional stacking mode.
In the wafer level system packaging process, two bare chips need to be bonded together to realize physical connection, and electrical connection between the two bare chips needs to be realized.
Disclosure of Invention
The embodiment of the invention provides a wafer level packaging method and a packaging structure, which can improve the packaging efficiency and the packaging reliability and reduce the packaging cost while realizing wafer level packaging.
To solve the above problems, an embodiment of the present invention provides a wafer level packaging method, including: providing a first device wafer formed with a plurality of first chips, wherein each first chip comprises a first surface and a second surface which are opposite, and the first surface is provided with a first interconnection electrode and an external electrode which are exposed and spaced; providing a plurality of second chips, wherein the surfaces of the second chips are provided with exposed second interconnection electrodes; bonding the second chip on the first surface of the first chip by using a bonding layer, wherein the second interconnection electrode and the first interconnection electrode are opposite up and down and enclose a cavity, and the second chip exposes the external electrode; and after bonding, forming an electroplating interconnection structure filled in the cavity and an electroplating interconnection bump protruding out of the surface of the external electrode.
Accordingly, an embodiment of the present invention provides a package structure, including: the chip comprises a substrate, a first chip and a second chip, wherein the substrate is provided with the first chip, the first chip comprises a first surface and a second surface which are opposite, and the first surface is provided with a first interconnection electrode and an external electrode which are exposed and spaced; the second chip is bonded on the first surface of the first chip, the surface of the second chip is provided with a second exposed interconnection electrode, the second interconnection electrode is opposite to the first interconnection electrode in the vertical direction, and the second chip exposes the external electrode; the bonding layer is positioned between the second chip and the first chip; a plated interconnect structure between and electrically connecting the second interconnect electrode and the first interconnect electrode; and electroplating the interconnection convex block to protrude out of the surface of the external electrode.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
the embodiment of the invention provides a first device wafer and a second chip, wherein a plurality of first chips are formed on the first device wafer, the first surfaces of the first chips are provided with exposed first interconnection electrodes and external electrodes which are spaced, the surface of the second chip is provided with an exposed second interconnection electrode, the second chip is bonded on the first surface of the first chip by utilizing a bonding layer, the second interconnection electrodes and the first interconnection electrodes are opposite up and down to form a cavity, the external electrodes are exposed from the second chip, and then an electroplating interconnection structure filled in the cavity and an electroplating interconnection bump protruding out of the surface of the external electrodes are formed; the embodiment of the invention forms the electroplating interconnection structure and the electroplating interconnection lug, thereby realizing wafer-level packaging, and influenced by the manufacturing process of the first device wafer, the surface of the external electrode is usually lower than the surface of the first chip, therefore, the electric property of the external electrode is led out through the electroplating interconnection lug, the electroplating interconnection lug protrudes out of the surface of the external electrode, which is easy to carry out wire bonding (wire bond) process, the connection performance of a welding wire and the electroplating interconnection lug is higher, thereby being beneficial to improving the packaging reliability, and the electroplating interconnection lug is formed while the electroplating interconnection structure is formed, thereby being beneficial to improving the packaging efficiency; in addition, the second chip is bonded on the surface of the first chip, and the external electrode is exposed, so that a containing space can be provided for a bonding wire connected with the external electrode, the bonding wire is compatible with three-dimensional stacked wafer-level packaging, the increase of the height of a packaging structure cannot be caused, and the bonding wire has the advantages of simple routing process and low cost. In summary, the embodiment of the invention improves the packaging efficiency and the packaging reliability and reduces the packaging cost while realizing wafer-level packaging.
In an alternative, the upper surface of the electroplated interconnection bump is a flat surface, thereby ensuring the bonding reliability of the subsequent bonding wire.
Drawings
Fig. 1 to 6 are schematic structural diagrams corresponding to steps of an embodiment of a wafer level packaging method according to the present invention.
Detailed Description
In the field of integrated circuit packaging, two bare chips with different functions or structures need to be integrated together, that is, SIP in a three-dimensional stacking mode is adopted, and such packaging not only needs to bond two bare chips to realize physical connection, but also needs to realize electrical connection between the two bare chips.
Among them, the most typical packaging method may be: 1) the upper bare chip and the lower bare chip are stacked on the substrate in a three-dimensional manner through the curing adhesive, and lead bonding pads of the two bare chips are led to the substrate by adopting a wire bond process; 2) the upper bare chip and the lower bare chip are stacked on the substrate in a three-dimensional manner through the curing adhesive, the lead bonding pad of the upper bare chip is led to the lead bonding pad of the lower bare chip by adopting a wire bond process, and then the lead bonding pad of the lower bare chip is led to the substrate; 3) realizing flip-chip bonding by means of bump welding (bump) prefabricated on the surface of the upper bare chip or bump welding prefabricated on the surface of the lower bare chip, and leading a lead pad of the lower bare chip onto the substrate by means of a wire bond; 4) the flip-chip bonding is realized by the projection spot welding prefabricated on the surface of the upper bare chip or the projection spot welding prefabricated on the surface of the lower bare chip, and the lead bonding pad of the lower bare chip is connected to the back surface of the lower bare chip by a through silicon via interconnection (TSV) structure prefabricated in the lower bare chip.
Among them, the wire bond process is a commonly used electrical connection process. However, during the manufacturing process of the device wafer, the exposed positions of the wire pads in the bare chip are generally protected by the dielectric layer to prevent short circuits, so that the surfaces of the wire pads are lower than the surface of the dielectric layer (i.e., the surfaces of the wire pads in the bare chip are generally lower than the surface of the bare chip), that is, grooves are formed in the bare chip to expose the wire pads.
Accordingly, since the surface of the wire bond pad in the die is generally lower than the surface of the die, this increases the process difficulty of the wire bond process, thereby reducing the electrical connection performance between the wire bond process-formed bonding wire and the wire bond pad, and thus reducing the package reliability.
In order to solve the technical problem, an embodiment of the present invention provides a first device wafer and a second chip, where a plurality of first chips are formed, a first surface of each first chip has a first interconnection electrode and an external electrode that are exposed and isolated at intervals, a surface of each second chip has a second interconnection electrode that is exposed, and the second chip is bonded to the first surface of the first chip by using a bonding layer, the second interconnection electrode and the first interconnection electrode are opposite to each other in the up-down direction to form a cavity, and the second chip exposes the external electrode, and then an electroplating process is performed to form an electroplating interconnection structure filled in the cavity and an electroplating interconnection bump protruding out of the surface of the external electrode; the embodiment of the invention utilizes an electroplating process to form an electroplating interconnection structure and an electroplating interconnection lug, thereby realizing wafer-level packaging, and is influenced by the manufacturing process of the first device wafer, the surface of the external electrode is usually lower than the surface of the first chip, therefore, the electric property of the external electrode is led out through the electroplating interconnection lug, the electroplating interconnection lug protrudes out of the surface of the external electrode, the routing process is easy to carry out, the connection performance of a bonding wire and the electroplating interconnection lug is higher, thereby being beneficial to improving the packaging reliability, and the electroplating interconnection lug is formed while the electroplating interconnection structure is formed, thereby being beneficial to improving the packaging efficiency; in addition, the second chip is bonded on the surface of the first chip, and the external electrode is exposed, so that a containing space can be provided for a bonding wire connected with the external electrode, the bonding wire is compatible with three-dimensional stacked wafer-level packaging, the increase of the height of a packaging structure cannot be caused, and the bonding wire has the advantages of simple routing process and low cost. In summary, the embodiment of the invention improves the packaging efficiency and the packaging reliability and reduces the packaging cost while realizing wafer-level packaging.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 6 are schematic structural diagrams corresponding to steps of an embodiment of a wafer level packaging method according to the present invention.
Referring to fig. 1, a first device Wafer (CMOS Wafer)100 formed with a plurality of first chips 110 is provided, the first chips 110 including opposite first and second surfaces 110a and 110b, the first surface 110a having exposed and spaced apart first interconnection electrodes 130 and external electrodes 120.
The packaging method is used for realizing wafer level system packaging, and the first device wafer 100 is used for bonding with a chip to be integrated in a subsequent process.
In this embodiment, the first device wafer 100 is fabricated using integrated circuit fabrication techniques, and the first device wafer 100 includes a substrate. As an example, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the first device wafer 100 includes opposite wafer front and wafer back sides, and the wafer back side refers to a bottom surface of the substrate in the first device wafer 100.
The first device wafer 100 has a plurality of first chips 110 formed therein, a first surface 110a of the first chips 110 has first interconnection electrodes 130 and external connection electrodes 120, and the first interconnection electrodes 130 and the external connection electrodes 120 are exposed at an edge of the first surface 110 a. The first surface 110a and the front surface of the wafer are the same surface, and the first interconnection electrode 130 and the external electrode 120 are both interconnection lead pads (Pad) of the first chip 110, and are used for electrically connecting the first chip 110 with other chips or circuit structures.
In this embodiment, the first interconnection electrode 130 and the external connection electrode 120 are electrically connected to different circuit structures in the first chip 110.
In this embodiment, a second chip is bonded on the first chip 110, the second interconnection electrode of the second chip is opposite to the first interconnection electrode 130 from top to bottom to form a cavity, and an electroplating interconnection structure filled in the cavity and an electroplating interconnection bump protruding from the surface of the external electrode 120 are formed by an electroplating process, and the electroplating interconnection structure and the electroplating interconnection bump are isolated from each other, thereby realizing electrical isolation between the electroplating interconnection structure and the electroplating interconnection bump.
Therefore, the minimum distance between the first interconnection electrode 130 and the external connection electrode 120 is not excessively small. If the minimum distance between the first interconnection electrode 130 and the external electrode 120 is too small, the plated interconnection structure and the plated interconnection bump are easily bridged (bridge) or merged (merge), thereby adversely affecting the reliability of the package. For this reason, in the present embodiment, the minimum pitch of the first interconnection electrode 130 and the external connection electrode 120 is 3 micrometers.
It should be noted that, in other embodiments, the first interconnection electrode may also be electrically connected to the external electrode according to the circuit design.
In this embodiment, a second chip is bonded on the first chip 110, and the first interconnection electrode 130 is used to electrically connect with the second chip. The external electrode 120 is used for electrically leading out a chip module formed by the first chip 110 and the corresponding second chip, so as to electrically connect the chip module with other substrates having circuit structures.
It should be noted that the exposed positions of the first interconnection electrode 130 and the external electrode 120 are protected by a dielectric layer (not labeled) to prevent short circuit, and in the manufacturing process of the first device wafer 100, the dielectric layer is etched to expose the first interconnection electrode 130 and the external electrode 120, so that the surfaces of the first interconnection electrode 130 and the external electrode 120 are lower than the first surface 110a, that is, the first surface 110a is formed with grooves respectively exposing the first interconnection electrode 130 and the external electrode 120.
It should be noted that, for convenience of illustration, the embodiment takes the first device wafer 100 with five first chips 110 formed therein as an example for description. The number of the first chips 110 is not limited to five.
Referring to fig. 2, a plurality of second chips 200 are provided, and the surfaces of the second chips 200 have second interconnection electrodes 210 exposed.
The second chip 200 is used as a chip to be integrated in the wafer level system package.
The second chip 200 may be one or more of an active element, a passive element, a micro electro mechanical system, an optical element, and the like. Specifically, the second chip 200 may be a functional chip such as a memory chip, a communication chip, a processing chip, a flash memory chip, or a logic chip.
Subsequently, a plurality of second chips 200 are integrated on the first device wafer 100, and a packaging integration process is completed on the first device wafer 100 to realize wafer-level packaging, so that the area of a packaging structure is greatly reduced, the manufacturing cost is reduced, the electrical performance is optimized, batch manufacturing is optimized, and the workload and the equipment requirement can be obviously reduced.
In this embodiment, the number of the second chips 200 is the same as the number of the first chips 110. In other embodiments, the number of the first chip and the second chip may also be different.
In this embodiment, the second chip 200 is fabricated by using an integrated circuit fabrication technology, and the second chip 200 includes a substrate. The description of the substrate of the second chip 200 may refer to the foregoing description of the first chip 110, and is not repeated herein.
The surface of the second chip 200 has a second interconnection electrode 210, and at the edge of the surface of the second chip 200, the second interconnection electrode 210 is exposed, and the second interconnection electrode 210 is an interconnection wire pad of the second chip 200. In this embodiment, the second chip 200 includes a chip front surface and a chip back surface opposite to each other, and the second interconnection electrode 210 is located on the chip front surface, that is, the chip front surface exposes the second interconnection electrode 210. Wherein the chip back side refers to the bottom surface of the substrate in the second chip 200.
It should be noted that the second chip 200 may have a similar surface structure as the first chip 110, the exposed position of the second interconnection electrode 210 is protected by a dielectric layer (not labeled) to prevent short circuit, and the surface of the second interconnection electrode 210 is lower than the surface of the second chip 200, that is, a groove exposing the second interconnection electrode 210 is formed on the surface of the second chip 200.
It should be noted that the size of the second chip 200 is smaller than that of the first chip 110, so that the second chip 200 can expose the external connection electrode 120 of the first chip 110 after the second chip 200 is bonded to the first chip 110.
With continued reference to fig. 2, the second chip 200 is bonded to the first surface 110a (shown in fig. 1) of the first chip 110 by using the bonding layer 140, the second interconnection electrode 210 and the first interconnection electrode 130 are opposite to each other up and down, so as to enclose the cavity 10, and the second chip 200 exposes the external electrode 120 of the first chip 110.
By bonding the second chip 200 to the first chip 110, system integration of the second chip 200 and the first wafer 100 is achieved.
Moreover, the second chip 200 is bonded on the first surface 110a so as to electrically connect the second chip 200 and the first chip 110.
In addition, the second chip 200 exposes the external electrode 120 of the first chip 110, so that the packaging method is compatible with a wire bonding process, that is, a receiving space can be provided for a bonding wire connected to the external electrode 120, so that the bonding wire is compatible with three-dimensional stacked wafer-level packaging, and the increase of the height of a packaging structure cannot be caused.
In this embodiment, after bonding, the second interconnection electrode 210 and the first interconnection electrode 130 are opposite to each other up and down to form a cavity 10, and the second interconnection electrode 210 and the first interconnection electrode 130 are located in the cavity 10.
The cavity 10 is used to fill the electroplated body, thereby forming an electroplated interconnect structure electrically connecting the second interconnect electrode 210 and the first interconnect electrode 130. The groove where the first interconnection electrode 130 is located and the groove where the second interconnection electrode 210 is located are buckled to form the cavity 10, and the cavity 10 is not closed, so that the plating body can be filled into the cavity 10.
As an example, each of the second chips 200 is individually bonded to the corresponding first chip 110 on the first device wafer 100 in a chip-level manner, so that each of the second chips 200 can be precisely bonded to a predetermined position.
In this embodiment, the second chip 200 is bonded on the first surface 110a by using the bonding layer 140. The bonding layer 140 has a thickness so as to form the unsealed cavity 10.
In this embodiment, the bonding layer 140 has viscosity, so that adhesion bonding can be achieved, the bonding temperature of the adhesion bonding is low, which is beneficial to reducing the influence on the performance of the chip, and the process of the adhesion bonding is simple.
Specifically, the bonding layer 140 is made of a photosensitive material, so that patterning can be realized through a photolithography process, and damage to the electrode is reduced.
In this embodiment, the bonding layer 140 is a Dry Film (Dry Film). In other embodiments, other types of adhesive layers may be used, such as Die Attach Film (DAF).
In this embodiment, after the bonding layer 140 is formed on the exposed first surface 110a of the first interconnection electrode 130 and the external electrode 120, the second chip 200 is bonded to the first surface 110 a. The bonding layer 140 is formed on the first device wafer 100, so that the bonding layer 140 can be formed on a plurality of first chips 110 in the same step, thereby improving the packaging efficiency.
Also, the bonding layer 140 exposes the first interconnection electrode 130 and the external connection electrode 120, thereby forming the unsealed cavity 10.
In other embodiments, the second chip may be bonded to the first chip after the bonding layer is formed on the second chip.
It should be noted that the thickness of the bonding layer 140 is not too small, nor too large.
If the thickness of the bonding layer 140 is too small, the adhesion of the bonding layer 140 is insufficient, and the bonding strength between the second chip 200 and the first device wafer 100 is reduced.
The subsequent electroplating body is filled in the cavity 10 to form an electroplated interconnection structure, and is deposited on the surface of the external electrode 120 at the same time to form an electroplated interconnection bump protruding from the surface of the external electrode 120, so that the electroplated interconnection bump protrudes from the first surface 110a of the first chip 110, thereby facilitating the wire bonding process. The thickness of the bonding layer 140 affects the height of the cavity 10, and the height of the cavity 10 correspondingly affects the height of the plated interconnect structure and the plated interconnect bump, and the greater the height of the cavity 10, the greater the volume of the plated interconnect structure and the plated interconnect bump. If the thickness of the bonding layer 140 is too small, the height of the cavity 10 is easily too small, so that the difficulty of filling the cavity 10 with a subsequent electroplating body is increased, and the height of the electroplated interconnection bump is easily too small, so that the difficulty of the routing process is difficult to significantly reduce; if the thickness is too large, the thickness of the package structure formed subsequently is too large, which is not favorable for the development of miniaturization of the device, and as the volumes of the plated interconnection structure and the plated interconnection bump become larger, the probability of bridging or fusion between the plated interconnection structure and the plated interconnection bump becomes higher. For this reason, in the present embodiment, the thickness of the bonding layer 140 is 5 to 50 micrometers.
In this embodiment, bonding is achieved by an optical alignment process. In the process of manufacturing the second chip 200 and the first device wafer 100, the surfaces of the second chip 200 and the first chip 110 have corresponding optical alignment marks, so that bonding can be achieved by using an optical alignment process, which is beneficial to improving bonding accuracy.
Wherein, the light source adopted by the optical alignment process comprises an infrared light source or a visible light source. As an example, the optical alignment process employs an infrared light source to further improve alignment accuracy.
In other embodiments, mechanical alignment may be used to achieve bonding, as appropriate. For example, when the chip surface is not formed with the alignment marks.
It should be noted that this embodiment is described by taking adhesive bonding as an example, and in other embodiments, other bonding methods may also be adopted to bond the second chip to the first device wafer, for example, the bonding is realized by silicon oxide-silicon oxide fusion bonding.
Referring to fig. 3, after bonding, a plated interconnection structure 31 filled in the cavity 10 (as shown in fig. 2) and a plated interconnection bump 32 protruding from the surface of the external electrode 120 are formed.
The plated interconnect structure 31 is used to realize an electrical connection between the first interconnect electrode 130 and the second interconnect electrode 210, thereby realizing an interconnect package of the second chip 200 and the first device wafer 100.
The plated interconnect bumps 32 electrically conduct the first chip 110 in preparation for a subsequent packaging process. Electrical connection of the first chip 110 to other substrates (e.g., circuit boards) can subsequently be achieved by electroplating the interconnect bumps 32, for example.
In the present embodiment, the electroplating interconnection structure 31 and the electroplating interconnection bump 32 are formed by using an electroplating process, and a good filling effect can be achieved in the cavity 10 by using the electroplating process, so that the reliability of electrical connection is improved.
The surface of the external electrode 120 is usually lower than the first surface 110a of the first chip 110 under the influence of the manufacturing process of the first device wafer 100, so that the electrical property of the external electrode 120 is led out through the plated interconnection bump 32, and the plated interconnection bump 32 protrudes out of the surface of the external electrode 120, which is easy for the subsequent routing process to be performed, and the connection performance between the bonding wire and the plated interconnection bump 32 is higher, thereby being beneficial to improving the packaging reliability; further, the plated interconnect bump 32 is formed at the same time as the plated interconnect structure 31 is formed, which is advantageous in improving the packaging efficiency. In summary, the present embodiment can improve the packaging efficiency and the packaging reliability while realizing the wafer level packaging.
In this embodiment, an electroplating process is performed to fill the cavity 10 with an electroplating body from the boundary of the second chip 200, and the electroplating body in the cavity 10 is in contact with both the first interconnection electrode 130 and the second interconnection electrode 210, thereby achieving electrical connection between the first interconnection electrode 130 and the second interconnection electrode 210.
Since the second chip 200 exposes the external electrode 120 of the first chip 110, the external electrode 120 is exposed to the process environment of the electroplating process, and thus the electroplating body fills the cavity 10 and deposits on the external electrode 120, thereby forming the electroplated interconnection bump 32 on the surface of the external electrode 120. The plated interconnection structure 31 and the plated interconnection bump 32 are formed in the same step, improving the package yield.
In this embodiment, the upper surface of the plated interconnection bump 32 is a flat surface, so as to ensure the reliability of the subsequent bonding of the bonding wire.
In this embodiment, the electroplating process is electroless plating (i.e., electroless plating). Specifically, the bonded second chip 200 and the first device wafer 100 are placed in a solution containing metal ions (e.g., a solution such as electroless silver plating, nickel plating, copper plating, etc.), without being energized, and the metal ions are reduced to metal by a strong reducing agent according to the redox reaction principle and deposited on the surfaces of the first interconnection electrode 130, the second interconnection electrode 210, and the external electrode 120 to form a dense metal plating layer, and after a period of reaction time, the metal plating layer fills the cavity 10, thereby forming the plated interconnection structure 31 and the plated interconnection bump 32.
By adopting the electrodeless electroplating, the electroplating body is deposited on the surface of the exposed electrode without electrifying, thereby reducing the requirement on the interconnection mode of the electrode in the chip and having higher process flexibility.
Wherein the cavity 10 has a certain height, which makes the plated interconnection bump 32 have a certain height, and the plated interconnection bump 32 protrudes from the surface of the external electrode 120.
In this embodiment, the material of the plated interconnect structure 31 and the plated interconnect bump 32 are the same, and each includes one or more of copper, nickel, zinc, tin, silver, gold, tungsten, and magnesium.
In other embodiments, when the first interconnection electrode and the external electrode need to be electrically connected, the first interconnection electrode and the external electrode can be electrically connected by making the plated interconnection structure and the plated interconnection bump contact or merge with each other according to the circuit design requirement.
Referring to fig. 4, after forming the plated interconnection structure 31 and the plated interconnection bump 32, the packaging method further includes: the first device wafer 100 (shown in fig. 3) is diced to form a chip module (not labeled) comprising the second chip 200 and the first chip 110 bonded together.
After dicing the first device wafer 100, the second chips 200 and the corresponding first chips 110 form independent chip modules, thereby preparing for subsequent bonding of the chip modules to other substrates.
The first device wafer 100 is usually provided with criss-cross scribe lines (scribes lines) disposed between any adjacent two of the first chips 110 on the first device wafer 100, so that the first device wafer 100 is diced along the scribe lines.
In this embodiment, the first device wafer 100 between the first chips 110 is partially etched from the first surface 110a to form trenches (not shown), and then the second surface 110b is subjected to back thinning to expose the trenches, so as to separate the first chips 110.
Because the etching process has a wider process window, a narrower cutting path can be etched, so that the probability of damage to the second chip 200, the electroplated interconnection structure 31 or the electroplated interconnection bump 32 can be reduced, the edge breakage phenomenon of the first chip 110 can be improved, the probability of damage to an effective circuit inside the first chip 110 is reduced, a complete independent stacked body can be obtained, and the packaging reliability can be improved.
Moreover, the back thinning process is performed on the second surface 110b, so that a wafer level chip package with lighter weight, thinner thickness and smaller volume can be realized.
In other embodiments, the cutting can be performed by laser cutting or mechanical cutting.
In this embodiment, the second chip 200 is bonded on the first device wafer 100 in a chip-level manner. In other embodiments, the second chip may also be bonded to the first device wafer in a wafer-level manner.
Specifically, in the step of providing a plurality of second chips, the second chips are located in a second device wafer; in the step of bonding, a second device wafer is bonded to the first device wafer, respectively. Therefore, before dicing the first device wafer, the packaging method further includes: and cutting the second device wafer to separate the second chips.
As an example, the second device wafer is diced prior to the electroplating process. By first cutting the second device wafer, the cavity can be better exposed so that the plating body enters the cavity. For the description of the dicing process of the second device wafer, reference may be made to the foregoing corresponding description of the dicing process of the first device wafer, and details are not repeated here.
Referring to fig. 5, after the first device wafer 100 (shown in fig. 3) is diced, the packaging method further includes: the second surface 110b (shown in fig. 1) of the first chip 110 is adhered to a substrate 300, and the substrate 300 has a circuit structure 310 therein.
The second surface 110b (shown in fig. 1) is bonded to the substrate 300, so as to prepare for a subsequent wire bonding process, so as to provide a circuit signal to the chip module formed by the first chip 110 and the second chip 200 by using the circuit structure 310 in the substrate 300, or to electrically connect the chip module with other chips or other substrates by using the circuit structure 310 in the substrate 300.
In this embodiment, the substrate 300 may be a Printed Circuit Board (PCB). In other embodiments, the substrate may also be a flexible printed circuit board (FPC) or an interposer (interposer) board or other types of substrates.
In this embodiment, the second surface 110b (shown in fig. 1) is bonded to the substrate 300 by the adhesive layer 230. As an example, the adhesive layer 230 may be a sheet adhesive film.
With continued reference to fig. 5, wire bonds 220 are formed by a wire bond process, the wire bonds 220 electrically connecting the plated interconnect bumps 32 and the circuit structure 310 in the substrate 300.
The wire bonds 220 enable electrical connection of the plated interconnect bumps 32 with the circuit structure 310, thereby enabling system integration of the chip module composed of the first chip 110 and the second chip 200 and the substrate 300.
The wire bonding process is the most commonly used circuit connection method in the integrated circuit packaging process, and the wire bonding process is used for sequentially bonding thin metal wires or metal strips on bonding points of a chip and a lead frame or a packaging substrate to form circuit connection. The wire bonding process has higher compatibility with the current packaging process, and has the advantages of simple process and low cost, so the wire bonding process is favorable for reducing the packaging cost.
In this embodiment, the bonding wires 220 are metal wires, such as: gold or aluminum wires.
In this embodiment, the highest position of the bonding wire 220 is lower than the surface of the second chip 200 facing away from the first chip 110. The subsequent process may also form a covering layer at least covering the plated interconnection structure 31, the plated interconnection bump 32 and the bonding wire 220, and by making the highest position of the bonding wire 220 lower than the surface of the second chip 200 facing away from the first chip 110, the plated interconnection structure 31, the plated interconnection bump 32 and the bonding wire 220 can be buried in the covering layer, and at the same time, the thickness of the package structure is easily made smaller.
In other embodiments, the highest point of the bonding wire may be flush with the surface of the second chip facing away from the chip.
Referring to fig. 6, after forming the bonding wires 220, the packaging method further includes: a capping layer 250 is formed covering at least the plated interconnect structure 31, the plated interconnect bumps 32 and the bonding wires 220.
The cover layer 250 serves to fix the first chip 110 and the second chip 200, so as to integrate the first chip 110 and the second chip 200 into a package. Furthermore, the cover layer 250 serves to achieve insulation, sealing and protection of the plated interconnect structure 31, the plated interconnect bumps 32 and the bonding wires 220.
Thus, the material of the capping layer 250 is an insulating material. In this embodiment, the material of the covering layer 250 includes one or two of a dielectric material and a plastic package material, and the dielectric material may be silicon oxide, silicon nitride, or other dielectric materials.
In this embodiment, the material of the covering layer 250 is a plastic package material. Specifically, the material of the cover layer 250 may be epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, low cost and the like, and is widely used as a packaging material for electronic devices and integrated circuits.
As an example, the cover layer 250 may be formed using an injection molding (injection molding) process.
In this embodiment, the covering layer 250 also covers the surface of the second chip 200 facing away from the first chip 110, so as to bury the second chip 200, the first chip 110, the plated interconnection structure 31, the plated interconnection bumps 32 and the bonding wires 220, thereby being beneficial to improving the package reliability.
In other embodiments, the top surface of the cover layer may be flush with the surface of the second chip facing away from the first chip, or the cover layer may cover a portion of the sidewall of the second chip.
Correspondingly, the invention also provides a packaging structure. Fig. 6 is a schematic structural diagram of an embodiment of a package structure of the invention.
The package structure includes: a substrate (not shown), in which a first chip 110 is formed, the first chip 110 including a first surface 110a and a second surface 110b opposite to each other, the first surface 110a having a first interconnection electrode 130 and an external electrode 120 exposed and spaced apart from each other; a second chip 200 bonded to the first surface 110a of the first chip 110, wherein the surface of the second chip 200 has a second interconnection electrode 210 exposed, the second interconnection electrode 210 is opposite to the first interconnection electrode 130 in the vertical direction, and the second chip 200 exposes the external electrode 120; a bonding layer 140 between the second chip 200 and the first chip 110; a plated interconnection structure 31 which is located between the second interconnection electrode 210 and the first interconnection electrode 130 and electrically connects the second interconnection electrode 210 and the first interconnection electrode 130; the interconnection bumps 32 are plated to protrude from the surface of the external electrode 120.
The electroplated interconnection structure 31 and the electroplated interconnection bump 32 are formed by utilizing an electroplating process, so that the packaging structure can be obtained by a wafer-level packaging manner, and the surface of the external electrode 120 is usually lower than the surface of the first chip 110 under the influence of a chip manufacturing process, so that the electrical property of the external electrode 120 is led out through the electroplated interconnection bump 32, the electroplated interconnection bump 32 protrudes out of the surface of the external electrode 120, the routing process is easy to perform, the connection performance of a bonding wire and the electroplated interconnection bump 32 is higher, the performance of the packaging structure is improved, and the electroplated interconnection structure 31 and the electroplated interconnection bump 32 can be formed in the same step, so that the packaging efficiency is improved; in addition, the second chip 200 is bonded on the surface of the first chip 110, and the external electrode 120 is exposed, which can provide a receiving space for the bonding wire connected to the external electrode 120, so that the bonding wire is compatible with the three-dimensional stacked wafer-level package, which does not result in an increase in the height of the package structure, and has the advantages of simple routing process and low cost. In summary, the present embodiment improves the packaging efficiency and the packaging reliability and reduces the packaging cost while realizing the wafer level packaging.
In this embodiment, the package structure is obtained after dicing, and thus the substrate is a chip-scale substrate, that is, the substrate includes a first chip 110. In other embodiments, the package structure may also be an uncut structure, and accordingly, the substrate is a wafer-level substrate, that is, the substrate is a wafer, and a plurality of first chips are formed in the wafer.
In this embodiment, the first chip 110 is manufactured by using an integrated circuit manufacturing technology, and the first chip 110 includes a substrate. As an example, the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.
In this embodiment, the first chip 110 includes a first surface 110a and a second surface 110b opposite to each other. As an example, the second surface 110b is a bottom surface of a substrate in the first chip 110.
The first surface 110a of the first chip 110 has the first interconnection electrode 130 and the external connection electrode 120, and at the edge of the first surface 110a, the first interconnection electrode 130 and the external connection electrode 120 are exposed. The first interconnection electrode 130 and the external electrode 120 are interconnection lead pads (Pad) of the first chip 110, and are used for electrically connecting the first chip 110 with other chips or circuit structures.
In this embodiment, the package structure includes a chip module, the chip module includes a second chip 200 and a first chip 110 bonded together, and the external electrode 120 is used for leading out electrical characteristics of the chip module, so as to electrically connect the chip module with other substrates having a circuit structure.
In this embodiment, the first interconnection electrode 130 and the external connection electrode 120 are electrically connected to different circuit structures in the first chip 110.
In this embodiment, the plated interconnect structure 31 and the plated interconnect bump 32 are isolated according to the circuit design requirements, thereby achieving electrical isolation therebetween.
Therefore, the minimum distance between the first interconnection electrode 130 and the external connection electrode 120 is not excessively small. If the minimum pitch of the first interconnection electrode 130 and the external electrode 120 is too small, the plated interconnection structure 31 and the plated interconnection bump 32 are easily bridged (bridge) or merged (merge), thereby adversely affecting the package reliability. For this reason, in the present embodiment, the minimum pitch of the first interconnection electrode 130 and the external connection electrode 120 is 3 micrometers.
It should be noted that, in other embodiments, the first interconnection electrode may also be electrically connected to the external electrode according to the circuit design.
It should be noted that the exposed positions of the first interconnection electrode 130 and the external electrode 120 are protected by a dielectric layer (not labeled) to prevent short circuit, and the dielectric layer is etched to expose the first interconnection electrode 130 and the external electrode 120 during the manufacturing process of the first chip 110, so that the surfaces of the first interconnection electrode 130 and the external electrode 120 are lower than the first surface 110 a.
The second chip 200 may be one or more of an active element, a passive element, a micro electro mechanical system, an optical element, and the like. Specifically, the second chip 200 may be a functional chip such as a memory chip, a communication chip, a processing chip, a flash memory chip, or a logic chip.
In this embodiment, the second chip 200 is fabricated by using an integrated circuit fabrication technology, and the second chip 200 includes a substrate. The description of the substrate of the second chip 200 may refer to the foregoing description of the first chip 110, and is not repeated herein.
The surface of the second chip 200 has a second interconnection electrode 210, and at the edge of the surface of the second chip 200, the second interconnection electrode 210 is exposed, and the second interconnection electrode 210 is an interconnection wire pad of the second chip 200. In this embodiment, the second chip 200 includes a chip front surface and a chip back surface opposite to each other, and the second interconnection electrode 210 is located on the chip front surface, that is, the chip front surface exposes the second interconnection electrode 210. Wherein the chip back side refers to the bottom surface of the substrate in the second chip 200.
It should be noted that the second chip 200 may have a similar surface structure as the first chip 110, the exposed position of the second interconnection electrode 210 is protected by a dielectric layer (not labeled) to prevent short circuit, and the surface of the second interconnection electrode 210 is lower than the surface of the second chip 200.
It should be noted that the size of the second chip 200 is smaller than that of the first chip 110, so that the external electrode 120 of the first chip 110 is exposed.
The second chip 200 exposes the external electrode 120 of the first chip 110, so that the package structure can be compatible with a wire bonding process, that is, a receiving space can be provided for a bonding wire connected to the external electrode 120, so that the bonding wire is compatible with three-dimensional stacked wafer-level packages, and the increase of the height of the package structure cannot be caused.
The second interconnection electrode 210 of the second chip 200 and the first interconnection electrode 130 of the first chip 110 are vertically opposite to each other so as to electrically connect the second chip 200 and the first chip 110.
The bonding layer 140 is used for bonding the second chip 200 and the first chip 110. Furthermore, the bonding layer 140 has a thickness such that the second interconnection electrode 210 and the first interconnection electrode 130 are opposite to each other up and down to form a cavity for accommodating the plated interconnection structure 31.
In this embodiment, the bonding layer 140 has viscosity, so that adhesion bonding can be achieved, the bonding temperature of the adhesion bonding is low, which is beneficial to reducing the influence on the performance of the chip, and the process of the adhesion bonding is simple.
Specifically, the bonding layer 140 is made of a photosensitive material, so that patterning can be realized through a photolithography process, and damage to the electrode is reduced.
In this embodiment, the bonding layer 140 is a Dry Film (Dry Film). In other embodiments, other types of adhesive layers may be used, such as Die Attach Film (DAF).
It should be noted that the thickness of the bonding layer 140 is not too small, nor too large.
If the thickness of the bonding layer 140 is too small, the adhesion of the bonding layer 140 is insufficient, and the bonding strength between the second chip 200 and the first chip 110 is reduced.
Furthermore, the electroplated interconnection bumps 32 protrude from the first surface 110a of the first chip 110, so as to facilitate the wire bonding process. The thickness of the bonding layer 140 affects the height of the cavity, which in turn affects the height of the plated interconnect structure 31 and the plated interconnect bump 32, and the larger the height of the cavity, the larger the volume of the plated interconnect structure 31 and the plated interconnect bump 32. If the thickness of the bonding layer 140 is too small, the height of the cavity is easily too small, so that the difficulty of filling the cavity with an electroplating body when forming the electroplating interconnection structure 31 is increased, and the height of the electroplating interconnection bump 32 is easily too small, so that the difficulty of a routing process is difficult to significantly reduce; if the thickness is too large, the thickness of the package structure is too large, which is not favorable for the development of device miniaturization, and as the volumes of the plated interconnection structure 31 and the plated interconnection bump 32 become larger, the probability of bridging or fusion of the plated interconnection structure 31 and the plated interconnection bump 32 becomes higher. For this reason, in the present embodiment, the thickness of the bonding layer 140 is 5 to 50 micrometers.
It should be noted that, in other embodiments, other bonding manners may also be used to bond the second chip to the first chip, for example, the bonding manner is implemented by using a silicon oxide-silicon oxide fusion bonding manner. The corresponding bonding layer may also be a dielectric layer, for example a silicon oxide layer.
The plated interconnection structure 31 is used to realize an electrical connection between the first interconnection electrode 130 and the second interconnection electrode 210, thereby realizing an interconnection package of the second chip 200 and the first chip 110.
The plated interconnect bumps 32 electrically conduct the first chip 110 in preparation for a subsequent packaging process. Electrical connection of the first chip 110 to other substrates (e.g., circuit boards) can subsequently be achieved by electroplating the interconnect bumps 32, for example.
In this embodiment, the plating interconnection structure 31 and the plating interconnection bump 32 are formed by a plating process, and a good filling effect can be achieved in the cavity by the plating process, so that the reliability of electrical connection is improved.
Since the second chip 200 exposes the external electrodes 120 of the first chip 110, the external electrodes 120 are exposed to the process environment of the electroplating process, and thus the electroplating body fills the cavities and deposits on the external electrodes 120, thereby forming the electroplated interconnection bumps 32 on the surfaces of the external electrodes 120. The plated interconnection structure 31 and the plated interconnection bump 32 are formed in the same step, improving the package yield.
Wherein the cavity has a certain height, which makes the plated interconnection bump 32 have a certain height, and the plated interconnection bump 32 protrudes from the surface of the external electrode 120.
In this embodiment, the upper surface of the plated interconnection bump 32 is a flat surface, so as to ensure the bonding reliability of the bonding wire.
In this embodiment, the material of the plated interconnect structure 31 and the plated interconnect bump 32 are the same, and each includes one or more of copper, nickel, zinc, tin, silver, gold, tungsten, and magnesium.
In this embodiment, the package structure further includes: a substrate 300, the substrate 300 having a circuit structure 310 therein; the wire bonds 220 electrically connect the plated interconnect bumps 32 with the circuit structure 310 in the substrate 300. The second surface 110b of the first chip 110 is adhered to the substrate 300.
The wire bonds 220 enable electrical connection of the plated interconnect bumps 32 with the circuit structure 310, thereby enabling system integration of the substrate 300 and the individual chip module constituted by the first chip 110 and the second chip 200. The second surface 110b is adhered to the substrate 300, and the first chip 110 and the substrate 300 are electrically connected by the bonding wire 220, so as to provide a circuit signal to the chip module by using the circuit structure 310 in the substrate 300, or to electrically connect the chip module with another chip or another substrate by using the circuit structure 310 in the substrate 300.
In this embodiment, the substrate 300 may be a Printed Circuit Board (PCB). In other embodiments, the substrate may also be a flexible printed circuit board (FPC) or an interposer (interposer) board or other types of substrates.
In this embodiment, the package structure further includes: and an adhesive layer 230 between the first chip 110 and the substrate 300. The adhesive layer 230 has adhesiveness for fixing the chip module to the substrate 300, and the adhesive layer 230 may be a sheet adhesive film as an example.
The bonding wires 220 are formed by a wire bonding process. The wire bonding process is the most commonly used circuit connection method in the integrated circuit packaging process, and the wire bonding process is used for sequentially bonding thin metal wires or metal strips on bonding points of a chip and a lead frame or a packaging substrate to form circuit connection. The wire bonding process has higher compatibility with the current packaging process, and has the advantages of simple process and low cost, so that the packaging cost of the packaging structure is lower.
In this embodiment, the bonding wires 220 are metal wires, such as: gold or aluminum wires.
In this embodiment, the highest position of the bonding wire 220 is lower than the surface of the second chip 200 facing away from the first chip 110. When forming the cover layer covering at least the plated interconnection structure 31, the plated interconnection bump 32, and the bonding wire 220, by making the highest point of the bonding wire 220 lower than the surface of the second chip 200 facing away from the first chip 110, it is possible to bury all the plated interconnection structure 31, the plated interconnection bump 32, and the bonding wire 220 in the cover layer, and at the same time, it is easy to make the thickness of the package structure small.
In other embodiments, the highest point of the bonding wire may be flush with the surface of the second chip facing away from the chip.
In this embodiment, the package structure further includes: and a cover layer 250 covering at least the plated interconnect structure 31, the plated interconnect bump 32, and the wire bond 220.
The cover layer 250 serves to fix the first chip 110 and the second chip 200, so as to integrate the first chip 110 and the second chip 200 into a package. Furthermore, the cover layer 250 serves to achieve insulation, sealing and protection of the plated interconnect structure 31, the plated interconnect bumps 32 and the bonding wires 220.
Therefore, the material of the covering layer 250 is an insulating material, the material of the covering layer 250 includes one or two of a dielectric material and a plastic package material, and the dielectric material may be silicon oxide, silicon nitride or other dielectric materials.
In this embodiment, the material of the covering layer 250 is a plastic package material. Specifically, the material of the cover layer 250 may be epoxy resin. Epoxy resin has the advantages of low shrinkage, good adhesion, good corrosion resistance, excellent electrical properties, low cost and the like, and is widely used as a packaging material for electronic devices and integrated circuits.
In this embodiment, the covering layer 250 also covers the surface of the second chip 200 facing away from the first chip 110, so as to bury the second chip 200, the first chip 110, the plated interconnection structure 31, the plated interconnection bumps 32 and the bonding wires 220, thereby being beneficial to improving the package reliability. In other embodiments, the top surface of the cover layer may be flush with the surface of the second chip facing away from the first chip, or the cover layer may cover a portion of the sidewall of the second chip.
It should be noted that the present embodiment is described by taking the case where the plated interconnect structure 31 is isolated from the plated interconnect bump 32. In other embodiments, the plated interconnect structure and the plated interconnect bump may also be in contact or merged when the first interconnect electrode and the external electrode need to be electrically connected according to circuit design requirements.
The package structure may be formed by the package method described in the foregoing embodiment, or may be formed by other package methods. For a specific description of the package structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A wafer level packaging method, comprising:
providing a first device wafer formed with a plurality of first chips, wherein each first chip comprises a first surface and a second surface which are opposite, and the first surface is provided with a first interconnection electrode and an external electrode which are exposed and spaced;
providing a plurality of second chips, wherein the surfaces of the second chips are provided with exposed second interconnection electrodes;
bonding the second chip on the first surface of the first chip by using a bonding layer, wherein the second interconnection electrode and the first interconnection electrode are opposite up and down and enclose a cavity, and the second chip exposes the external electrode;
and after bonding, forming an electroplating interconnection structure filled in the cavity and an electroplating interconnection bump protruding out of the surface of the external electrode.
2. The wafer-level packaging method of claim 1, wherein after forming the plated interconnect structures and plated interconnect bumps, the wafer-level packaging method further comprises: and cutting the first device wafer to form a chip module, wherein the chip module comprises the second chip and the first chip which are bonded together.
3. The wafer-level packaging method of claim 2, wherein after dicing the first device wafer, the wafer-level packaging method further comprises: bonding the second surface of the first chip to a substrate, wherein the substrate is provided with a circuit structure;
and forming a bonding wire by using a routing process, wherein the bonding wire is electrically connected with the electroplated interconnection bump and the circuit structure in the substrate.
4. The wafer-level packaging method of claim 1, wherein a minimum pitch of the first interconnection electrode and the external electrode is 3 μm.
5. The wafer level packaging method of claim 1, wherein the bonding layer has a thickness of 5 to 50 microns.
6. The wafer-level packaging method of claim 1, wherein an upper surface of the plated interconnect bumps is a flat surface.
7. The wafer level packaging method as claimed in claim 3, wherein the highest position of the bonding wire is flush with the surface of the second chip facing away from the first chip, or the highest position of the bonding wire is lower than the surface of the second chip facing away from the first chip.
8. The wafer-level packaging method of claim 1, wherein the plated interconnect structures and plated interconnect bumps are formed using an electroplating process, the electroplating process being an electroless plating process.
9. The wafer-level packaging method of claim 1, wherein each of the second chips is individually bonded to a corresponding first chip on the first device wafer;
alternatively, the first and second electrodes may be,
in the step of providing the plurality of second chips, the second chips are located in a second device wafer;
in the step of bonding, the second device wafer is bonded to the first device wafer.
10. The wafer-level packaging method of claim 9, wherein prior to forming the plated interconnect structures and plated interconnect bumps, the wafer-level packaging method further comprises: and cutting the second device wafer and separating each second chip.
11. The wafer level packaging method of claim 1, wherein bonding is achieved using an optical alignment process.
12. The wafer level packaging method of claim 1, wherein the material of the bonding layer comprises a dry film or a sticky film.
13. A package structure, comprising:
the chip comprises a substrate, a first chip and a second chip, wherein the substrate is provided with the first chip, the first chip comprises a first surface and a second surface which are opposite, and the first surface is provided with a first interconnection electrode and an external electrode which are exposed and spaced;
the second chip is bonded on the first surface of the first chip, the surface of the second chip is provided with a second exposed interconnection electrode, the second interconnection electrode is opposite to the first interconnection electrode in the vertical direction, and the second chip exposes the external electrode;
the bonding layer is positioned between the second chip and the first chip;
a plated interconnect structure between and electrically connecting the second interconnect electrode and the first interconnect electrode;
and electroplating the interconnection convex block to protrude out of the surface of the external electrode.
14. The package structure of claim 13, wherein the substrate is a chip-scale substrate;
the package structure further includes: a substrate having a circuit structure therein; a bonding wire electrically connecting the plated interconnect bump and a circuit structure in the substrate;
wherein the second surface of the first chip is bonded to the substrate.
15. The package structure of claim 13, wherein the first interconnect electrode and the external electrode have a minimum pitch of 3 microns.
16. The package structure of claim 13, wherein the bonding layer has a thickness of 5 to 50 microns.
17. The package structure of claim 13, wherein an upper surface of the plated interconnect bump is a planar surface.
18. The package structure of claim 14, wherein a highest point of the bonding wire is flush with a surface of the second chip facing away from the first chip, or the highest point of the bonding wire is lower than a surface of the second chip facing away from the first chip.
19. The package structure of claim 13, wherein the material of the bonding layer comprises a dry film or a die attach film.
20. The package structure of claim 14, wherein the package structure further comprises: a cover layer at least covering the electroplated interconnection structure, the electroplated interconnection bump and the bonding wire.
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Cited By (2)

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Publication number Priority date Publication date Assignee Title
CN113539861A (en) * 2021-07-16 2021-10-22 芯知微(上海)电子科技有限公司 Heterogeneous bare chip system integrated chip structure and manufacturing method thereof
CN116544228A (en) * 2023-07-06 2023-08-04 广东致能科技有限公司 Wafer-level cascode device, chip and preparation method thereof

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Publication number Priority date Publication date Assignee Title
CN113539861A (en) * 2021-07-16 2021-10-22 芯知微(上海)电子科技有限公司 Heterogeneous bare chip system integrated chip structure and manufacturing method thereof
CN116544228A (en) * 2023-07-06 2023-08-04 广东致能科技有限公司 Wafer-level cascode device, chip and preparation method thereof

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