CN113923108A - Method, system, equipment and storage medium for automatically configuring time delay parameters - Google Patents
Method, system, equipment and storage medium for automatically configuring time delay parameters Download PDFInfo
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Abstract
The invention provides a method, a system, equipment and a storage medium for automatically configuring time delay parameters, which are used for solving the technical problem that the experimental parameters for configuring a network interface cannot be automatically adjusted in the prior art, and the method for automatically configuring the time delay parameters comprises the following steps: sequentially sending a plurality of different delay durations which can be used by the PHY chip to the PHY chip in different time periods, so that the PHY chip uses the corresponding delay durations to delay time sequence signals in the PHY chip in the corresponding time periods; receiving test data sent by the PHY chip in each time period, and recording the number of error frames generated by communication between the MAC and the PHY chip in the corresponding time period; and setting the delay time corresponding to the time period with the minimum number of error frames in all time periods as the final delay time used by the PHY chip.
Description
Technical Field
The present invention relates to the field of network interface technologies, and in particular, to a method, a system, a device, and a storage medium for automatically configuring a delay parameter.
Background
Currently, an ethernet link of a network device such as NVR (network video recorder) and IP Camera (IPC) generally comprises a Central Processing Unit (CPU), a Media Access Control (MAC) Layer and a Physical Layer (PHY). Since the MAC is typically a digital circuit and the PHY contains a large number of analog devices, the MAC is typically integrated within the CPU while the PHY remains external to the CPU. Signals are transmitted between the MAC and the PHY through Media Independent Interfaces (MIIs), simplified Media Independent interfaces (RMII), Gigabit Media Independent Interfaces (GMII), simplified Gigabit Media Independent interfaces (RGMII) and other interfaces.
When designing a product, a signal in an interface between the MAC and the PHY needs to configure a clock delay parameter according to a condition of Printed Circuit Board Assembly (PCBA), so that the signal meets a timing sequence and signal quality required by an interface protocol. However, a large amount of manpower and material resources are required to be consumed for manually measuring different parameters, and some platforms cannot detect signal waveforms through equipment such as an oscilloscope and the like.
In view of this, how to automatically adjust and configure the delay parameter of the network interface becomes a technical problem to be solved urgently.
Disclosure of Invention
The invention provides a method, a system, equipment and a storage medium for automatically configuring a time delay parameter, which are used for solving the technical problem that the experimental parameter for configuring a network interface cannot be automatically adjusted in the prior art.
A first aspect of the present invention provides a method for automatically configuring a delay parameter, configured to set a delay duration of a timing signal in a physical layer chip, where the method includes:
sequentially sending a plurality of different delay durations which can be used by the physical layer chip to the physical layer chip by different time periods, so that the physical layer chip uses the corresponding delay durations to delay time sequence signals in the physical layer chip in the corresponding time period;
receiving test data sent by the physical layer chip of a medium access control layer in each time period, and recording the number of error frames generated by communication between the medium access control layer and the physical layer chip in the corresponding time period;
and setting the delay time corresponding to the time period with the minimum number of error frames in all time periods as the final used delay time of the physical layer chip.
Optionally, before sequentially sending a plurality of different delay durations usable by the physical layer chip to the physical layer chip through the time-divided durations, the method further includes: and setting the time length of the time period corresponding to each delay time length to be the same.
Optionally, the sequentially sending a plurality of different delay durations usable by the physical layer chip to the physical layer chip through the time-divided durations includes:
before each time slot starts, corresponding delay time is sent to the physical layer chip through the time slot until all the delay time is sent; wherein at most one delay duration is sent within the same time period.
Optionally, in each time period, receiving, by the mac layer, test data sent by the physical layer chip, and recording the number of error frames generated by communication between the mac layer and the physical layer chip in the corresponding time period, includes:
receiving test data sent by the physical layer chip, and carrying out frame check sequence (frame check sequence) detection on each data frame of the test data; the test data is received when the test data transmitted by the physical layer chip reaches the transmission upper limit of an interface;
when the data frame can not pass the frame check sequence detection, determining the data frame as an error frame;
and recording the number of all error frames in the test data received in the corresponding time period.
Optionally, performing frame check sequence (frame check sequence) detection on each data frame of the test data, including:
detecting a frame check sequence field in each data frame, and acquiring a first cyclic redundancy check (cyclic redundancy check) result carried in the frame check sequence field;
performing cyclic redundancy check calculation on the data frame to obtain a second cyclic redundancy check calculation result, and comparing the second cyclic redundancy check calculation result with the first cyclic redundancy check result;
if a plurality of first cyclic redundancy check results are different from the second cyclic redundancy check calculation result, determining that the data frame does not pass frame check sequence detection;
and if the first cyclic redundancy check result is the same as the second cyclic redundancy check calculation result, determining that the data frame passes the frame check sequence detection.
Optionally, setting a delay duration corresponding to a time period in which the number of the error frames is the minimum in all time periods as a delay duration finally used by the physical layer chip, includes:
when a plurality of different delay time lengths which can be used by the physical layer chip are all sent to the physical layer chip and all test data sent by the physical layer chip in time periods corresponding to all the delay time lengths are received, reading the number of error frames sent by the physical layer chip in the corresponding time periods under the plurality of different delay time lengths;
and sequencing the different delay durations according to the number of error frames, acquiring the delay duration used by the physical layer chip when the number of the error frames is minimum, and setting the delay duration as the delay duration finally used by the physical layer chip.
Optionally, the method for automatically configuring a delay parameter further includes: and when the number of the error frames generated in any time period is determined to be 0 frame, determining the corresponding delay time to be the optimal delay time, directly setting the optimal delay time to be the delay time finally used by the physical layer chip, and stopping sending the delay time to the physical layer chip.
In a second aspect, an embodiment of the present application provides a system for automatically configuring a delay parameter, including:
the parameter adjusting unit is used for sequentially sending a plurality of different delay durations which can be used by the physical layer chip to the physical layer chip through the time periods, so that the physical layer chip uses the corresponding delay durations to delay the time sequence signals in the physical layer chip in the corresponding time period;
the data processing unit is used for receiving the test data sent by the physical layer chip through the medium access control layer in each time period and recording the number of error frames generated by communication between the medium access control layer and the physical layer chip in the corresponding time period;
and the parameter determining unit is used for setting the delay time corresponding to the time period with the minimum number of error frames in all time periods as the delay time finally used by the physical layer chip.
Optionally, the parameter adjusting unit is further configured to:
and setting the time length of the time period corresponding to each delay time length to be the same.
Optionally, the parameter adjusting unit is further configured to:
before each time slot starts, corresponding delay time is sent to the physical layer chip through the time slot until all the delay time is sent; wherein at most one delay duration is sent within the same time period.
Optionally, the data processing unit is further configured to:
receiving the test data sent by the physical layer chip, and carrying out frame check sequence detection on each data frame of the test data;
when the data frame can not pass the frame check sequence detection, determining the data frame as an error frame;
and recording the number of all error frames in the test data received in the corresponding time period.
Optionally, the data processing unit is further configured to:
detecting a frame check sequence field in each data frame, and acquiring a first cyclic redundancy check result carried in the frame check sequence field;
performing cyclic redundancy check calculation on the data frame to obtain a second cyclic redundancy check calculation result, and comparing the second cyclic redundancy check calculation result with the first cyclic redundancy check result;
if a plurality of first cyclic redundancy check results are different from the second cyclic redundancy check calculation result, determining that the data frame does not pass frame check sequence detection;
and if the first cyclic redundancy check result is the same as the second cyclic redundancy check calculation result, determining that the data frame passes the frame check sequence detection.
Optionally, the parameter determining unit is further configured to:
when a plurality of different delay time lengths which can be used by the physical layer chip are all sent to the physical layer chip and all test data sent by the physical layer chip in time periods corresponding to all the delay time lengths are received, reading the number of error frames sent by the physical layer chip in the corresponding time periods under the plurality of different delay time lengths;
sequencing the different delay durations according to the number of error frames, and acquiring the delay duration used by the physical layer chip when the number of the error frames is minimum;
and setting the delay time length as the delay time length finally used by the physical layer chip.
Optionally, the parameter determining unit is further configured to:
and when the number of the error frames generated in any time period is determined to be 0 frame, determining the corresponding delay time to be the optimal delay time, directly setting the optimal delay time to be the delay time finally used by the physical layer chip, and stopping sending the delay time to the physical layer chip.
In a third aspect, an embodiment of the present application provides a system for automatically configuring a delay parameter, including:
a device under test for performing the method as described in the first aspect.
And the pressure test equipment is connected with the equipment to be tested through a network cable and is used for providing test data for the equipment to be tested and achieving the maximum bandwidth of the current network.
In a fourth aspect, an embodiment of the present application provides an apparatus for automatically configuring a delay parameter, including: a central processing unit having a medium access control layer chip thereon, the central processing unit being further configured to perform the method according to the first aspect;
the medium access control layer chip is connected with the physical layer chip through a first interface and transmits data;
the physical layer chip is used for receiving network data.
The technical scheme in the embodiment of the invention has the following beneficial effects: the CPU of the device to be tested sequentially sends a plurality of different delay durations which can be used by the physical layer chip to the physical layer chip by time intervals, so that the physical layer chip uses the corresponding delay durations to delay time sequence signals in the physical layer chip in the corresponding time intervals. Then, the CPU of the device to be tested receives the test data sent by the physical layer chip in each time period, and records the number of error frames generated by communication between the medium access control layer and the physical layer chip in the corresponding time period. And finally, the CPU of the device to be tested sets the delay time corresponding to the time period with the minimum number of error frames in all time periods as the delay time finally used by the physical layer chip. The device to be tested can test by itself and select the delay time with the best signal effect sent by the physical layer chip as the delay time for final use. The method reduces the manpower and material resource loss required by manually measuring the signal quality under different time delay parameters, and enables the network interface between the medium access control layer and the physical layer to always transmit signals with the best network effect.
Drawings
Fig. 1 is a flowchart of a method for automatically configuring a delay parameter according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a system for automatically configuring a delay parameter according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating an automatic configuration of delay parameters provided by an embodiment of the present invention;
fig. 4 is a schematic diagram of a structure of a MAC frame according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a record of error frame data according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an automatic configuration delay parameter system according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another system for automatically configuring a delay parameter according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of an apparatus for automatically configuring a delay parameter according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application.
In the prior art, because the conditions of Printed Circuit Board Assemblies (PCBA) of different products are often different, in order to ensure that signals in an interface between a Media Access Control (MAC) Layer and a Physical Layer (PHY) meet the requirements of an interface protocol, technicians manually measure the signal quality of the signals in the interface between the MAC Layer and the PHY Layer under different parameters through devices such as an oscilloscope and the like, and judge whether the interface protocol is met, but this method needs to consume a large amount of manpower and material resources. And on some platforms, such as CPU platforms like haisi, clock signals and data signals are sent in alignment, so that technicians cannot directly measure delay parameters of the signals through an oscilloscope.
Therefore, the invention provides a method, a system, equipment and a computer storage medium for automatically configuring a time delay parameter, which are used for solving the technical problem that the time delay parameter of a network interface cannot be automatically adjusted and configured in the prior art.
The technical scheme provided by the embodiment of the application is described in the following with the accompanying drawings of the specification.
Referring to fig. 1, the present invention provides a method for automatically configuring a delay parameter, which is applied to a Central Processing Unit (CPU) of a device to be tested, referring to fig. 2, fig. 2 is a schematic structural diagram of a system for automatically configuring a delay parameter according to an embodiment of the present invention, and a specific flow of the method is described as follows:
And 102, receiving the test data sent by the physical layer chip in each time period, and recording the number of error frames generated by communication between the medium access control layer and the physical layer chip in the corresponding time period.
And 103, setting the delay time corresponding to the time period with the minimum number of error frames in all time periods as the final delay time used by the physical layer chip.
Wherein, can use a plurality of different time delay duration with the physical layer chip, before sending the physical layer chip in proper order to the timesharing, still include: and setting the time duration of the time period corresponding to each delay time duration to be the same.
Wherein, it is long with the usable a plurality of different delays of physical layer chip, sends physical layer chip in proper order for the timesharing, includes: before each time period starts, the corresponding delay time length is sent to the physical layer chip until all the delay time lengths are sent; wherein at most one delay duration is sent within the same time period.
For example, referring to fig. 3, fig. 3 is a schematic diagram of an automatic configuration delay parameter according to an embodiment of the present invention. Fig. 3 includes a device to be tested and a test device, where the device to be tested and the test device are connected to each other through a network cable, and the device to be tested further includes a Physical Layer (PHY) chip, and the PHY chip and a media access control Layer (media access control) in a Central Processing Unit (CPU)control, MAC) is connected through a first interface to receive data, and a second interface is provided between the CPU and the PHY chip to allow the CPU to set a delay time of a timing signal in the PHY chip. The device to be tested can be Network devices such as a Network Video Recorder (NVR), a Network CAMERA (IP Camera), various embedded systems and the like, and the test device can be computer devices such as a personal computer, a server and the like. The device to be tested comprises a CPU301 and a PHY chip 3021, signals are transmitted between the MAC3011 and the PHY chip 3021 of the CPU301 through a Media Independent Interface (MII), and the CPU301 further transmits a signal through an Integrated Circuit bus (I-Integrated Circuit, I)2C) The delay time used when the PHT chip 3021 transmits signals through the MII interface is set. The CPU301 further includes an error frame register 3012 for recording the number of error frames generated by communication between the MAC3011 and the PHY chip 3021.
It is assumed that the test device continuously sends test data to the PHY chip 3021 of the device under test through the network cable, the PHY chip 3021 of the device under test sends the test data to the MAC3011 in the CPU301 through the MII interface, at this time, a signal transmitted through the MII interface reaches an upper limit, and the time duration of the time period set by the CPU301 is 10 min. The available delay time of the PHY chip is three, which are 1ns, 2ns and 3 ns.
CPU301 through I2The C bus sends the first available delay time of PHY chip 3021 to PHY chip 3021 in 1ns, and PHY chip 3021 transmits 10min of data to MAC3011 using a delay time of 1 ns. In the corresponding first 10min period, the CPU301 detects that 6 error data frames have occurred in the data transmitted from the PHY chip 3021 to the MAC 3011. When the first 10min is over, the CPU301 passes I2The C bus sends the second available delay time duration of PHY chip 3021 to PHY chip 3021 of 2ns, and PHY chip 3021 transmits 10min of data to MAC3011 using a delay time duration of 2 ns. In the corresponding second 10min period, the CPU detects 3 erroneous data frames. When the second 10min is over, the CPU301 passes I2The C bus sends the third available delay time of the PHY chip 3021 to the PHY chip 3021 for 3ns, and the PHY chip 3021 transmits 10min of data to the MAC3011 using a delay time of 3 ns. And at a corresponding third time of 10minIn the section, the CPU detects that 9 error frames are received in the data transmitted from the PHY chip 3021.
When all three delay time lengths are sent, and the number of error frames generated by communication between the MAC3011 and the PHY chip 3021 in a corresponding time period is recorded, the CPU301 detects that the time period in which the generated error frames are the minimum is the second 10min time period, and only 3 error frames are generated. The CPU301 sets the delay time period 2ns used in the second 10min period as the delay time period of the final use of the PHY chip 3021.
In practical applications, the first Interface may include a Media Independent Interface (MII), a Reduced Media Independent Interface (RMII), a Gigabit Media Independent Interface (GMII), a Reduced Gigabit Media Independent Interface (RGMII), a Ten Bit Interface (Ten Bit Interface, TBI), XAUI (10Gigabit Attachment Unit Interface, XAUI), and other communication interfaces between the MAC and the PHY, and the second Interface may be an Integrated Circuit bus (Inter-Integrated Circuit, I)2C) And a Serial Peripheral Interface (SPI) bus used for transmitting information from the CPU to the PHY chip.
In the embodiment provided by the invention, the CPU of the device to be tested sequentially sends a plurality of different delay durations which can be used by the PHY chip to the PHY chip through the second interface in different time periods, so that the PHY chip uses the corresponding delay durations to delay the time sequence signals in the PHY chip in the corresponding time periods. Then, the CPU of the device to be tested receives the test data sent by the PHY chip through the MAC in each time period, and records the number of error frames generated by communication between the MAC and the PHY chip in the corresponding time period. And finally, the CPU of the device to be tested sets the delay time corresponding to the time period with the minimum number of error frames in all time periods as the delay time finally used by the PHY chip. The device to be tested can test by itself and select the delay time with the best signal effect sent by the PHY chip as the delay time for final use. The method reduces the manpower and material resource loss required by manually measuring the signal quality under different time delay parameters, and enables the network interface between the MAC layer and the PHY layer to always transmit signals with the best network effect.
One possible implementation manner, in each time period, receiving test data sent by the physical layer chip through the medium access control layer, and recording the number of error frames generated by communication between the medium access control layer and the physical layer chip in the corresponding time period, includes:
receiving test data sent by a physical layer chip through a first interface, and carrying out frame check sequence detection on each data frame of the test data; the test data is received when the test data transmitted by the physical layer chip reaches the transmission upper limit of the first interface; when the data frame can not pass the frame check sequence detection, determining the data frame as an error frame; and recording the number of all error frames in the test data received in the corresponding time period.
Wherein performing frame check sequence (frame check sequence) detection on each data frame of the test data comprises: detecting a frame check sequence field in each data frame, and acquiring a first cyclic redundancy check result carried in the frame check sequence field; performing cyclic redundancy check calculation on the data frame to obtain a second cyclic redundancy check calculation result, and comparing the second cyclic redundancy check calculation result with the first cyclic redundancy check result; if the first cyclic redundancy check result is different from the second cyclic redundancy check calculation result, determining that the data frame does not pass the frame check sequence detection; and if the first cyclic redundancy check result is the same as the second cyclic redundancy check calculation result, determining that the data frame passes the frame check sequence detection.
For example, taking the example in fig. 3 as an example, assuming that the preset time period is 10min, at which the test data sent by the PHY chip 3021 through the MII interface has reached the transmission upper limit of the MII interface, it is assumed that the CPU301 receives two frames of data within one time period. As shown in fig. 4, fig. 4 is a schematic structural diagram of a MAC frame according to an embodiment of the present invention, where a MAC frame includes a frame header portion, a data portion, and a frame tail portion, and the frame tail portion includes a Frame Check Sequence (FCS).
The CPU301 of the device under test receives test data sent by the PHY chip 3021 to the MAC3011 via the MII interface, and performs FCS detection on each data frame. The CPU301 performs Cyclic Redundancy Check (CRC) calculation on the frame header portion and the data portion in the first data frame to obtain a second CRC calculation result, where the calculation result is a. Meanwhile, the CPU301 reads the end of frame part in the data frame, where the frame check sequence is the first CRC result, and the first CRC result is a. The CPU301 compares the first CRC result and the second CRC calculation result, determines that the two results are different, and determines that the data frame is an error frame and fails FCS detection.
The CPU301 performs CRC calculation on the frame header portion and the data portion in the second data frame to obtain a second CRC calculation result, which is B. Meanwhile, the CPU301 reads the end of frame part in the data frame, where the frame check sequence is the first CRC result, and the first CRC result is B. The CPU301 compares the first CRC result and the second CRC calculation result, determines that both results are the same, and determines that the data frame passes FCS detection.
After the FCS detection is performed on both frames of data, the CPU301 of the device under test records that the data of the error frame is 1 frame in the test data received in the time period.
In the embodiment provided by the invention, the CPU of the equipment to be tested searches the error frames in each frame data by performing FCS detection on the data of each frame, and the number of the error frames is taken as a reference object for measuring the signal quality, so that the signal quality is quantized into values which can be compared with each other, and the CPU of the equipment to be tested is convenient to select the delay parameter with the best signal quality.
One possible implementation manner, setting a delay duration corresponding to a time period with the least number of error frames in all time periods as a delay duration finally used by a physical layer chip, includes:
when a plurality of different delay time lengths which can be used by the physical layer chip are all sent to the physical layer chip, and all test data sent by the physical layer chip in time periods corresponding to all the delay time lengths are received, reading the number of error frames sent by the physical layer chip in the corresponding time periods under the plurality of different delay time lengths; sorting a plurality of different delay durations according to the number of error frames, and acquiring the delay duration used by the physical layer chip when the number of error frames is minimum; and setting the delay time length as the delay time length finally used by the physical layer chip.
For example, in the example shown in fig. 3, it is assumed that the delay time available to the PHY chip 3021 is 3 in total, including 1ns, 2ns, and 3 ns. The duration of the preset time period set by the CPU301 of the device under test is 10 min.
When the CPU301 of the device under test sends all the three delay times to the PHY chip 3021, and records the number of error frames sent by the PHY chip 3021 in the time period corresponding to the three delay times, the CPU301 of the device under test reads the number of error frames sent in the time period corresponding to the three delay times. As shown in fig. 5, fig. 5 is a schematic diagram of recording of error frame data according to an embodiment of the present invention. When the delay time is set to 1ns, the PHY chip 3021 sends 10min of test data to the MAC3011, where 6 error frames are detected; when the delay time is set to 2ns, the PHY chip 3021 sends 10min of test data to the MAC3011, where 3 error frames are detected; when the delay time period is set to 3ns, the PHY chip 3021 transmits test data for 10min to the MAC3011, where 9 error frames are detected. And sequencing the three delay durations according to the number of the error frames detected in the corresponding time periods, wherein the sequencing results are 2ns (3), 1ns (6) and 3ns (9). Therefore, when the CPU301 of the device under test minimizes the error frame (3 error frames), the delay time 2ns used by the PHY chip 3021 is set as the delay time finally used by the PHY chip 3021.
In the embodiment provided by the invention, the CPU of the device to be tested sets the delay time when the error frame is minimum as the delay time finally used by the PHY chip. The PHY chip can use the delay parameter with the best transmission effect to send data to the MAC.
In a possible implementation manner, the method for automatically configuring a delay parameter further includes: and when the number of error frames generated in any time period is determined to be 0 frame, determining the corresponding delay time to be the optimal delay time, directly setting the optimal delay time to be the delay time finally used by the physical layer chip, and stopping sending the delay time to the physical layer chip.
For example, taking the example in fig. 3 as an example, assuming that the set time period is 10min, there are 4 delay times that can be used by the PHY chip, which are 1ns, 2ns, 3ns, and 4ns, respectively. The CPU301 of the device under test sends a delay time to the PHY chip 3021 every 10min, and detects an error frame in the test data sent by the PHY chip 3021 in a time period corresponding to the delay time. In the first time period, the PHY chip sends 10min of test data using a delay time of 1ns, and the CPU301 records 6 error frames. In the second time period, the PHY chip sends 10min of test data with a delay time of 2ns, and the CPU301 records 3 error frames. In the third time period, the PHY chip sends 10min of test data with a delay time of 3ns, and the CPU301 records 0 error frame. At this time, the CPU301 determines that 3ns is the optimal delay time of the PHY chip 3021, directly sets the optimal delay time 3ns as the delay time finally used by the PHY chip 3021, and does not send the delay time of 4ns to the PHY chip 3021 any more.
In the embodiment provided by the invention, when the CPU of the device to be tested detects a certain delay time, the PHY chip sends the signal with the best quality and no error frame, the delay time is directly set as the delay time finally used by the PHY chip, and the testing of other delay times is stopped. The time required for testing is reduced and computing resources are saved.
Based on the same inventive concept, the present application provides a system for automatically configuring a delay parameter, referring to fig. 6, the system for automatically configuring a delay parameter includes:
a parameter adjusting unit 601, configured to sequentially send a plurality of different delay durations that can be used by the physical layer chip to the physical layer chip through the second interface in different time periods, so that the physical layer chip uses the corresponding delay durations to delay the timing signal in the physical layer chip in the corresponding time period;
a data processing unit 602, configured to receive, in each time period, test data sent by the physical layer chip through the medium access control layer, and record the number of error frames generated by communication between the medium access control layer and the physical layer chip in a corresponding time period;
the parameter determining unit 603 is configured to set a delay duration corresponding to a time period with the minimum number of error frames in all time periods as a delay duration finally used by the physical layer chip.
In a possible implementation, the parameter adjusting unit 601 is further configured to:
and setting the time duration of the time period corresponding to each delay time duration to be the same.
In a possible implementation, the parameter adjusting unit 601 is further configured to:
before each time period starts, the corresponding delay time length is sent to the physical layer chip through the second interface until all the delay time lengths are sent; wherein at most one delay duration is sent within the same time period.
In one possible implementation, the data processing unit 602 is further configured to:
receiving test data sent by a physical layer chip through a first interface, and carrying out frame check sequence detection on each data frame of the test data; when the data frame can not pass the frame check sequence detection, determining the data frame as an error frame; and recording the number of all error frames in the test data received in the corresponding time period.
In one possible implementation, the data processing unit 602 is further configured to:
detecting a frame check sequence field in each data frame, and acquiring a first cyclic redundancy check result carried in the frame check sequence field; performing cyclic redundancy check calculation on the data frame to obtain a second cyclic redundancy check calculation result, and comparing the second cyclic redundancy check calculation result with the first cyclic redundancy check result; if the majority of the first cyclic redundancy check results are different from the second cyclic redundancy check calculation results, determining that the data frame does not pass the frame check sequence detection; and if the first cyclic redundancy check result is the same as the second cyclic redundancy check calculation result, determining that the data frame passes the frame check sequence detection.
In one possible implementation, the parameter determining unit 603 is further configured to:
when a plurality of different delay time lengths which can be used by the physical layer chip are all sent to the physical layer chip, and all test data sent by the physical layer chip in time periods corresponding to all the delay time lengths are received, reading the number of error frames sent by the physical layer chip in the corresponding time periods under the plurality of different delay time lengths; sorting a plurality of different delay durations according to the number of error frames, and acquiring the delay duration used by the physical layer chip when the number of error frames is minimum; and setting the delay time length as the delay time length finally used by the physical layer chip.
In a possible implementation, the parameter determining unit 603 is further configured to:
when the number of error frames generated in any time period is determined to be 0 frame, the corresponding delay time is determined to be the optimal delay time, the optimal delay time is directly set to be the delay time finally used by the physical layer chip, and the delay time is stopped being sent to the physical layer chip
Based on the same inventive concept, the present application provides a system for automatically configuring a delay parameter, referring to fig. 7, the system for automatically configuring a delay parameter includes:
the device under test 701 is configured to execute the method for automatically configuring the time delay parameter.
And the pressure test equipment 702 is connected with the equipment to be tested through a network cable, and is used for providing test data for the equipment to be tested and achieving the maximum bandwidth of the current network.
Based on the same inventive concept, an embodiment of the present invention provides an apparatus for automatically configuring a delay parameter, and referring to fig. 8, the apparatus for automatically configuring a delay parameter includes:
a central processing unit 801, on which a medium access control layer chip 802 is included, and the central processing unit is further configured to execute the method for automatically configuring the delay parameter as described above;
the medium access control layer chip 802 is connected with the physical layer chip 803 through a first interface and transmits data;
the physical layer chip 803 is configured to receive network data.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A method for automatically configuring a delay parameter, configured to set a delay duration of a timing signal in a physical layer chip, the method comprising:
sequentially sending a plurality of different delay durations which can be used by the physical layer chip to the physical layer chip in different time periods, so that the physical layer chip uses the corresponding delay durations to delay time sequence signals in the physical layer chip in the corresponding time period;
receiving test data sent by the physical layer chip in each time period, and recording the number of error frames generated by communication between the medium access control layer and the physical layer chip in the corresponding time period;
and setting the delay time corresponding to the time period with the minimum number of error frames in all time periods as the final used delay time of the physical layer chip.
2. The method of claim 1, wherein sequentially sending a plurality of different delay time periods available to the physical layer chip in time periods to the physical layer chip, further comprises:
and setting the time length of the time period corresponding to each delay time length to be the same.
3. The method of claim 1, wherein sequentially sending a plurality of different delay durations available to the physical layer chip in time periods comprises:
before each time slot starts, sending the corresponding delay time to the physical layer chip until all the delay time is sent; wherein at most one delay duration is sent within the same time period.
4. The method of claim 1, wherein receiving test data sent by the physical layer chip via the media access control layer in each time period and recording the number of error frames generated by communication between the media access control layer and the physical layer chip in the corresponding time period comprises:
receiving test data sent by the physical layer chip, and carrying out frame check sequence detection on each data frame of the test data; the test data is received when the test data transmitted by the physical layer chip reaches the transmission upper limit of an interface;
when the data frame can not pass the frame check sequence detection, determining the data frame as an error frame;
and recording the number of all error frames in the test data received in the corresponding time period.
5. The method of claim 4, wherein performing frame check sequence detection on each data frame of the test data comprises:
detecting a frame check sequence field in each data frame, and acquiring a first cyclic redundancy check result carried in the frame check sequence field;
performing cyclic redundancy check calculation on the data frame to obtain a second cyclic redundancy check calculation result, and comparing the second cyclic redundancy check calculation result with the first cyclic redundancy check result;
if the first cyclic redundancy check result is different from the second cyclic redundancy check calculation result, determining that the data frame does not pass frame check sequence detection;
and if the first cyclic redundancy check result is the same as the second cyclic redundancy check calculation result, determining that the data frame passes the frame check sequence detection.
6. The method of claim 1, wherein setting a delay duration corresponding to a time period in which the number of error frames generated in all time periods is the smallest as a delay duration finally used by the physical layer chip comprises:
when a plurality of different delay time lengths which can be used by the physical layer chip are all sent to the physical layer chip and all test data sent by the physical layer chip in time periods corresponding to all the delay time lengths are received, reading the number of error frames sent by the physical layer chip in the corresponding time periods under the plurality of different delay time lengths;
sorting the different delay durations according to the number of error frames, obtaining the delay duration used by the physical layer chip when the number of error frames is minimum, and sorting the delay durations
The delay time is set as the delay time of the physical layer chip used finally.
7. The method of claim 1, further comprising:
and when the number of the error frames generated in any time period is determined to be 0 frame, determining the corresponding delay time to be the optimal delay time, directly setting the optimal delay time to be the delay time finally used by the physical layer chip, and stopping sending the delay time to the physical layer chip.
8. A system for automatically configuring a delay parameter, comprising:
the parameter adjusting unit is used for sequentially sending a plurality of different delay durations which can be used by the physical layer chip to the physical layer chip in different time periods, so that the physical layer chip uses the corresponding delay durations to delay the time sequence signals in the physical layer chip in the corresponding time period;
the data receiving unit is used for receiving the test data sent by the physical layer chip in each time period and recording the number of error frames generated by communication between the medium access control layer and the physical layer chip in the corresponding time period;
and the parameter determining unit is used for setting the delay time corresponding to the time period with the minimum number of error frames in all time periods as the delay time finally used by the physical layer chip.
9. A system for automatically configuring a delay parameter, comprising:
a device under test for performing the method of any one of claims 1-7;
and the pressure test equipment is connected with the equipment to be tested through a network cable and is used for providing test data for the equipment to be tested and achieving the maximum bandwidth of the current network.
10. An apparatus for automatically configuring delay parameters, comprising:
a central processing unit having a media access control layer chip embodied thereon, the central processing unit further configured to perform the method of any of claims 1-7;
the medium access control layer chip is connected with the physical layer chip through a first interface and transmits data;
the physical layer chip is used for receiving network data.
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