CN113904631A - Low noise amplifier and low noise amplifier chip - Google Patents
Low noise amplifier and low noise amplifier chip Download PDFInfo
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- CN113904631A CN113904631A CN202111194980.XA CN202111194980A CN113904631A CN 113904631 A CN113904631 A CN 113904631A CN 202111194980 A CN202111194980 A CN 202111194980A CN 113904631 A CN113904631 A CN 113904631A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/52—Circuit arrangements for protecting such amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
Abstract
The application discloses a low noise amplifier and a low noise amplifier chip. Wherein the low noise amplifier comprises: a receiver; a first radio frequency switch, a first end of the first radio frequency switch being connected to the receiver; a first end of the multistage low noise amplification module is connected with a second end of the first radio frequency switch; a first attenuation path having a first end connected to the second end of the first RF switch; and the radio frequency switch is connected with the second end of the multistage low-noise amplification module and the second end of the first attenuation path. The low noise amplifier provided by the embodiment of the application is an amplitude limiting low noise amplifier SIP chip with a bypass. Effectively reduces layout area and system complexity, improves system receiving sensitivity, and is particularly suitable for being applied to a receiving front end of a backpack or handheld ultrashort wave communication radio station with strict requirements on size and weight.
Description
Technical Field
The application belongs to the technical field of communication, and particularly relates to a low-noise amplifier and a low-noise amplifier chip.
Background
The amplitude limiting low-noise amplifier is widely applied to the front end of an ultrashort wave radio station receiving system. And simultaneously has the functions of an amplitude limiter and a low noise amplifier. The low-noise amplifier can amplify weak signals with low noise, can inhibit strong interference signals, and plays a role in protecting a post-stage circuit. In a receiving chain, a weak signal obtains a certain gain after passing through a low noise amplifier, but a larger receiving signal may saturate the low noise amplifier to distort the receiving signal, thereby affecting the demodulation quality of the receiving signal.
On the premise of the existing miniaturization requirement, the traditional amplitude limiting low-noise amplifier generally adopts a hybrid integrated circuit or a single-chip microwave integrated circuit to cascade an amplitude limiter and a low-noise amplifier together, a peripheral circuit adopts a plurality of discrete devices to realize the functions of blocking, choking, matching and the like, and the design of a plane layout mode is adopted. The plane layout mode has large size and limited circuit layout, and is difficult to adapt to the miniaturization development requirement of communication radio stations.
Disclosure of Invention
An object of the present application is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
The application provides a low noise amplifier, low noise amplifier includes: a receiver; a first radio frequency switch, a first end of the first radio frequency switch being connected to the receiver; a first end of the multistage low noise amplification module is connected with a second end of the first radio frequency switch; a first attenuation path having a first end connected to the second end of the first RF switch; and the radio frequency switch is connected with the second end of the multistage low-noise amplification module and the second end of the first attenuation path.
Optionally, in an embodiment of the present application, the multistage low noise amplification module includes: a first low noise amplifier, a first end of the first low noise amplifier being connected to a second end of the first radio frequency switch; a second attenuation path having a first end connected to a second end of the first low noise amplifier; a second low noise amplifier having a first end connected to a second end of the second attenuation path.
Optionally, in this embodiment of the present application, the second attenuation path is a pi-type attenuation path.
Optionally, in this embodiment of the present application, the first attenuation path is a pi-type attenuation path.
The application provides a low noise amplifier chip, low noise amplifier chip includes: a radio frequency signal substrate; the low noise amplifier is arranged on the radio frequency signal substrate.
Optionally, IN this embodiment of the present application, the first pin RF _ IN of the radio frequency signal substrate is connected to the node RF 1; c1 is located between the radio frequency nodes RF1 and RF 2; z1 is located between RF2 and RF3, is switched in reverse, and is grounded; z2 is located between RF3 and RF4, is forward connected, is grounded, and is connected to node RF 1; c1 is located between the radio frequency nodes RF1 and RF 2; z1 is located between RF2 and RF3, is switched in reverse, and is grounded; z2 is located between RF3 and RF4, is forward connected, and is grounded, C2 is located between RF4 and RF 5; SPDT1 is located between RF5, RF6 and RF 19; c3 is located between RF6 and RF 7; LNA1 is located between RF7 and RF 8; c4 is located between RF9 and RF 10; ATT1 is located between RF10 and RF 11; c5 is located between RF11 and RF 12; LNA2 is located between RF12 and RF 13; c6 is located between RF14 and RF 15; z3 is located between RF15 and RF16, is switched in reverse, and is grounded; z4 is located between RF16 and RF17, is forward connected, and is grounded; c7 is located between RF17 and RF 18; c8 is located between RF19 and RF 20; ATT2 is located between RF20 and RF 21; c9 is located between RF21 and RF 22; SPDT2 is located between RF18, RF22 and RF23, forming a combination with SPDT 1; c13 is located between RF23 and RF 24; the RF24 node is connected to the package 36 pin to the radio frequency output RF _ OUT.
Optionally, in this embodiment of the application, the second pin of the radio frequency signal substrate is a power supply port VDD and is connected to the direct current node DC 1; the capacitor C12 is connected among the direct current nodes DC1, DC2 and DC6 and is grounded; the inductor L2 is positioned between a direct current node DC6 and a DC7, and a DC7 node is connected with radio frequency nodes RF13 and RF 14; c10 is located between DC node DC2 and DC node DC3, and is grounded; l3 is located between DC3 and DC 4; c11 is located between DC node DC4 and DC node DC5, and is grounded; l1 is located between DC node DC5 and radio frequency nodes RF8 and RF 9.
Optionally, in the embodiment of the present application, a radio frequency signal reaches the input port of the SPDT1 through the radio frequency nodes RF1, RF2, RF3, RF4, and RF5, and the signal reaches the RF6 node through level control of CTRL _ a; signals pass through RF6, RF7, RF8, RF9, RF10, RF11, RF12, RF13, RF14, RF15, RF16, RF17 and RF18 to SPDT2, and through the radio frequency node RF24 to RF _ OUT output by controlling the level of CTRL _ B, the signals pass through RF 23.
Optionally, in this embodiment of the application, by controlling the levels of CTRL _ a and CTRL _ B, a radio frequency signal reaches radio frequency node RF19 from radio frequency node RF5, reaches radio frequency node RF23 through radio frequency nodes RF20, RF21, and RF22, and is connected to RF _ OUT through radio frequency node 24 to output a radio frequency signal; the direct current signal VDD passes through direct current nodes DC1, DC6, and DC7 to RF13 to power LNA 2; the RF8 is reached through DC2, DC3, DC4, and DC5 to power LNA 1.
Compared with the prior art, the method has the following beneficial effects:
the low noise amplifier provided by the embodiment of the application is an amplitude limiting low noise amplifier SIP chip with a bypass, effectively reduces layout area and system complexity, improves system receiving sensitivity, and is particularly suitable for being applied to a receiving front end of a backpack or handheld ultrashort wave communication radio station with strict requirements on size and weight.
The embodiment realizes effective protection of a post-stage circuit under large signals, obtains smaller noise coefficient under small signals, has larger link gain, can achieve the effects of amplitude limiting protection and low-noise amplification, and has certain innovation value.
Additional advantages, objects, and features of the application will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the application.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a schematic structural diagram of a low noise amplifier provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of a low noise amplifier chip according to an embodiment of the present disclosure.
Detailed Description
The present application will now be described in further detail with reference to the accompanying drawings, whereby one skilled in the art can, with reference to the description, make an implementation.
It will be understood that terms such as "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
The technical solution of the present application will be described in detail below with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, the low noise amplifier provided in the embodiment of the present application includes: a receiver; a first radio frequency switch, a first end of the first radio frequency switch being connected to the receiver; a first end of the multistage low noise amplification module is connected with a second end of the first radio frequency switch; a first attenuation path having a first end connected to the second end of the first RF switch; and the radio frequency switch is connected with the second end of the multistage low-noise amplification module and the second end of the first attenuation path.
Optionally, in an embodiment of the present application, the multistage low noise amplification module includes: a first low noise amplifier, a first end of the first low noise amplifier being connected to a second end of the first radio frequency switch; a second attenuation path having a first end connected to a second end of the first low noise amplifier; a second low noise amplifier having a first end connected to a second end of the second attenuation path.
Optionally, in this embodiment of the present application, the second attenuation path is a pi-type attenuation path.
Optionally, in this embodiment of the present application, the first attenuation path is a pi-type attenuation path.
Referring to fig. 1, the rf signal received by the receiver enters the first stage rf switch after being limited by the limiter. The rf switch splits the rf signal into two paths: one is a low noise amplifier which is cascaded through two stages, and the other path is a pi-type attenuation path; and then output through a radio frequency switch. After strong interference signals enter the receiver, the signal intensity is greatly reduced after amplitude limiting of the amplitude limiter, and a receiving post-stage circuit is protected. When the received signal is very small, the signal enters a low-noise amplification link through the radio frequency switch selection signal, a good noise coefficient is obtained, meanwhile, a large link gain is obtained, and the signal enters the radio frequency switch through a first-stage amplitude limiter. When the received signal is large, the radio frequency switch selects to enter the attenuation chain.
The circuit is applied to an ultrashort wave band, and the low-noise amplification link can ensure that the whole receiving link has a good noise coefficient by using a two-stage low-noise amplifier cascade mode, so that the sensitivity of the receiving link is effectively improved, and meanwhile, the damage of a strong interference signal to a rear-stage link is effectively restrained. In addition, the radio frequency switch chip is selected to replace the traditional mechanical switch, so that the volume is saved, and the switching time is effectively shortened to nanosecond level.
The invention combines the prior SIP technology to integrate the circuit into a QFN64 packaged chip with 7.5mm multiplied by 7.5mm, thereby not only saving the layout area, but also providing a solution for miniaturization. In the ultra-short wave band, the noise coefficient of the whole link can be as low as 2.6dB, and simultaneously, the gain of more than 30dB can be obtained. By adopting the SIP technology, the layout area can be greatly reduced, chips of various different processes can be integrated, and the finished product has good consistency.
In the embodiment of the application, the discrete device is designed in the chip, so that the area is reduced, any peripheral device is not needed, and the use difficulty is reduced; and an amplitude limiter is added behind the amplifier to protect a post-stage circuit.
The low noise amplifier provided by the embodiment of the application is an amplitude limiting low noise amplifier SIP chip with a bypass, effectively reduces layout area and system complexity, improves system receiving sensitivity, and is particularly suitable for being applied to a receiving front end of a backpack or handheld ultrashort wave communication radio station with strict requirements on size and weight.
The embodiment realizes effective protection of a post-stage circuit under large signals, obtains smaller noise coefficient under small signals, has larger link gain, can achieve the effects of amplitude limiting protection and low-noise amplification, and has certain innovation value.
As shown in fig. 2, the present application provides a low noise amplifier chip, which includes: a radio frequency signal substrate; the low noise amplifier is arranged on the radio frequency signal substrate.
Optionally, IN this embodiment of the present application, the first pin RF _ IN of the radio frequency signal substrate is connected to the node RF 1; c1 is located between the radio frequency nodes RF1 and RF 2; z1 is located between RF2 and RF3, is switched in reverse, and is grounded; z2 is located between RF3 and RF4, is forward connected, is grounded, and is connected to node RF 1; c1 is located between the radio frequency nodes RF1 and RF 2; z1 is located between RF2 and RF3, is switched in reverse, and is grounded; z2 is located between RF3 and RF4, is forward connected, and is grounded, C2 is located between RF4 and RF 5; SPDT1 is located between RF5, RF6 and RF 19; c3 is located between RF6 and RF 7; LNA1 is located between RF7 and RF 8; c4 is located between RF9 and RF 10; ATT1 is located between RF10 and RF 11; c5 is located between RF11 and RF 12; LNA2 is located between RF12 and RF 13; c6 is located between RF14 and RF 15; z3 is located between RF15 and RF16, is switched in reverse, and is grounded; z4 is located between RF16 and RF17, is forward connected, and is grounded; c7 is located between RF17 and RF 18; c8 is located between RF19 and RF 20; ATT2 is located between RF20 and RF 21; c9 is located between RF21 and RF 22; SPDT2 is located between RF18, RF22 and RF23, forming a combination with SPDT 1; c13 is located between RF23 and RF 24; the RF24 node is connected to the package 36 pin to the radio frequency output RF _ OUT.
Optionally, in this embodiment of the application, the second pin of the radio frequency signal substrate is a power supply port VDD and is connected to the direct current node DC 1; the capacitor C12 is connected among the direct current nodes DC1, DC2 and DC6 and is grounded; the inductor L2 is positioned between a direct current node DC6 and a DC7, and a DC7 node is connected with radio frequency nodes RF13 and RF 14; c10 is located between DC node DC2 and DC node DC3, and is grounded; l3 is located between DC3 and DC 4; c11 is located between DC node DC4 and DC node DC5, and is grounded; l1 is located between DC node DC5 and radio frequency nodes RF8 and RF 9.
Optionally, in the embodiment of the present application, a radio frequency signal reaches the input port of the SPDT1 through the radio frequency nodes RF1, RF2, RF3, RF4, and RF5, and the signal reaches the RF6 node through level control of CTRL _ a; signals pass through RF6, RF7, RF8, RF9, RF10, RF11, RF12, RF13, RF14, RF15, RF16, RF17 and RF18 to SPDT2, and through the radio frequency node RF24 to RF _ OUT output by controlling the level of CTRL _ B, the signals pass through RF 23.
Optionally, in this embodiment of the application, by controlling the levels of CTRL _ a and CTRL _ B, a radio frequency signal reaches radio frequency node RF19 from radio frequency node RF5, reaches radio frequency node RF23 through radio frequency nodes RF20, RF21, and RF22, and is connected to RF _ OUT through radio frequency node 24 to output a radio frequency signal; the direct current signal VDD passes through direct current nodes DC1, DC6, and DC7 to RF13 to power LNA 2; the RF8 is reached through DC2, DC3, DC4, and DC5 to power LNA 1.
With reference to fig. 2, the design of the present invention includes: the blocking capacitors C1, C2, C3, C4, C5, C6, C7, C8, C9 and C13; grounded capacitances C10, C11, and C12; choke inductances L1, L2, and L3; attenuators ATT1 and ATT 2; limiters Z1 and Z2, Z3 and Z4; low noise amplifiers LNA1 and LNA 2; single pole double throw switches SPDT1 and SPDT 2; nodes on the radio frequency signal substrate RF1, RF2, RF3, RF4, RF5, RF6, RF7, RF8, RF9, RF10, RF11, RF12, RF13, RF14, RF15, RF16, RF17, RF18, RF19, RF20, RF21, RF22, RF23, and RF 24; direct current signals are at nodes DC1, DC2, DC3, DC4, DC5 and DC6 on the substrate.
Wherein pin 63 of the package is RF _ IN, connected to node RF 1; c1 is located between the radio frequency nodes RF1 and RF 2; z1 is located between RF2 and RF3, is switched in reverse, and is grounded; z2 is located between RF3 and RF4, is switched in forward direction, and is connected with Z1 in pair to play a role in amplitude limiting; c2 is located between RF4 and RF 5; the SPDT1 is positioned among the RF5, the RF6 and the RF19, and realizes a channel switching function; c3 is located between RF6 and RF 7; LNA1 is located between RF7 and RF 8; c4 is located between RF9 and RF 10; ATT1 is located between RF10 and RF 11; c5 is located between RF11 and RF 12; LNA2 is located between RF12 and RF 13; c6 is located between RF14 and RF 15; z3 is located between RF15 and RF16, is switched in reverse, and is grounded; z4 is located between RF16 and RF17, is switched in forward direction, and is connected with Z3 in pair to play a role in amplitude limiting; c7 is located between RF17 and RF 18; c8 is located between RF19 and RF 20; ATT2 is located between RF20 and RF 21; c9 is located between RF21 and RF 22; the SPDT2 is positioned among the RF18, the RF22 and the RF23, realizes a channel switching function and is combined with the SPDT 1; c13 is located between RF23 and RF 24; the RF24 node is connected to the package 36 pin to the radio frequency output RF _ OUT. The states of SPDT1 and SPDT2 are determined by the high and low of input level signals CTRL _ A and CTRL _ B at pins 8 and 9, respectively.
The 48 pins of the package are power supply ports VDD and connected with a direct current node DC 1; the capacitor C12 is connected among the direct current nodes DC1, DC2 and DC6 and is grounded; the inductor L2 is positioned between a direct current node DC6 and a DC7, and a DC7 node is connected with radio frequency nodes RF13 and RF 14; c10 is located between DC node DC2 and DC node DC3, and is grounded; l3 is located between DC3 and DC 4; c11 is located between DC node DC4 and DC node DC5, and is grounded; l1 is located between DC node DC5 and radio frequency nodes RF8 and RF 9.
Radio frequency signals reach the input port of the SPDT1 through radio frequency nodes RF1, RF2, RF3, RF4, RF5, and the signals reach the RF6 node through level control of CTRL _ a. Signals pass through RF6, RF7, RF8, RF9, RF10, RF11, RF12, RF13, RF14, RF15, RF16, RF17 and RF18 to SPDT2, and through the radio frequency node RF24 to RF _ OUT output by controlling the level of CTRL _ B, the signals pass through RF 23. By controlling the levels of CTRL _ A and CTRL _ B, a radio frequency signal reaches a radio frequency node RF19 from a radio frequency node RF5, passes through radio frequency nodes RF20, RF21 and RF22 to reach a radio frequency node RF23, and is connected with RF _ OUT through a radio frequency node 24 to output a radio frequency signal. The direct current signal VDD passes through direct current nodes DC1, DC6, and DC7 to RF13 to power LNA 2; the RF8 is reached through DC2, DC3, DC4, and DC5 to power LNA 1.
It can be understood that: 1. the amplitude limiter and the low-noise amplifier are cascaded, and peripheral devices are not needed, so that the traditional layout area is greatly reduced; 2. meanwhile, the amplitude limiter plays a good role in protecting a post-stage circuit in a receiving link; 3. the invention cascades two stages of low noise amplifiers, obtains larger receiving link gain and smaller link noise coefficient, thereby improving the sensitivity of the whole receiving link, and for a backpack communication radio station, the invention can receive weaker signals and improve the communication reliability; 4. in the invention, the radio frequency switch is added to effectively distinguish the large and small received signals, so that the larger signal enters the receiver and then directly enters the next stage through the direct link, thereby avoiding the influence of the large signal on the low noise amplifier and ensuring the demodulation quality of the large signal; 5. the radio frequency switch adopted by the invention effectively distinguishes the signal size, and solves the problem of low speed of the traditional mechanical switch. The switching speed of the radio frequency switch is in the order of tens of nanoseconds. 6. The choke inductance of the low noise amplifier is optimized. An inductor with a large inductance value is needed according to the traditional design, the packaging is large, the height is high, the height of the SIP chip is directly influenced, and the resonant frequency is low. The inductor is divided and optimized to be replaced by an inductor with a smaller inductance value, so that the height of the inductor is reduced, and the self-resonance frequency of the inductor is effectively improved; 7. when the substrate is arranged, the radio frequency path is arranged along the edge of the PCB as much as possible, the signal barrier is added in the middle, and the self-excitation of the link is effectively prevented.
Although the embodiments of the present application have been disclosed above, they are not limited to the applications listed in the description and the embodiments. It can be applied in all kinds of fields suitable for the present application. Additional modifications will readily occur to those skilled in the art. Therefore, the application is not limited to the specific details and illustrations shown and described herein, without departing from the general concept defined by the claims and their equivalents.
Claims (9)
1. A low noise amplifier, comprising:
a receiver;
a first radio frequency switch, a first end of the first radio frequency switch being connected to the receiver;
a first end of the multistage low noise amplification module is connected with a second end of the first radio frequency switch;
a first attenuation path having a first end connected to the second end of the first RF switch;
and the radio frequency switch is connected with the second end of the multistage low-noise amplification module and the second end of the first attenuation path.
2. The low noise amplifier of claim 1, wherein the multi-stage low noise amplification module comprises:
a first low noise amplifier, a first end of the first low noise amplifier being connected to a second end of the first radio frequency switch;
a second attenuation path having a first end connected to a second end of the first low noise amplifier;
a second low noise amplifier having a first end connected to a second end of the second attenuation path.
3. The low noise amplifier of claim 2, wherein the second attenuation path is a pi-type attenuation path.
4. The low noise amplifier of claim 1, wherein the first attenuation path is a pi-type attenuation path.
5. A low noise amplifier chip, comprising:
a radio frequency signal substrate;
the low noise amplifier of any one of claims 1 to 4 disposed on the radio frequency signal substrate.
6. The low noise amplifier chip of claim 5, wherein the first pin RF _ IN of the RF signal substrate is connected to a node RF 1; c1 is located between the radio frequency nodes RF1 and RF 2; z1 is located between RF2 and RF3, is switched in reverse, and is grounded; z2 is located between RF3 and RF4, is forward connected, is grounded, and is connected to node RF 1;
c1 is located between the radio frequency nodes RF1 and RF 2; z1 is located between RF2 and RF3, is switched in reverse, and is grounded; z2 is located between RF3 and RF4, is forward connected, and is grounded,
c2 is located between RF4 and RF 5; SPDT1 is located between RF5, RF6 and RF 19; c3 is located between RF6 and RF 7; LNA1 is located between RF7 and RF 8; c4 is located between RF9 and RF 10; ATT1 is located between RF10 and RF 11; c5 is located between RF11 and RF 12; LNA2 is located between RF12 and RF 13; c6 is located between RF14 and RF 15; z3 is located between RF15 and RF16, is switched in reverse, and is grounded; z4 is located between RF16 and RF17, is forward connected, and is grounded; c7 is located between RF17 and RF 18; c8 is located between RF19 and RF 20; ATT2 is located between RF20 and RF 21; c9 is located between RF21 and RF 22; SPDT2 is located between RF18, RF22 and RF23, forming a combination with SPDT 1; c13 is located between RF23 and RF 24; the RF24 node is connected to the package 36 pin to the radio frequency output RF _ OUT.
7. The LNA chip of claim 5, where the second pin of the RF signal substrate is connected to the DC node DC1 for the supply port VDD; the capacitor C12 is connected among the direct current nodes DC1, DC2 and DC6 and is grounded; the inductor L2 is positioned between a direct current node DC6 and a DC7, and a DC7 node is connected with radio frequency nodes RF13 and RF 14; c10 is located between DC node DC2 and DC node DC3, and is grounded; l3 is located between DC3 and DC 4; c11 is located between DC node DC4 and DC node DC5, and is grounded; l1 is located between DC node DC5 and radio frequency nodes RF8 and RF 9.
8. The LNA chip of claim 5, where the RF signals reach the input port of the SPDT1 through RF nodes RF1, RF2, RF3, RF4, RF5, controlled by the level of CTRL _ A, the signals reaching the RF6 node; signals pass through RF6, RF7, RF8, RF9, RF10, RF11, RF12, RF13, RF14, RF15, RF16, RF17 and RF18 to SPDT2, and through the radio frequency node RF24 to RF _ OUT output by controlling the level of CTRL _ B, the signals pass through RF 23.
9. The lna chip of claim 8, wherein the levels of CTRL _ a and CTRL _ B are controlled such that the RF signal reaches RF node RF19 from RF node RF5, passes through RF nodes RF20, RF21, and RF22 to reach RF node RF23, passes through RF node 24, and is connected to RF _ OUT to output the RF signal; the direct current signal VDD passes through direct current nodes DC1, DC6, and DC7 to RF13 to power LNA 2;
the RF8 is reached through DC2, DC3, DC4, and DC5 to power LNA 1.
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| CN202111194980.XA CN113904631A (en) | 2021-10-13 | 2021-10-13 | Low noise amplifier and low noise amplifier chip |
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Application publication date: 20220107 |