CN113900368A

CN113900368A - Time-to-digital converter applied to array laser radar

Info

Publication number: CN113900368A
Application number: CN202111189192.1A
Authority: CN
Inventors: 朱樟明; 胡进; 楚泽坤; 马瑞
Original assignee: Xidian University; Wuhu Research Institute of Xidian University
Current assignee: Xidian University; Wuhu Research Institute of Xidian University
Priority date: 2021-06-29
Filing date: 2021-10-12
Publication date: 2022-01-07
Anticipated expiration: 2041-10-12
Also published as: CN113900368B

Abstract

The invention discloses a time-to-digital converter applied to an array type laser radar, which comprises: the circuit comprises a START/STOP logic circuit, an interpolation voltage-controlled ring oscillator, a counter, an encoder, a START signal end and a STOP signal end; the first input end and the second input end of the START/STOP logic circuit are respectively connected with a START signal end and a STOP signal end, the first output end of the START/STOP logic circuit is connected with the first input end of the interpolation type voltage-controlled ring oscillator, the second output end of the START/STOP logic circuit is connected with the second input end of the interpolation type voltage-controlled ring oscillator, the output end of the interpolation type voltage-controlled ring oscillator is connected with the encoder, the counter comprises a plurality of cascaded true single-phase D triggers, and the input end of the counter is connected with the START signal end. The time-to-digital converter has high measurement precision and good phase noise characteristics, and can be used as a time interval measurement circuit of a large-scale single-photon avalanche diode pixel array in three-dimensional imaging application.

Description

Time-to-digital converter applied to array laser radar

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a time-to-digital converter applied to an array type laser radar.

Background

An array type laser radar applied to scenes such as autopilot and aircraft navigation needs a Time-to-Digital Converter (TDC) with higher high resolution. In these applications, there is one TDC inside each pixel, and thus the number of TDCs is quite large. In addition, the TDC requires an accuracy of < -100 ps, and a function of adjustable accuracy needs to be supported. In order for the TDC to work properly under different environments, the resolution of the TDC needs to be insensitive to the variation of pvt (process Voltage temperature).

The simplest method for implementing the TDC is to use a counter to count the number of pulses of a high-speed clock included in the time to be measured. But this solution is not practical for applications requiring particularly high precision. The particularly high accuracy requires a very high frequency clock, the resulting power consumption will be very high, and a great challenge is posed to the design of the counter. The TDC based on the vernier delay chain and the pulse shortening method can realize the TDC which is lower than the delay resolution of the delay unit, and can break through the process limit. Therefore, these two schemes are also not suitable for large-scale array lidar applications. The ring structure is one of the most suitable TDC structures for array applications. The resolution of a TDC based on a ringing structure depends mainly on the process node. To further improve the resolution, a phase interpolation method may be employed. Since the TDC operates in continuous mode, two samples are required to complete the quantization. To reduce power consumption, TDCs applied to lidar applications should only operate within time of flight. Therefore, a TDC structure that consumes a small silicon area and has low power consumption and can simultaneously realize high resolution is required.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides a time-to-digital converter for an array type lidar. The technical problem to be solved by the invention is realized by the following technical scheme:

the invention provides a time-to-digital converter applied to an array type laser radar, which comprises: the circuit comprises a START/STOP logic circuit, an interpolation voltage-controlled ring oscillator, a counter, an encoder, a START signal end and a STOP signal end; wherein,

the START/STOP logic circuit comprises a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the interpolation-type voltage-controlled ring oscillator comprises a first input terminal, a second input terminal, and an output terminal, and the counter comprises an input terminal; a first input terminal and a second input terminal of the START/STOP logic circuit are connected to the START signal terminal and the STOP signal terminal, respectively, a first output terminal of the START/STOP logic circuit is connected to a first input terminal of the interpolation type voltage-controlled ring oscillator, a second output terminal of the START/STOP logic circuit is connected to a second input terminal of the interpolation type voltage-controlled ring oscillator, an output terminal of the interpolation type voltage-controlled ring oscillator is connected to the encoder, the counter includes a plurality of true single-phase D flip-flops in cascade, and an input terminal is connected to the START signal terminal.

In one embodiment of the invention, the interpolation-type voltage-controlled ring oscillator includes a first loop and an interpolation module.

In one embodiment of the invention, the first loop comprises a four-stage difference unit.

In one embodiment of the invention, the power supply further comprises a power supply voltage signal terminal;

the first loop comprises a first type of inverter: I0-I7, inverter of the second type: B0-B7, and a NAND gate: N0-N7; wherein,

the output end of I0 is connected with the input end of I1, the output end of I1 is connected with the input end of I2, the output end of I2 is connected with the input end of I3, the output end of I3 is connected with the input end of I7, the output end of I7 is connected with the input end of I6, the output end of I6 is connected with the input end of I5, the output end of I5 is connected with the input end of I4, and the output end of I4 is connected with the input end of I0;

the input end of B0 is connected with the output end of I0, the input end of B1 is connected with the output end of I1, the input end of B2 is connected with the output end of I2, the input end of B3 is connected with the output end of I3, the input end of B4 is connected with the output end of I4, the input end of B5 is connected with the output end of I5, the input end of B6 is connected with the output end of I6, and the input end of B7 is connected with the output end of I7;

an output terminal of N0 is connected to an output terminal of I7, a first input terminal of N0 is connected to a second output terminal of the START/STOP logic circuit, and a second input terminal of N0 is connected to an output terminal of I0; an output end of the N1 is connected with an output end of the I0, a first input end of the N1 is connected with an output end of the I7, and a second input end of the N1 is connected with the power supply voltage signal end; an output end of the N2 is connected with an output end of the I6, a first input end of the N2 is connected with an output end of the I1, and a second input end of the N2 is connected with the power supply voltage signal end; an output terminal of N3 is connected to an output terminal of I1, a first input terminal of N3 is connected to an output terminal of I6, and a second input terminal of N3 is connected to a second output terminal of the START/STOP logic circuit; an output terminal of N4 is connected to an output terminal of I5, a first input terminal of N4 is connected to an output terminal of I2, and a second input terminal of N4 is connected to a second output terminal of the START/STOP logic circuit; an output end of the N5 is connected with an output end of the I2, a first input end of the N5 is connected with an output end of the I5, and a second input end of the N5 is connected with the power supply voltage signal end; the output end of the N6 is connected with the output end of the I4, the first input end of the N6 is connected with the power supply voltage signal end, and the second input end of the N6 is connected with the output end of the I3; an output terminal of N7 is connected to an output terminal of I3, a first input terminal of N7 is connected to an output terminal of I4, and a second input terminal of N7 is connected to a second output terminal of the START/STOP logic circuit.

In one embodiment of the invention, the interpolation module comprises a first interpolation unit, a second interpolation unit, a third interpolation unit and a fourth interpolation unit;

the first interpolation unit, the second interpolation unit, the third interpolation unit and the fourth interpolation unit all comprise two interpolation subunits and two NAND gates.

In one embodiment of the present invention, the first interpolation unit includes a first interpolation subunit, a second interpolation subunit, and a nand gate: n8 and N9, the first interpolation subunit including a first type of inverter: i8 and I9, inverter of the second type: b8, and a first capacitor, the second interpolation subunit comprises a first inverter type I10 and I11, a second inverter type: b9, and a second capacitance;

wherein, the input end of I8 is connected with the output end of I4, and the output end of I8 is connected with the first node; the input end of I9 is connected with the output end of B1, and the output end of I9 is connected with the first node; the input end of I10 is connected with the output end of I0, the output end of I10 is connected with the second node, the input end of I11 is connected with the output end of B0, and the output end of I11 is connected with the second node; an output terminal of N8 is connected to the second node, a first input terminal of N8 is connected to the supply voltage signal terminal, and a second input terminal of N8 is connected to the first node; an output terminal of N9 is connected to the first node, a first input terminal of N9 is connected to the second node, and a second input terminal of N9 is connected to the supply voltage signal terminal; an input terminal of B8 is connected with the first node; an input of B9 is connected to the second node.

In one embodiment of the invention, the START/STOP logic circuit comprises a first type of inverter: i12 and I13, nand gate: n10 and N11, and gate: a1, a third node, and a fourth node;

wherein, the input end of I12 is connected with the STOP signal end, the output end of I12 is connected with the first input end of N10, the second input end of N10 is connected with the third node, the output end of N10 is connected with the first input end of N11, the second input end of N11 is connected with the output end of I13, the input end of I13 is connected with the START signal end, the output end of N11 is connected with the third node, the first input end of A1 is connected with the third node, the second input end of A1 is connected with the fourth node, and the output end of A1 is connected with the first input end of the interpolation type voltage-controlled ring oscillator.

In one embodiment of the present invention, the interpolation-type voltage-controlled ring oscillator further comprises a first transistor for supplying power to the first inverter and the nand gate in the interpolation-type voltage-controlled ring oscillator.

Compared with the prior art, the invention has the beneficial effects that:

the invention provides a time-to-digital converter applied to an array type laser radar, which comprises: the device comprises a START/STOP logic circuit, an interpolation voltage-controlled ring oscillator, a counter and an encoder, wherein the interpolation voltage-controlled ring oscillator has higher measurement precision, and the interpolation voltage-controlled ring oscillator is reset before the START of each test period, so that the measurement error caused by uncertain initial state can be eliminated; in addition, in the time-to-digital converter provided by the invention, the counter is formed by cascading a plurality of true single-phase D triggers, and compared with the traditional latching type D trigger, the true single-phase D trigger is only driven by a single-phase clock, so that the area and the power consumption are smaller, and meanwhile, the time-to-digital converter also has better phase noise characteristics, and can be used as a time interval measuring circuit of a large-scale single-photon avalanche diode pixel array in three-dimensional imaging application.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

Fig. 1 is a schematic structural diagram of a time-to-digital converter applied to an array type lidar according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a first loop in an interpolation-type voltage-controlled ring oscillator according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of an interpolation module in an interpolation-type voltage-controlled ring oscillator according to an embodiment of the present invention;

FIG. 4 is a schematic structural diagram of a first interpolation unit in an interpolation module according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of a START/STOP logic circuit in an interpolation-type voltage-controlled ring oscillator according to an embodiment of the present invention;

FIG. 6 is a timing diagram illustrating the operation of the START/STOP logic circuit provided by an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a counter according to an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of an encoder according to an embodiment of the present invention;

fig. 9 is a schematic structural diagram of another time-to-digital converter applied to an array type lidar according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

As shown in fig. 1, a time-to-digital converter 100 applied to an array type lidar according to an embodiment of the present invention includes: START/STOP logic circuit 10, interpolation type voltage-controlled ring oscillator 20, counter 30, encoder 40, START signal terminal and STOP signal terminal; wherein,

START/STOP logic circuit 10 comprises a first input, a second input, a first output and a second output, interpolation type voltage controlled ring oscillator 20 comprises a first input, a second input and an output, counter 30 comprises an input; a first input terminal and a second input terminal of the START/STOP logic circuit 10 are connected to a START signal terminal and a STOP signal terminal, respectively, a first output terminal of the START/STOP logic circuit 10 is connected to a first input terminal of the interpolation-type voltage-controlled ring oscillator 20, a second output terminal of the START/STOP logic circuit 10 is connected to a second input terminal of the interpolation-type voltage-controlled ring oscillator 20, an output terminal of the interpolation-type voltage-controlled ring oscillator 20 is connected to the encoder 40, the counter 30 includes a plurality of true single-phase D flip-flops which are cascaded, and an input terminal thereof is connected to the START signal terminal.

In the present embodiment, the time-to-digital converter 100 is composed of a START/STOP logic circuit 10, an interpolation type voltage-controlled ring oscillator 20, a counter 30, an encoder 40, a START signal terminal, and a STOP signal terminal. Specifically, the START/STOP logic circuit 10 is used for generating a gate signal, and the input terminals thereof are respectively connected to the START signal terminal and the STOP signal terminal, and the SATRT signal can set the gate signal to a valid value when coming, and make the interpolation type voltage controlled ring oscillator 20 START to operate, and when the STOP signal comes, the interpolation type voltage controlled ring oscillator 20 STOPs operating. The interpolation-type voltage-controlled ring oscillator 20 may be composed of an inverter and a nand gate, and is a multi-stage differential unit based on an inverter unit, and has a reset function and a gate control function.

Furthermore, the counter 30 circuit is formed by cascading single-phase D flip-flops having a reset function, and resets before each time interval measurement is performed, and outputs high-order count state information. Alternatively, the encoder 40 is composed of logic gates, and outputs the lower three-bit count state by detecting the output signal of each stage of the differential unit in the interpolation-type voltage-controlled ring oscillator 20, using its composed eight-bit binary state code as the input code.

In the time-to-digital converter 100, the interpolation-type voltage-controlled ring oscillator 20 includes a first loop 201 and an interpolation module 202. Optionally, the first loop 201 includes four stages of differential units, and with reference to fig. 2, the first stage of differential unit includes I0, B0, I7, and B7, the second stage of differential unit includes I1, B1, I6, and B6, the third stage of differential unit includes I2, B2, I5, and B5, and the fourth stage of differential unit includes I3, B3, I4, and B4.

As shown in fig. 2, the first loop 201 includes a first type of inverter: I0-I7, inverter of the second type: B0-B7, and a NAND gate: N0-N7; wherein,

an output terminal of N0 is connected to an output terminal of I7, a first input terminal of N0 is connected to a second output terminal of START/STOP logic circuit 10, and a second input terminal of N0 is connected to an output terminal of I0; the output end of N1 is connected with the output end of I0, the first input end of N1 is connected with the output end of I7, and the second input end of N1 is connected with a power supply voltage signal end; the output end of N2 is connected with the output end of I6, the first input end of N2 is connected with the output end of I1, and the second input end of N2 is connected with a power supply voltage signal end; an output terminal of N3 is connected to an output terminal of I1, a first input terminal of N3 is connected to an output terminal of I6, and a second input terminal of N3 is connected to a second output terminal of START/STOP logic circuit 10; an output terminal of N4 is connected to an output terminal of I5, a first input terminal of N4 is connected to an output terminal of I2, and a second input terminal of N4 is connected to a second output terminal of START/STOP logic circuit 10; the output end of N5 is connected with the output end of I2, the first input end of N5 is connected with the output end of I5, and the second input end of N5 is connected with a power supply voltage signal end; the output end of N6 is connected with the output end of I4, the first input end of N6 is connected with a power supply voltage signal end, and the second input end of N6 is connected with the output end of I3; an output terminal of N7 is connected to an output terminal of I3, a first input terminal of N7 is connected to an output terminal of I4, and a second input terminal of N7 is connected to a second output terminal of START/STOP logic circuit 10.

Specifically, the first loop 201 is composed of eight inverters of the first type: I0-I7, eight inverters of the second type driven as outputs: B0-B7, and four pairs of nand gates: N0-N7. When the control signal EN output by the first output terminal of the START/STOP logic circuit 10 is at a high level, the interpolation type voltage-controlled ring oscillator 20 STARTs to operate and enters an oscillation state; on the contrary, when the control signal EN output by the first output terminal of the START/STOP logic circuit 10 is at a low level, there is no signal path between the inverters of each stage, that is, there is no signal path between the differential structures of four stages, the output voltage is kept unchanged due to the parasitic capacitance of the field effect transistor in the inverters of the first and second stages, and the interpolation type voltage-controlled ring oscillator 20 STOPs operating.

Further, with continued reference to FIG. 2, each output terminal inside the interpolating type VCO 20 is connected to a second type of inverter B0-B7 having a strong driving capability, which outputs the phase state of each node to the outside as an output driver. As shown in fig. 2, each stage of differential unit includes a pair of and gates, and the and gates N0-N7 in this embodiment mainly implement three functions: (1) fully differentiating the output of each stage of the differential unit; (2) when the reset signal RST output from the second output terminal of the START/STOP logic circuit 10 is low, the internal node is reset to a desired initial state; (3) the output voltage of the differential cell undergoing a transition is restored to a digital level when the oscillation is stopped.

In the first loop 201, the input signals of the nand gate N0 are the output signal a1 and the reset signal RST of I0, the output terminal of N0 is connected to the output terminal of I7, the input signals of the nand gate N1 are the output signal B1 and the power supply voltage signal of I7, the output terminal of N1 is connected to the output terminal of I0, the input signals of the nand gate N0 are the output signal a0 and VDD of I0, respectively, the output terminal is connected to the output terminal of I0, the input signals of the nand gate N0 are the output signal B0 and the reset signal RST of I0, respectively, the output terminal is connected to the output terminal of I0, the input signals of the nand gate N0 are the output signal B0 and VDD of I0, respectively, the output terminal is connected to the output terminal of I0, the input signals of the nand gate N0 are the output signal B0 and the output terminal of I0, respectively, and the output terminal of VDD of the nand gate N0 is connected to the output terminal of I0, the input terminal of the nand gate N0, respectively, the input signal RST signal B0, and the output terminal of the input terminal of the nand gate N0 is connected to the output terminal of the input terminal of the nand gate N0, respectively, the input signals of the nand gate N7 are the output signal a0 and the reset signal RST of the I4, respectively, and the output terminal is connected to the output terminal of the I3. It can be understood that when the reset signal RST is at a high level, the output of the nand gate having the reset signal RST as an input is the inverse of the other input, so that the signals output by each stage of the differential unit are complementary; conversely, when the reset signal RST is at a low level, the output of the nand gate having the reset signal RST as an input is at a high level. As can be seen from fig. 2, when the reset signal is asserted, O7, O5N, O3 and O1N are reset to a high level, and O7N, O5, O3N and O1 are reset to a low level, that is, the set initial state of the interpolation voltage-controlled ring oscillator 20.

It should be noted that, in the first loop 201, the output signal of I3 is input to I7, and the output signal of I4 is input to I0, which can avoid the problem that the conventional even-order ring oscillator cannot oscillate under the dc condition.

Alternatively, as shown in fig. 3, in the interpolation type voltage controlled ring oscillator 20, the interpolation module 202 includes a first interpolation unit PIP1, a second interpolation unit PIP2, a third interpolation unit PIP3, and a fourth interpolation unit PIP 4; wherein the first interpolation unit PIP1, the second interpolation unit PIP2, the third interpolation unit PIP3 and the fourth interpolation unit PIP4 each include two interpolation sub-units and two nand gates.

It should be understood that since the structures of the first interpolation unit PIP1, the second interpolation unit PIP2, the third interpolation unit PIP3 and the fourth interpolation unit PIP4 are the same in this embodiment, only the first interpolation unit PIP1 is illustrated as an example.

Referring to fig. 4, the first interpolation unit PIP1 includes a first interpolation subunit PI1, a second interpolation subunit PI2, and a nand gate: n8 and N9, the first interpolation subunit PI1 includes inverters of the first type: i8 and I9, inverter of the second type: b8, and a first capacitor, the second interpolation subunit PI2 includes first type inverters I10 and I11, a second type inverter: b9, and a second capacitance;

wherein, the input end of I8 is connected with the output end of I4, and the output end of I8 is connected with the first node M1; the input end of I9 is connected with the output end of B1, and the output end of I9 is connected with a first node M1; an input end of I10 is connected with an output end of I0, an output end of I10 is connected with a second node M2, an input end of I11 is connected with an output end of B0, and an output end of I11 is connected with a second node M2; an output end of the N8 is connected with a second node M2, a first input end of the N8 is connected with a power supply voltage signal end, and a second input end of the N8 is connected with a first node M1; an output end of the N9 is connected with a first node M1, a first input end of the N9 is connected with a second node M2, and a second input end of the N9 is connected with a power supply voltage signal end; an input terminal of the B8 is connected to a first node M1; an input terminal of the B9 is connected to a second node M2.

Specifically, the in-phase delayed signals a0 and B1 pass through the first inverters I8 and I9 to obtain the interpolated phase a0_ B1, the in-phase delayed signals a1 and B0 pass through the first inverters I10 and I11 to obtain the interpolated phase a1_ B0, the input signals of the nand gate N8 are a0_ B1 and VDD, the output terminal of the nand gate N8 is connected to a1_ B0, the input signals of the nand gate N9 are a1_ B0 and RST, and the output terminal is connected to a0_ B1. The interpolation phases a0_ B1 and a1_ B0 are complementary, and output signals O2 and O2N are obtained through second inverters B8 and B9 with strong driving capability.

In order to match the load effect, the first interpolation subunit PI1 and the second interpolation subunit PI2 further include a first capacitor C1 and a second capacitor C2, and the first capacitor C1 and the second capacitor C2 are both MOS capacitors, so that the interpolation module 202 can be ensured to realize accurate interpolation by appropriately adjusting the sizes of the MOS capacitors.

Alternatively, as shown in FIG. 5, the START/STOP logic circuit 10 includes an inverter of the first type: i12 and I13, nand gate: n10 and N11, and gate: a1, a third node M3M3, and a fourth node M4M 4;

an input end of the I12 is connected with a STOP signal end, an output end of the I12 is connected with a first input end of the N10, a second input end of the N10 is connected with a third node M3, an output end of the N10 is connected with a first input end of the N11, a second input end of the N11 is connected with an output end of the I13, an input end of the I13 is connected with a START signal end, an output end of the N11 is connected with a third node M3, a first input end of the a1 is connected with a third node M3, a second input end of the a1 is connected with a fourth node M4, and an output end of the a1 is connected with a first input end of the interpolation type voltage-controlled ring oscillator 20.

Referring to FIGS. 5-6, the START/STOP logic circuit 10 includes a first type of inverter: i12 and I13, nand gate: n10 and N11, and gate: a1, a third node M3M3, and a fourth node M4M4, when the START signal arrives, the control signal EN goes high, the interpolation voltage controlled ring oscillator 20 STARTs oscillating, when the STOP signal arrives, EN goes low, the interpolation voltage controlled ring oscillator 20 STOPs operating, and the reset signal RST is complementary to the START signal. In this embodiment, the RST signal ensures that the internal node of the interpolated vclo 20 is reliably reset to the desired level, and therefore a monostable circuit is not required to generate the short reset signal. In addition, the and gate a1 is effective to ensure that RST and EN are not simultaneously asserted, which would otherwise result in incomplete reset, and thus an initial phase that is not desired to be reset, resulting in a phase error.

As shown in fig. 7, in this embodiment, the counter 30 may be formed by cascading 10 single-phase D flip-flops with asynchronous reset function, the output QN of each stage of D flip-flop is connected to the input D of the stage of D flip-flop and the clock CLK of the next stage of D flip-flop, the first stage of D flip-flop takes the output signal O7 of the interpolation type voltage controlled ring oscillator 20 as the counting clock, so that the resolution is the ring period, and records the number of ring periods between the START and STOP signals, and outputs the high-order data D <3:12> of the TDC.

Further, referring to fig. 8, in the time-to-digital converter 100, the encoder 40 is composed of an inverter: I14-I15 and an XOR gate: E1-E4. In this embodiment, the encoder 40 detects the low four-bit node state to obtain the three-bit decoding S <0:2>, and the following logical relationship is obtained by simplification:

S＜2＞＝OUT＜3＞

the input of the inverter I14 is the signal O7N, the output end is connected to the input end of I15, the output end of I15 is D <2>, and I14 and I15 are used as buffers. The input signals of the exclusive-OR gate E1 are O7N and O3N respectively, the output is D <1>, the input signals of E2 are O7N and O5, the input signals of E3 are O3N and O1, the output signals of E2 and E3 are the input signals of E4, and the output signal of E6 is D <0 >.

Optionally, as shown in fig. 9, the time-to-digital converter 100 further includes a first transistor T1 for supplying power to the first type of inverter and the nand gate in the interpolation-type voltage-controlled ring oscillator 20.

Specifically, to compensate for the effect of PVT variations on the ring frequency, the supply voltage of the interpolated vco 20 is adjusted by a local large-sized thick-gate NMOS transistor, i.e., the first transistor T1. The control voltage may be provided by a phase locked loop, and the output of the NMOS only powers the first inverter and nand gate in the interpolation-type voltage-controlled ring oscillator 20, and the second inverter may be powered by 1.8V.

The beneficial effects of the invention are that:

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.

In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.

While the present application has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims

1. A time-to-digital converter for array type laser radar, comprising: the circuit comprises a START/STOP logic circuit, an interpolation voltage-controlled ring oscillator, a counter, an encoder, a START signal end and a STOP signal end; wherein,

2. The time-to-digital converter applied to the array type laser radar is characterized in that the interpolation type voltage-controlled ring oscillator comprises a first loop and an interpolation module.

3. The time-to-digital converter for array lidar according to claim 2, wherein the first loop comprises four stages of differential units.

4. The time-to-digital converter applied to the array type laser radar is characterized by further comprising a power supply voltage signal end;

5. The time-to-digital converter applied to the array type lidar of claim 2, wherein the interpolation module comprises a first interpolation unit, a second interpolation unit, a third interpolation unit and a fourth interpolation unit;

6. The time-to-digital converter for array lidar according to claim 5, wherein the first interpolation unit comprises a first interpolation subunit, a second interpolation subunit, and a nand gate: n8 and N9, the first interpolation subunit including a first type of inverter: i8 and I9, inverter of the second type: b8, and a first capacitor, the second interpolation subunit comprises a first inverter type I10 and I11, a second inverter type: b9, and a second capacitance;

7. The time-to-digital converter for array lidar according to claim 1, wherein the START/STOP logic circuit comprises a first inverter: i12 and I13, nand gate: n10 and N11, and gate: a1, a third node, and a fourth node;

8. The time-to-digital converter applied to the array type lidar of claim 1, further comprising a first transistor for supplying power to the first inverter and the nand gate in the interpolation type voltage-controlled ring oscillator.