CN117081570A - On-chip resistor calibration circuit - Google Patents

Abstract

The invention discloses an on-chip resistor calibration circuit. The circuit comprises a reading circuit module, a counter circuit module, a calibration control circuit module and an external reference resistor. The current mirror in the readout circuit generates two voltages at two ends of the external reference resistor and the on-chip adjustable resistor circuit respectively, the readout circuit module generates high-low level signals by comparing the two voltages, the counter circuit module adjusts the count value according to the high-low level signals output by the comparator and then outputs variable digital control signals to control the on-chip adjustable resistor circuit in the readout circuit, when the voltages at two ends of the on-chip adjustable resistor in the readout circuit are equal to the voltages at two ends of the external reference resistor, the on-chip adjustable resistor is adjusted to a desired value, the high-low level signals output by the comparator in the readout circuit are changed, and at the moment, the digital control signals output by the latch in the counter circuit adjust the on-chip adjustable resistor to enable the on-chip adjustable resistor to reach the desired value, and therefore on-chip resistor calibration is completed.

Description

On-chip resistor calibration circuit

Technical Field

The invention relates to an on-chip resistor calibration circuit, in particular to a differential clock input port and differential signal input port resistor calibration circuit for an ultra-high speed analog-to-digital converter, belonging to the field of integrated circuit resistor calibration systems.

Background

Integrated circuits are typically fabricated on monocrystalline silicon substrates by forming various electronic components and metal lines through a series of semiconductor processes such as deposition, doping, etching, etc., to achieve the desired circuit functions. Although modern semiconductor technology can realize passive devices such as resistors, capacitors and the like through materials such as diffusion areas, polysilicon and the like, in the design and production of integrated circuits, technological deviation can lead to inconsistent actual resistance values and design values of chips after chip assembly, the deviation can even reach 20%, and the accuracy of the actual resistance values of the resistors in the chips can influence the performance of corresponding circuits and even cause functional errors. For example, a non-uniform resistive impedance on the transmission line and an output resistance within the chip will create signal reflection phenomena, resulting in serious signal integrity problems. The inaccuracy of the resistance of the filter in the phase-locked loop circuit also affects the design index, the overlarge resistance can generate larger thermal noise, and the overlarge resistance can lead the filter to be incapable of completely filtering the noise of the charge pump, so that the index of the output signal is poor. Therefore, calibrating the resistance of the on-chip resistor is a problem that often needs to be considered in engineering design.

Disclosure of Invention

The technical solution of the invention is that: the on-chip resistor calibration circuit overcomes the defects of the prior art, realizes high-precision calibration of on-chip resistors by adopting a digital-analog hybrid design method, ensures that the matching of a chip and an external input signal source meets the requirements, and is beneficial to ensuring the integrity and the reliability of signal reception.

The technical scheme of the invention is as follows: an on-chip resistor calibration circuit comprises a read-out circuit module, a counter circuit module and an external reference resistor R1;

the reading circuit module is used for generating voltages at two ends of the external reference resistor R1 and the on-chip adjustable resistor circuit respectively by using a current mirror, comparing the voltages at two ends of the external reference resistor R1 with the voltages at two ends of the on-chip adjustable resistor circuit, and generating a counting control signal CTRL according to a comparison result and outputting the counting control signal CTRL to the counter circuit module; when the voltage at two ends of the external reference resistor R1 is smaller than the voltage at two ends of the on-chip adjustable resistor circuit, the counting control signal CTRL is a high-level signal, otherwise, the counting control signal CTRL is a low-level signal;

the counter circuit module is internally provided with a digital counter, when the count control signal CTRL is a high-level signal, the count value of the digital counter is increased, otherwise, the count value of the digital counter is decreased, the count value of the digital counter is used as a first digital control word CTRL1 to latch and control an on-chip adjustable resistor circuit of the readout circuit module, the resistance value of the on-chip adjustable resistor circuit is adjusted until the state of the count control signal CTRL representing the voltage of two ends of an external reference resistor R1 and the voltage of two ends of the on-chip adjustable resistor circuit in the readout circuit module changes, and the on-chip adjustable resistor R3 to be calibrated is adjusted according to the latched first digital control word CTRL1 at the moment, so that the on-chip adjustable resistor R3 to be calibrated reaches the expected resistance value, and the on-chip resistor calibration is completed;

the on-chip adjustable resistor R3 to be calibrated and the on-chip adjustable resistor circuit are formed by serially connecting or parallelly connecting adjustable resistor units, the structural form of the on-chip adjustable resistor circuit is the same as that of the on-chip adjustable resistor R3 to be calibrated, and the initial value resistance of the on-chip adjustable resistor circuit is larger than the expected resistance of the on-chip adjustable resistor R3 to be calibrated.

Preferably, the on-chip resistor calibration circuit further comprises a calibration control circuit module and a clock control circuit module;

the calibration control circuit module is used for generating control signals of the whole calibration period and controlling the enabling and resetting of the read-out circuit module and the counter circuit module;

and the clock control circuit module is used for generating clock signals required by the counter circuit module, and the counter circuit module completes the counting function under the beat of the clock signals.

Preferably, the readout circuit module comprises a bias control circuit, a current mirror circuit, a comparator circuit, and an on-chip adjustable resistance circuit;

the bias control circuit is used for generating a direct-current bias voltage signal VBIAS and providing the direct-current bias voltage signal VBIAS for the current mirror circuit;

the current mirror circuit generates two paths of currents, wherein the first path of current is provided for the adjustable resistor circuit, and the second path of current is provided for the off-chip resistor;

one end of the on-chip adjustable resistor circuit is connected with the node A1, and the other end of the on-chip adjustable resistor circuit is grounded and controlled by a first digital control word CTRL 1; one end of the external reference resistor R1 is connected with the node A2, and the other end is grounded; the positive input end of the comparator circuit is connected with the node A1, the negative input end of the comparator circuit is connected with the node A2, and the output end of the comparator circuit is connected with the node A3;

when the voltage V1 of the A1 node is larger than the voltage V2 of the A2 node, the comparator outputs a high level, and when the voltage V1 of the A1 node is smaller than the voltage V2 of the A2 node, the comparator outputs a low level; when the first digital control word CTRL1 is increased, the resistance of the on-chip adjustable resistance circuit is reduced, and the voltage V1 of the node A1 is reduced; when the first digital control word CTRL1 decreases, the resistance of the on-chip adjustable resistance circuit increases, and the voltage V1 at node A1 increases.

Preferably, the current mirror circuit comprises a power supply, PMOS tubes M1 and M2; the DC bias voltage signal VBIAS is connected to the grid electrodes of the PMOS tubes M1 and M2, the sources of the M1 and M2 are commonly connected to the power supply voltage, the drain electrode of the M2 is connected with the node A2, the drain electrode of the M1 is connected with the node A1, the current of the MOS tube M2 in the current mirror circuit generates a voltage V2 at the node A2 through an off-chip resistor R1, and the current of the M1 generates a voltage V1 at the node A1 through an on-chip adjustable resistor.

Preferably, a certain scale factor k exists in the magnitude of the two paths of current generated by the current mirror circuit, and the magnitude of the scale factor k is determined by the ratio of the adjustable resistor to the external reference resistor R1:

k=the resistance of the off-chip reference resistor R1/the resistance of the on-chip adjustable resistor circuit.

Preferably, the adjustable resistor comprises a parallel resistor string and a switch control circuit;

the adjustable resistor comprises a pair of resistors RA 0-RAn and switching tubes M31-M3 n, wherein the two resistors RA0 are connected in series at two ends of the adjustable resistor, a common node between the two resistors RA0 is a common mode voltage signal FB and is output to a switch control circuit, the two resistors RA1 are connected in series at two ends of the adjustable resistor through the switching tube M31, the two resistors RA2 are connected in series at two ends of the adjustable resistor through the switching tube M32, and the two resistors RAn are connected in series at two ends of the adjustable resistor through the switching tube M3n so as to adjust the resistance value at two ends of the adjustable resistor through the connection and disconnection of the switching tubes M31-M3 n; the resistance relationship between the resistors RA1 to RAn satisfies the exponential relationship RA2 = 2 x RA1, RA3 = 2 ² ×RA1，RAn＝2 ^n-1 ×RA1；

The input end of the switch control circuit comprises a common mode voltage signal FB and a first digital control word CTRL1, the first digital control signal CTRL1 is an M-bit binary number, the first digital control signal CTRL1 is decoded to generate n-bit digital control signals K1-Kn, when the M-bit binary number represented by the first digital control signal CTRL1 is converted into decimal i-1, the digital control signal Ki outputs a high level, a fixed differential pressure is formed between the high level and the common mode voltage signal FB, the rest digital control signals output low levels, and the gates of switching tubes M31-M3 n connected with the digital control signals K1-Kn are used for controlling the switching tubes M31-M3 n in the parallel resistor string to be turned on and off.

Preferably, the switch control circuit comprises a high voltage generating circuit, a decoding logic circuit and n switch control units, wherein each switch control unit comprises a current source Ii, MOS tubes M4i, M5i and M6i, and i=1 to n;

the high voltage generation circuit is used for generating a voltage higher than a power supply voltage;

the decoding logic circuit generates enabling signals EN1 to ENn according to the first digital control word CTRL 1; when the m-bit binary number represented by the first digital control signal CTRL1 is converted into decimal i-1, the enable signal ENi is high level, and the rest enable signals are low level;

the current source Ii is connected with the output end of the high-voltage generating circuit and the drain electrode of the MOS tube M4i, the MOS tube M4i generates a signal Ki in a diode connection mode, the source electrode of the M4i is connected with the source electrode of the M5i, the grid electrode of the M5i is connected with the common mode voltage signal FB, the drain electrode is grounded, the drain electrode of the M6i is connected with the grid electrode of the M4i, the source electrode of the M6i is connected with the ENi, and the grid electrode of the M6i is connected with the power supply voltage VDD;

when ENi is at a logic low level, since M6i is on, ki is also at the logic low level, and the switch tube M3i is off; when ENi is at logic high level, M6i is in an off state, the voltage value of Ki is common-mode voltage signal FB plus the gate-source voltages of M4i and M5i, and the source voltage and the drain voltage of switching tube M3i are equal to common-mode voltage signal FB.

Preferably, the input end of the counter circuit module comprises an enable signal EN, a reset signal RST, a clock signal CLK3 and a counting control signal CTRL, the output end comprises a first digital control word CTRL1 and a second digital control word CTRL2, and the digital counter circuit and the latch circuit are contained inside;

when the counting control signal CTRL is in a high level, a first digital control word CTRL1 of the digital counter circuit is added with 1 until the counting control signal CTRL is in a low level, and at the moment, the latch circuit latches the first digital control word CTRL1 and outputs the first digital control word CTRL1 to a second digital control word CTRL2 to adjust an on-chip adjustable resistor R3 to be calibrated;

when the count control signal CTRL is at a low level, the digital counter circuit outputs a first digital control word CTRL1 minus 1 until the count control signal CTRL is at a high level, at which time the latch circuit latches the first digital control word CTRL1 and outputs the first digital control word CTRL1 to a second digital control word CTRL2, and adjusts the on-chip adjustable resistor R3 to be calibrated.

Preferably, the external reference resistor R1 is a resistor with an accuracy higher than 0.1%. Compared with the prior art, the invention has the beneficial effects that:

(1) The on-chip resistor calibration circuit has the advantage of high precision, and realizes high-precision calibration of the on-chip resistor, because the calibration is compared with the off-chip high-precision resistor, the adjustment error of the on-chip resistor value is less than 5%;

(2) The two paths of currents generated by the current mirror in the readout circuit have a certain scaling factor k, and different scaling factors k can be selected according to the size of the on-chip adjustable resistor, wherein k=the resistance value of the off-chip resistor/the resistance value of the adjustable resistor R2. The circuit has a very large resistance calibration range;

(3) The counter has the data latching function, can preset the initial value after power-on, selects different initial values according to different process deviations, can reduce the number of calibration cycles and shorten the resistance calibration time;

(4) The control switch in the on-chip adjustable resistor adopts a grid voltage bootstrap technology, so that the on-resistance can be reduced and kept stable, the change caused by the change of signals can be avoided, the non-ideal effect of the switch is reduced, and the resistor calibration precision is improved.

(5) The external reference resistor is a resistor with the precision higher than 0.1%, is connected with one current mirror in the reading circuit and is used for generating reference voltage, and the calibration precision is greatly improved.

Drawings

FIG. 1 is a schematic diagram of an on-chip resistor calibration circuit according to an embodiment of the present invention;

FIG. 2 (a) is a schematic diagram of an on-chip adjustable resistor circuit in a series configuration according to an embodiment of the present invention;

FIG. 2 (b) is a schematic diagram of an on-chip adjustable resistor circuit in parallel configuration according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of the internal components of an on-chip adjustable resistor circuit according to an embodiment of the present invention;

FIG. 4 is a diagram of a switch control circuit according to an embodiment of the present invention;

FIG. 5 is a flow chart of a resistor calibration control according to an embodiment of the present invention.

Detailed Description

The invention will be described in detail below with reference to the drawings and the specific embodiments.

Because the input signal frequency of the ultra-high speed analog-to-digital converter is high, receiving the high frequency signal is a great challenge, and the integrity of the received signal is maintained by designing an accurate on-chip input matching resistor. In order to realize high-precision and wide-range resistance value calibration, the invention adopts a digital-analog hybrid design method, uses an external reference resistor as a benchmark, adopts a high-precision on-chip resistance calibration circuit, and can accurately calibrate the resistance value of the on-chip resistor, thereby realizing a wider resistance value adjustment range and being applicable to various application fields requiring accurate on-chip resistance.

As shown in fig. 1, the present invention provides a high-precision on-chip resistor calibration circuit, which is composed of a readout circuit module 101, a counter circuit module 102, a calibration control circuit module 103, a clock control circuit module 104, and an external reference resistor R1. Wherein:

the readout circuit module 101 generates voltages at the external reference resistor R1 and two ends (two nodes A1 and A2) of the on-chip resistor circuit respectively by using an internal current mirror, compares the voltages at the two ends of the external reference resistor R1 with the voltages at the two ends of the on-chip adjustable resistor circuit, and generates a count control signal CTRL according to the comparison result to output to the counter circuit module 102; when the voltage at two ends of the external reference resistor R1 is smaller than the voltage at two ends of the on-chip adjustable resistor circuit, the counting control signal CTRL is a high-level signal, otherwise, the counting control signal CTRL is a low-level signal, and the counting control signal CTRL is output to the counter circuit module 102;

the counter circuit module 102 is internally provided with a digital counter, when the count control signal CTRL is a high-level signal, the count value of the digital counter is increased, otherwise, the count value of the digital counter is decreased, the count value of the digital counter is used as a first digital control word CTRL1 to latch and control an on-chip adjustable resistor circuit of the readout circuit module 101, the resistance value of the on-chip adjustable resistor circuit is adjusted until the state of the count control signal CTRL representing the voltage of two ends of an external reference resistor R1 and the voltage of two ends of the on-chip adjustable resistor circuit in the readout circuit module 101 changes, and the on-chip adjustable resistor R3 to be calibrated is adjusted according to the first digital control word CTRL1 latched at the moment, so that the on-chip adjustable resistor R3 to be calibrated reaches a desired resistance value, and the on-chip resistor calibration is completed;

a calibration control circuit module 103 for generating control signals, enable signals and reset signals for the whole calibration period to control the enable states and reset of the readout circuit module 101 and the counter circuit module 102;

the clock control circuit module 104 is configured to generate a clock required by the counter circuit module 102, control a timing relationship between the counter circuit module 102 and the calibration control circuit module 103, and make the whole calibration circuit work according to a correct timing, for example, the counter circuit module 102 performs a counting function under a clock signal.

In the circuit, the on-chip adjustable resistor R3 to be calibrated and the on-chip adjustable resistor circuit are formed by serially connecting or parallelly connecting adjustable resistor units, the structural form of the on-chip adjustable resistor circuit is the same as that of the on-chip adjustable resistor R3 to be calibrated, and the initial value resistance of the on-chip adjustable resistor circuit is larger than the expected resistance of the on-chip adjustable resistor R3 to be calibrated. In order to improve the accuracy of the calibration, the external reference resistor R1 is preferably a resistor having an accuracy higher than 0.1%.

The readout circuit module 101 is composed of a bias control circuit, a current mirror circuit, an on-chip trimming resistor circuit, and a comparator circuit.

As shown in fig. 1, the bias control circuit generates a dc bias voltage VBIAS, which is provided to the current mirror circuit;

the current mirror circuit generates two paths of currents, wherein the first path of current is provided for the adjustable resistor circuit, and the second path of current is provided for the off-chip resistor;

the current mirror circuit comprises a power supply, PMOS tubes M1 and M2; the DC bias voltage VBIAS is connected to the grid electrodes of the PMOS tubes M1 and M2 in the current mirror circuit, the sources of the M1 and M2 are commonly connected to the power supply voltage, the drain electrode of the M2 is connected with the node A2, the drain electrode of the M1 is connected with the node A1, the current of the MOS tube M2 in the current mirror circuit generates a voltage V2 at the node A2 through an off-chip resistor R1, and the current of the M1 generates a voltage V1 at the node A1 through an on-chip adjustable resistor.

One end of the on-chip adjustable resistor circuit is connected with the node A1, and the other end of the on-chip adjustable resistor circuit is grounded and controlled by a first digital control word CTRL 1; one end of the external reference resistor R1 is connected with the node A2, and the other end is grounded; the positive input end of the comparator circuit is connected with the node A1, the negative input end of the comparator circuit is connected with the node A2, and the output end of the comparator circuit is connected with the node A3;

when the voltage V1 of the A1 node is larger than the voltage V2 of the A2 node, the comparator outputs a high level, and when the voltage V1 of the A1 node is smaller than the voltage V2 of the A2 node, the comparator outputs a low level; when the first digital control word CTRL1 is increased, the resistance of the on-chip adjustable resistance circuit is reduced, and the voltage V1 of the node A1 is reduced; when the first digital control word CTRL1 decreases, the resistance of the on-chip adjustable resistance circuit increases, and the voltage V1 at node A1 increases.

Assuming that the voltage V1 at the node A1 is greater than the voltage V2 at the node A2, the comparator outputs a high level, and the counter circuit outputs a digital control signal CTRL1 plus 1 at this time, so that the resistance of the on-chip adjustable resistor R2 decreases, the voltage V1 at the node A1 decreases accordingly, and the comparator compares the magnitudes of V1 and V2 again until the voltage V1 at the node A1 is less than the voltage V2 at the node A2. The reason when the voltage V1 of the node A1 is smaller than the voltage V2 of the node A2 is the same, and the description is omitted.

As shown in fig. 2 (a) and 2 (b), the on-chip adjustable resistor circuit is composed of a plurality of adjustable resistors RA, each controlled by the first digital control word CTRL1, which are independent of N and are identical in series or parallel, and are related to the R3 resistance. The first digital control word CTRL1 is m bits and the initial value may be set to 1000 …. The high-low level signal output from the readout circuit module 101 is received, the count value is adjusted, the count is started from the initial value 1000, and then a variable digital control signal binary is output, and the variable digital control signal binary is output to the on-chip resistor circuit of the readout circuit module 101, and the resistance value is adjusted.

As shown in fig. 3, R2 in fig. 1 may be formed by connecting n RA in series or in parallel, as shown in fig. 2, a specific structure of each RA is that an adjustable resistor in the on-chip adjustable resistor circuit shown in fig. 3 is formed by connecting a resistor string in parallel with a switch control circuit, and fig. 4 is a specific structure diagram of the switch control circuit.

The adjustable resistor comprises a pair of resistors RA 0-RAn and switching tubes M31-M3 n, wherein the two resistors RA0 are connected in series at two ends of the adjustable resistor, a common node between the two resistors is a common mode voltage signal FB and is output to a switch control circuit, the two resistors RA1 are connected in series at two ends of the adjustable resistor through the switching tube M31, and the two resistors RA2 are connected in series at two ends of the adjustable resistor through a switching tube M32, and similarly, two resistors RAn are connected in series at two ends of the adjustable resistor through a switching tube M3n, and the resistance values at two ends of the adjustable resistor are adjusted through the on and off of the switching tubes M31-M3 n; the resistance relationship between the resistors RA1 to RAn satisfies the exponential relationship RA2 = 2 x RA1, RA3 = 2 ² ×RA1，RAn＝2 ^n-1 ×RA1；

The input end of the switch control circuit comprises a common mode voltage signal FB and a first digital control word CTRL1, the first digital control signal CTRL1 is an M-bit binary number, the first digital control signal CTRL1 is decoded to generate n-bit digital control signals K1-Kn, when the M-bit binary number represented by the first digital control signal CTRL1 is converted into decimal i-1, the digital control signal Ki outputs a high level, a fixed differential pressure is formed between the high level and the common mode voltage signal FB, the rest digital control signals output low levels, and the gates of switching tubes M31-M3 n connected with the digital control signals K1-Kn are used for controlling the switching tubes M31-M3 n in the parallel resistor strings to be turned on and off, so that the resistance value between the nodes T5 and T6 can be adjusted.

As shown in fig. 4, the switch control circuit includes a high voltage generating circuit, a decoding logic circuit, and n switch control units, each of which includes a current source Ii, MOS transistors M4i, M5i, M6i, i=1 to n.

The high voltage generating circuit is used for generating a voltage higher than the power supply voltage, typically about 2 times the power supply voltage.

The decoding logic circuit generates enabling signals EN1 to ENn according to the first digital control word CTRL 1; when the m-bit binary number represented by the first digital control signal CTRL1 is converted to decimal i-1, the enable signal ENi is high and the remaining enable signals are low.

The current source Ii is connected with the output end of the high-voltage generating circuit and the drain electrode of the MOS tube M4i, the MOS tube M4i generates a signal Ki in a diode connection mode, the source electrode of the M4i is connected with the source electrode of the M5i, the grid electrode of the M5i is connected with the common mode voltage signal FB, the drain electrode is grounded, the drain electrode of the M6i is connected with the grid electrode of the M4i, the source electrode of the M6i is connected with the ENi, and the grid electrode of the M6i is connected with the power supply voltage VDD;

when ENi is at a logic low level, since M6i is on, ki is also at the logic low level, and the switch tube M3i is off; when ENi is at logic high level, M6i is in an off state, the voltage value of Ki is common-mode voltage signal FB plus the gate-source voltages of M4i and M5i, and the source voltage and the drain voltage of switching tube M3i are equal to common-mode voltage signal FB.

The method comprises the following steps: the current source I1 is connected with the output end of the high-voltage generating circuit and the drain electrode of the MOS tube M41, the MOS tube M41 generates a signal K1 in a diode connection mode, the source electrode of the M41 is connected with the source electrode of the M51, the grid electrode of the M51 is connected with the FB, the drain electrode is grounded, the drain electrode of the M61 is connected with the grid electrode of the M41, the source electrode of the M61 is connected with the EN1, and the grid electrode of the M61 is connected with the power supply voltage VDD. The connection relationship between the current source In and the MOS transistors M4n, M5n, M6n is the same as the connection relationship between the current source I1 and the MOS transistors M41, M51, M61, and will not be described again.

When EN1 is at a logic low level, since M61 is on, K1 is also at a logic low level, and the switching transistor M31 is off. When EN1 is at logic high level, M61 is in off state, the voltage value of K1 is determined by M41 and M51, at this time, the voltage value of K1 is FB plus the gate-source voltages of M41 and M51, the source voltage and the drain voltage of the switching tube M31 are about equal to FB, so that the gate-source voltage of M31 is the gate-source voltage of M41 plus the gate-source voltage of M51, which is related to the current source I1 only and is unrelated to FB, so that the gate-source voltage of the switching tube M31 is a fixed value unrelated to FB, which can ensure the linearity of the switching tube and improve the adjustment accuracy of the resistor.

The counter circuit block 102 has an input terminal including an enable signal EN, a reset signal RST, a clock signal CLK3, a control signal CTRL, and an output terminal including a first digital control word CTRL1 and a second digital control word CTRL2. The digital counter circuit and the latch circuit are contained inside.

When the count control signal CTRL is at a high level, the first digital control word CTRL1 output by the digital counter circuit is added with 1 until the count control signal CTRL is at a low level, and at this time, the latch circuit latches the first digital control word CTRL1 and outputs the first digital control word CTRL1 to the second digital control word CTRL2, so as to adjust the on-chip adjustable resistor R3 to be calibrated.

When the count control signal CTRL is at a low level, the digital counter circuit outputs a first digital control word CTRL1 minus 1 until the count control signal CTRL is at a high level, at which time the latch circuit latches the first digital control word CTRL1 and outputs the first digital control word CTRL1 to a second digital control word CTRL2, and adjusts the on-chip adjustable resistor R3 to be calibrated.

The calibration control circuit block 103 has an input terminal including a power-on reset signal, a calibration command signal, and a clock signal CLK, and an output terminal including an enable signal EN, an enable signal EN3, and a reset signal RST. The power-on reset signal is a power-on pulse signal for resetting the whole calibration control circuit, the command calibration signal is used for controlling whether the calibration control circuit starts calibration, the enable signal EN3 is used for controlling the enable state of the readout circuit, the enable signal EN is used for controlling the enable state of the counter circuit, and the reset signal RST is used for resetting the counter circuit.

The clock control circuit block 104 has an input comprising a clock signal CLK and an output comprising a clock signal CLK3 for clocking the counter circuit.

As shown in fig. 5, the entire on-chip resistance calibration process is as follows:

1. enabling a calibration command and starting a calibration flow;

2. starting a calibration circuit, and outputting a counting control signal CTRL by a reading circuit;

3. adjusting the digital counter to output a digital code and adjusting the resistance value of R2;

4. comparing the voltage values of nodes A1 and A2;

5. judging whether calibration is finished, if the voltages of the nodes A1 and A2 are equal or the relationship between the voltages is changed, finishing the calibration, otherwise, repeating the step 5;

6. a latch in the counter circuit module latches the value output by the digital counter and outputs the value to R3, and the resistance value of R3 is adjusted;

7. closing the calibration circuit;

8. turning on a calibration independent circuit;

9. the calibration is completed.

In summary, the present invention provides an on-chip resistor calibration circuit, which can accurately adjust the resistance value of an on-chip resistor which changes due to process fluctuation, and the on-chip resistor calibration circuit adopts an analog-digital hybrid control method to realize high-precision calibration of an on-chip resistor, wherein the adjustment error of the on-chip resistor is less than 5%, so that the matching between a chip and an external input signal source meets the requirement, and the on-chip resistor calibration circuit is favorable for ensuring the integrity and reliability of signal reception.

It should be noted that, although the specific resistor calibration circuit and the constituent modules are described in the specific embodiments of the present invention, the descriptions of these specific circuits are only for illustrating the content of the present invention. Various changes and modifications may be made to the examples of the invention without departing from the principles of the invention, but such modifications are intended to be within the scope of the claims. The present invention is therefore broad.

The present invention is not an undue matter of the prior art.

Claims (9)

1. An on-chip resistor calibration circuit is characterized by comprising a read-out circuit module (101), a counter circuit module (102) and an external reference resistor R1;

the reading circuit module (101) is used for generating voltages at two ends of the external reference resistor R1 and the on-chip adjustable resistor circuit respectively by using a current mirror, comparing the voltages at two ends of the external reference resistor R1 and the voltages at two ends of the on-chip adjustable resistor circuit, generating a counting control signal CTRL according to a comparison result and outputting the counting control signal CTRL to the counter circuit module (102); when the voltage at two ends of the external reference resistor R1 is smaller than the voltage at two ends of the on-chip adjustable resistor circuit, the counting control signal CTRL is a high-level signal, otherwise, the counting control signal CTRL is a low-level signal;

the counter circuit module (102) is internally provided with a digital counter, when the count control signal CTRL is a high-level signal, the count value of the digital counter is increased, otherwise, the count value of the digital counter is decreased, the count value of the digital counter is used as a first digital control word CTRL1 to latch and control an on-chip adjustable resistor circuit of the readout circuit module (101), the resistance value of the on-chip adjustable resistor circuit is adjusted until the state of the count control signal CTRL representing the relation between the voltage at two ends of an external reference resistor R1 and the voltage at two ends of the on-chip adjustable resistor circuit in the readout circuit module (101) changes, and the on-chip adjustable resistor R3 to be calibrated is adjusted according to the first digital control word CTRL1 latched at the moment, so that the on-chip adjustable resistor R3 to be calibrated reaches the expected resistance value, and the on-chip resistor calibration is completed;

the on-chip adjustable resistor R3 to be calibrated and the on-chip adjustable resistor circuit are formed by serially connecting or parallelly connecting adjustable resistor units, the structural form of the on-chip adjustable resistor circuit is the same as that of the on-chip adjustable resistor R3 to be calibrated, and the initial value resistance of the on-chip adjustable resistor circuit is larger than the expected resistance of the on-chip adjustable resistor R3 to be calibrated.

2. An on-chip resistor calibration circuit according to claim 1, further comprising a calibration control circuit module (103), a clock control circuit module (104);

a calibration control circuit module (103) for generating a control signal for the whole calibration period, and controlling the enabling and resetting of the readout circuit module (101) and the counter circuit module (102);

and the clock control circuit module (104) is used for generating clock signals required by the counter circuit module (102), and the counter circuit module (102) completes the counting function under the beat of the clock signals.

3. An on-chip resistor calibration circuit according to claim 1, characterized in that the readout circuit module (101) comprises a bias control circuit, a current mirror circuit, a comparator circuit, an on-chip adjustable resistor circuit;

the bias control circuit is used for generating a direct-current bias voltage signal VBIAS and providing the direct-current bias voltage signal VBIAS for the current mirror circuit;

the current mirror circuit generates two paths of currents, wherein the first path of current is provided for the adjustable resistor circuit, and the second path of current is provided for the off-chip resistor;

one end of the on-chip adjustable resistor circuit is connected with the node A1, and the other end of the on-chip adjustable resistor circuit is grounded and controlled by a first digital control word CTRL 1; one end of the external reference resistor R1 is connected with the node A2, and the other end is grounded; the positive input end of the comparator circuit is connected with the node A1, the negative input end of the comparator circuit is connected with the node A2, and the output end of the comparator circuit is connected with the node A3;

when the voltage V1 of the A1 node is larger than the voltage V2 of the A2 node, the comparator outputs a high level, and when the voltage V1 of the A1 node is smaller than the voltage V2 of the A2 node, the comparator outputs a low level; when the first digital control word CTRL1 is increased, the resistance of the on-chip adjustable resistance circuit is reduced, and the voltage V1 of the node A1 is reduced; when the first digital control word CTRL1 decreases, the resistance of the on-chip adjustable resistance circuit increases, and the voltage V1 at node A1 increases.

4. An on-chip resistor calibration circuit according to claim 1, wherein the current mirror circuit comprises a power supply, PMOS transistors M1 and M2; the DC bias voltage signal VBIAS is connected to the grid electrodes of the PMOS tubes M1 and M2, the sources of the M1 and M2 are commonly connected to the power supply voltage, the drain electrode of the M2 is connected with the node A2, the drain electrode of the M1 is connected with the node A1, the current of the MOS tube M2 in the current mirror circuit generates a voltage V2 at the node A2 through an off-chip resistor R1, and the current of the M1 generates a voltage V1 at the node A1 through an on-chip adjustable resistor.

5. An on-chip resistor calibration circuit according to claim 1 wherein the magnitude of the two currents generated by the current mirror circuit has a scaling factor k, the magnitude of the scaling factor k being determined by the ratio of the adjustable resistor to the external reference resistor R1:

k=the resistance of the off-chip reference resistor R1/the resistance of the on-chip adjustable resistor circuit.

6. An on-chip resistor calibration circuit according to claim 1 wherein the adjustable resistor comprises a parallel resistor string and a switch control circuit;

the adjustable resistor comprises a pair of resistors RA 0-RAn and switching tubes M31-M3 n, wherein the two resistors RA0 are connected in series at two ends of the adjustable resistor, a common node between the two resistors is a common mode voltage signal FB, and the common mode voltage signal FB is output to the switching control circuitTwo resistors RA1 are connected in series at two ends of the adjustable resistor through a switching tube M31, two resistors RA2 are connected in series at two ends of the adjustable resistor through a switching tube M32, and the like, two resistors RAn are connected in series at two ends of the adjustable resistor through a switching tube M3n, and the resistance values at two ends of the adjustable resistor are adjusted through the on and off of the switching tubes M31-M3 n; the resistance relationship between the resistors RA1 to RAn satisfies the exponential relationship RA2 = 2 x RA1, RA3 = 2 ² ×RA1，RAn＝2 ^n-1 ×RA1；

The input end of the switch control circuit comprises a common mode voltage signal FB and a first digital control word CTRL1, the first digital control signal CTRL1 is an M-bit binary number, the first digital control signal CTRL1 is decoded to generate n-bit digital control signals K1-Kn, when the M-bit binary number represented by the first digital control signal CTRL1 is converted into decimal i-1, the digital control signal Ki outputs a high level, a fixed differential pressure is formed between the high level and the common mode voltage signal FB, the rest digital control signals output low levels, and the gates of switching tubes M31-M3 n connected with the digital control signals K1-Kn are used for controlling the switching tubes M31-M3 n in the parallel resistor string to be turned on and off.

7. An on-chip resistor calibration circuit according to claim 6, wherein the switch control circuit comprises a high voltage generation circuit, a decoding logic circuit and n switch control units, each switch control unit comprising a current source Ii, MOS transistors M4i, M5i, M6i, i=1 to n;

the high voltage generation circuit is used for generating a voltage higher than a power supply voltage;

the decoding logic circuit generates enabling signals EN1 to ENn according to the first digital control word CTRL 1; when the m-bit binary number represented by the first digital control signal CTRL1 is converted into decimal i-1, the enable signal ENi is high level, and the rest enable signals are low level;

the current source Ii is connected with the output end of the high-voltage generating circuit and the drain electrode of the MOS tube M4i, the MOS tube M4i generates a signal Ki in a diode connection mode, the source electrode of the M4i is connected with the source electrode of the M5i, the grid electrode of the M5i is connected with the common mode voltage signal FB, the drain electrode is grounded, the drain electrode of the M6i is connected with the grid electrode of the M4i, the source electrode of the M6i is connected with the ENi, and the grid electrode of the M6i is connected with the power supply voltage VDD;

when ENi is at a logic low level, since M6i is on, ki is also at the logic low level, and the switch tube M3i is off; when ENi is at logic high level, M6i is in an off state, the voltage value of Ki is common-mode voltage signal FB plus the gate-source voltages of M4i and M5i, and the source voltage and the drain voltage of switching tube M3i are equal to common-mode voltage signal FB.

8. An on-chip resistor calibration circuit according to claim 1, characterized in that the input of the counter circuit module (102) comprises an enable signal EN, a reset signal RST, a clock signal CLK3, a count control signal CTRL, the output comprises a first digital control word CTRL1 and a second digital control word CTRL2, and the digital counter circuit and the latch circuit are internally comprised;

when the counting control signal CTRL is in a high level, a first digital control word CTRL1 of the digital counter circuit is added with 1 until the counting control signal CTRL is in a low level, and at the moment, the latch circuit latches the first digital control word CTRL1 and outputs the first digital control word CTRL1 to a second digital control word CTRL2 to adjust an on-chip adjustable resistor R3 to be calibrated;

when the count control signal CTRL is at a low level, the digital counter circuit outputs a first digital control word CTRL1 minus 1 until the count control signal CTRL is at a high level, at which time the latch circuit latches the first digital control word CTRL1 and outputs the first digital control word CTRL1 to a second digital control word CTRL2, and adjusts the on-chip adjustable resistor R3 to be calibrated.

9. An on-chip resistor calibration circuit according to claim 1 wherein the external reference resistor R1 is a resistor with an accuracy of greater than 0.1%.