CN113890405B - Pulse forward carrier phase-shifting sine pulse width modulation method for eliminating MMC common mode voltage - Google Patents

Pulse forward carrier phase-shifting sine pulse width modulation method for eliminating MMC common mode voltage Download PDF

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CN113890405B
CN113890405B CN202110955314.7A CN202110955314A CN113890405B CN 113890405 B CN113890405 B CN 113890405B CN 202110955314 A CN202110955314 A CN 202110955314A CN 113890405 B CN113890405 B CN 113890405B
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sub
module
bridge arm
phase
pulse
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CN113890405A (en
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李虹
王佳信
褚召义
王作兴
邵天骢
李志君
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Beijing Jiaotong University
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/505—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
    • H02M7/515—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
    • H02M7/525—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with automatic control of output waveform or frequency
    • H02M7/527—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only with automatic control of output waveform or frequency by pulse width modulation
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/505—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
    • H02M7/515—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
    • H02M7/521—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only in a bridge configuration
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02E60/60—Arrangements for transfer of electric power between AC networks or generators via a high voltage DC link [HVCD]

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Inverter Devices (AREA)

Abstract

The application provides a pulse sequential carrier phase-shifting sinusoidal pulse width modulation method for eliminating MMC common mode voltage, which relates to the technical field of power electronics, wherein the method comprises the following steps: step S1: comparing the modulated wave with a carrier wave to obtain a pulse signal; step S2: capturing a pulse falling edge of a pulse signal; step S3: the sub-modules are grouped and the drive pulse of the switching tube is generated by the falling edge of the captured pulse. The application can eliminate common-mode voltage of MMC system, effectively reduce leakage current and common-mode noise of system, and effectively solve the technical problems of leakage current and common-mode interference generated by stray capacitance of high-frequency common-mode voltage in the prior MMC, and endangering motor bearing and communication system.

Description

Pulse forward carrier phase-shifting sine pulse width modulation method for eliminating MMC common mode voltage
Technical Field
The application relates to the technical field of power electronics, in particular to a pulse-forward carrier phase-shifting sine pulse width modulation method and device for eliminating MMC common mode voltage.
Background
MMC has been used as a power electronic converter with wide application prospect in the fields of medium and high voltage, and has many advantages: low loss, low step voltage, low electromagnetic interference, etc. The MMC circuit structure is shown in fig. 3, and the modulation modes of the MMC are mainly divided into two types: (1) low switching frequency modulation, such as: recent level approximation modulation, selective harmonic cancellation modulation; (2) high switching frequency modulation, such as: carrier phase-shifting sinusoidal pulse width modulation and carrier stacked sinusoidal pulse width modulation.
However, in current MMC research, little is done on common mode voltage. In practice, there is a common mode voltage at high frequency jumps in MMC, whereWhen carrier phase-shifting sinusoidal pulse width modulation is used, the amplitude of each jump of MMC common-mode voltage is about U dc and/6N, the presence of which is not negligible. The high-frequency common-mode voltage can generate leakage current and common-mode interference through stray capacitance, and damage to motor bearings, communication systems and the like is needed to be solved.
Disclosure of Invention
The present application aims to solve at least one of the technical problems in the related art to some extent.
Therefore, the first purpose of the application is to provide a pulse-sequential carrier phase-shifting sinusoidal pulse width modulation method for eliminating MMC common-mode voltage, which solves the technical problems of leakage current and common-mode interference generated by stray capacitance in the prior MMC and damaging motor bearings, communication systems and the like, eliminates common-mode voltage high-frequency jump, and effectively reduces system leakage current and common-mode noise.
The second objective of the present application is to provide a pulse-forward carrier phase-shifting sinusoidal pulse width modulation device for eliminating common mode voltage of MMC.
A third object of the present application is to propose a non-transitory computer readable storage medium.
To achieve the above objective, an embodiment of a first aspect of the present application provides a pulse-sequential carrier phase-shifting sinusoidal pulse width modulation method for eliminating common mode voltage of an MMC, including step S1: comparing the modulated wave with a carrier wave to obtain a pulse signal; step S2: capturing a pulse falling edge of a pulse signal; step S3: the sub-modules are grouped and the drive pulse of the switching tube is generated by the falling edge of the captured pulse.
Optionally, in an embodiment of the present application, the modulated wave is compared with a carrier wave to obtain a pulse signal, specifically based on pulse width modulation, an isosceles triangle carrier wave is adopted, the carrier waves corresponding to the sub-modules are arranged in a phase-shifting manner, and the pulse signal corresponding to each sub-module is obtained by comparing the modulated wave signal with the carrier wave signal, where when the modulated wave signal is greater than the carrier wave signal, a high level signal is output, and when the modulated wave signal is less than the carrier wave signal, a low level signal is output.
Alternatively, in one embodiment of the present application, when the pulse signal changes from high to low, the falling edge capture signal outputs a high level for one clock cycle, and at other times, the falling edge capture signal outputs always a low level, expressed as:
wherein u is neg,jkl0 Representing the falling edge acquisition signal, u jkl0 The pulse signal obtained by comparing the modulated wave with the carrier wave is represented by j, k represents the phase unit of the MMC, k represents the upper bridge arm and the lower bridge arm, l represents the serial numbers of the submodules, and T represents the clock period of the digital circuit.
Optionally, in one embodiment of the present application, the sub-modules are grouped, specifically, the upper bridge arm and the lower bridge arm are divided into a predetermined number of ordered sub-module groups, and the driving pulses of six sub-modules in one sub-module group are expressed as follows in sequence:
wherein u is akl Drive signal representing the first sub-module of a-phase k bridge arm, u bkl Drive signal representing the l-th sub-module of the b-phase k bridge arm, u ckl Drive signal representing the first submodule of the c-phase k-arm, u ak(N/2+l) Drive signal representing N/2+l sub-module of a-phase k bridge arm, u bk(N/2+l) Drive signal representing N/2+l sub-module of b-phase k-arm, u ck(N/2+l) N/2+l sub-module representing c-phase k bridge arm, u neg,akl0 A falling edge capturing signal of pulse signal obtained by comparing modulated wave of first submodule of a phase k bridge arm with carrier wave, u neg,bkl0 A falling edge capturing signal of a pulse signal obtained by comparing a modulated wave of an l sub-module of a b-phase k bridge arm with a carrier wave, u neg,ckl0 A falling edge capturing signal representing a pulse signal obtained by comparing a modulated wave of an l sub-module of a c-phase k bridge arm with a carrier wave, u neg,ak(N/2+l)0 A falling edge capturing signal of pulse signal obtained by comparing a modulated wave of N/2+l th submodule of a phase k bridge arm with carrier wave, u neg,bk(N/2+l)0 Capturing a signal on the falling edge of a pulse signal obtained by comparing a modulated wave of a N/2+l th submodule of a b-phase k bridge arm with a carrier wave, and u neg,ck(N/2+l)0 The method comprises the steps of representing a falling edge capturing signal of a pulse signal obtained by comparing a modulated wave of a c-phase k bridge arm N/2+l sub-module with a carrier wave, wherein N represents the number of the sub-modules, and T represents a clock period of a digital circuit.
Optionally, in one embodiment of the application, the resulting submodule drive pulses have the following characteristics:
the driving pulse falling edge of the first sub-module of the a-phase upper bridge arm is at the same time as the driving pulse rising edge of the N/2+l sub-module of the b-phase upper bridge arm, the driving pulse falling edge of the N/2+l sub-module of the b-phase upper bridge arm is at the same time as the driving pulse rising edge of the first sub-module of the c-phase upper bridge arm, the driving pulse falling edge of the first sub-module of the c-phase upper bridge arm is at the same time as the driving pulse rising edge of the N/2+l sub-module of the a-phase upper bridge arm, the driving pulse falling edge of the N/2+l sub-module of the a-phase upper bridge arm is at the same time as the driving pulse rising edge of the first sub-module of the b-phase upper bridge arm, and the driving pulse falling edge of the first sub-module of the b-phase upper bridge arm is at the same time as the driving pulse rising edge of the N/2+l sub-module of the c-phase upper bridge arm.
In order to achieve the above object, a second aspect of the present application provides a pulse-sequential carrier phase-shifting sinusoidal pulse width modulation device for eliminating common mode voltage of MMC, which comprises a comparing module, a capturing module, and a generating module, wherein,
the comparison module is used for comparing the modulated wave with the carrier wave to obtain a pulse signal;
the capturing module is used for capturing the pulse falling edge of the pulse signal;
and the generation module is used for grouping the sub-modules and generating driving pulses of the switching tube through the falling edges of the captured pulses.
To achieve the above object, an embodiment of a third aspect of the present application provides a non-transitory computer-readable storage medium capable of performing a pulse-sequential carrier-phase-shift sinusoidal pulse width modulation method for eliminating an MMC common-mode voltage when instructions in the storage medium are executed by a processor.
The pulse forward carrier phase-shifting sinusoidal pulse width modulation method for eliminating the common mode voltage of the MMC, the pulse forward carrier phase-shifting sinusoidal pulse width modulation device for eliminating the common mode voltage of the MMC and a non-transitory computer readable storage medium solve the technical problems that the common mode voltage of the traditional MMC generates leakage current and common mode interference through stray capacitance, a motor bearing, a communication system and the like are damaged, and the purposes of effectively reducing the leakage current and common mode noise of the MMC and improving the working performance of the MMC are achieved by optimizing a sub-module switching sequence and eliminating common mode voltage high frequency jump in real time.
Additional aspects and advantages of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the application.
Drawings
The foregoing and/or additional aspects and advantages of the application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:
FIG. 1 is a flowchart of a pulse-forward carrier phase-shifting sinusoidal pulse width modulation method for eliminating MMC common mode voltage according to an embodiment of the present application;
FIG. 2 is another flowchart of a pulse-forward carrier phase-shifting sinusoidal pulse width modulation method for eliminating MMC common mode voltage according to an embodiment of the present application;
fig. 3 is a schematic circuit diagram of an MMC circuit according to a pulse-sequential carrier phase-shifting sinusoidal pulse width modulation method for eliminating an MMC common mode voltage according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a carrier wave and a modulated wave of a pulse-compliant carrier phase-shifting sinusoidal pulse width modulation according to an embodiment of the present application;
FIG. 5 is a timing chart showing a driving pulse forming process of one sub-module of the pulse-sequential carrier phase-shifting sinusoidal pulse width modulation method for eliminating MMC common mode voltage according to the embodiment of the present application;
FIG. 6 is a schematic diagram of driving pulses of all sub-modules of a sub-module group of a pulse-sequential carrier phase-shifting sinusoidal pulse width modulation method for eliminating common mode voltage of MMC according to an embodiment of the present application;
fig. 7 is a schematic diagram of a common mode voltage implemented by an MMC with 4 bridge arm submodules according to carrier phase-shifting sinusoidal pulse width modulation under the working conditions of bus voltage 800V, load current effective value 11.3A and modulation ratio 0.8 in the embodiment of the present application;
FIG. 8 is a schematic diagram of a common mode voltage of an MMC with 4 bridge arm submodules according to the present application under the working conditions of a bus voltage of 800V, a load current effective value of 11.3A, and a modulation ratio of 0.8;
fig. 9 is a schematic structural diagram of a pulse-forward carrier phase-shifting sinusoidal pulse width modulation device for eliminating common mode voltage of MMC according to a second embodiment of the present application.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present application and should not be construed as limiting the application.
The following describes a pulse-forward carrier phase-shifting sinusoidal pulse width modulation method and device for eliminating MMC common mode voltage according to an embodiment of the application with reference to the accompanying drawings.
Fig. 1 is a flowchart of a pulse-forward carrier phase-shifting sinusoidal pulse width modulation method for eliminating an MMC common-mode voltage according to an embodiment of the application.
As shown in fig. 1, the pulse-forward carrier phase-shifting sinusoidal pulse width modulation method for eliminating the common mode voltage of the MMC comprises the following steps:
step 101, comparing a modulated wave with a carrier wave to obtain a pulse signal;
step 102, capturing a pulse falling edge of a pulse signal;
step 103, grouping the sub-modules and generating the driving pulse of the switching tube by the captured pulse falling edge.
According to the pulse sequential carrier phase-shifting sinusoidal pulse width modulation method for eliminating the common mode voltage of the MMC, the modulated wave is compared with the carrier wave to obtain a pulse signal; capturing a pulse falling edge of a pulse signal; the sub-modules are grouped and the drive pulse of the switching tube is generated by the falling edge of the captured pulse. Therefore, the technical problems that the leakage current and common-mode interference are generated by the high-frequency common-mode voltage through the stray capacitance, the motor bearing, the communication system and the like in the existing MMC can be solved, the common-mode voltage high-frequency jump is eliminated in real time by optimizing the switching sequence of the submodule, and the purposes of effectively reducing the leakage current and the common-mode noise of the MMC and improving the working performance of the MMC are achieved.
Further, in the embodiment of the application, the modulated wave is compared with the carrier wave to obtain the pulse signal, specifically, based on pulse width modulation, an isosceles triangle carrier wave is adopted, the carrier waves corresponding to the submodules are arranged according to a phase shift mode, and the pulse signal corresponding to each submodule is obtained by comparing the modulated wave signal with the carrier wave signal, wherein when the modulated wave signal is larger than the carrier wave signal, a high-level signal is output, and when the modulated wave signal is smaller than the carrier wave signal, a low-level signal is output.
If the number of sub-modules per leg of the MMC is N (N is usually an even number) Then carrier u corresponding to sub-module in upper bridge arm car,pl The phase difference between the two sub-modules is 360 degrees/N, and the carrier wave u corresponding to the sub-module in the lower bridge arm is the carrier wave u car,nl The phase difference between the first sub-module and the second sub-module is 360 degrees/2N, wherein l=1, 2. Three-phase upper bridge arm modulation wave u ref,ap 、u ref,bp And u ref,cp Phase difference 120 DEG, three-phase lower bridge arm modulation wave u ref,an 、u ref,bn And u ref,cn The phase difference is 120 degrees, and the modulation wave u corresponding to the upper bridge arm and the lower bridge arm in each phase ref,jp And u ref,jn 180 ° (j=a, b, c).
The application does not take the generated pulse directly as a sub-module driving pulse, but the pulse is used as a control signal of the driving pulse. The pulse expression obtained by comparing the modulated wave with the carrier wave is as follows:
further, in the embodiment of the present application, when the pulse signal changes from high level to low level, the falling edge capturing signal outputs a high level of one clock cycle, and at other moments, the falling edge capturing signal outputs a low level all the time, which is expressed as:
wherein u is neg,jkl0 Representing the falling edge acquisition signal, u jkl0 The pulse signal obtained by comparing the modulated wave with the carrier wave is represented by j, k represents the phase unit of the MMC, k represents the upper bridge arm and the lower bridge arm, l represents the serial numbers of the submodules, and T represents the clock period of the digital circuit.
Further, in the embodiment of the present application, the sub-modules are grouped, specifically, the upper bridge arm and the lower bridge arm are divided into a predetermined number of sub-module groups with order, and the driving pulses of six sub-modules in one sub-module group are expressed as follows in order:
wherein u is akl Drive signal representing the first sub-module of a-phase k bridge arm, u bkl Drive signal representing the l-th sub-module of the b-phase k bridge arm, u ckl Drive signal representing the first submodule of the c-phase k-arm, u ak(N/2+l) Drive signal representing N/2+l sub-module of a-phase k bridge arm, u bk(N/2+l) Drive signal representing N/2+l sub-module of b-phase k-arm, u ck(N/2+l) N/2+l sub-module representing c-phase k bridge arm, u neg,akl0 A falling edge capturing signal of pulse signal obtained by comparing modulated wave of first submodule of a phase k bridge arm with carrier wave, u neg,bkl0 A falling edge capturing signal of a pulse signal obtained by comparing a modulated wave of an l sub-module of a b-phase k bridge arm with a carrier wave, u neg,ckl0 A falling edge capturing signal representing a pulse signal obtained by comparing a modulated wave of an l sub-module of a c-phase k bridge arm with a carrier wave, u neg,ak(N/2+l)0 Representing the falling edge capturing signal of the pulse signal obtained by comparing the modulated wave of the N/2+l th submodule of the a-phase k bridge arm with the carrier wave,u neg,bk(N/2+l)0 capturing a signal on the falling edge of a pulse signal obtained by comparing a modulated wave of a N/2+l th submodule of a b-phase k bridge arm with a carrier wave, and u neg,ck(N/2+l)0 The method comprises the steps of representing a falling edge capturing signal of a pulse signal obtained by comparing a modulated wave of a c-phase k bridge arm N/2+l sub-module with a carrier wave, wherein N represents the number of the sub-modules, and T represents a clock period of a digital circuit.
The upper bridge arm and the lower bridge arm can be divided into N/2 sub-module groups with sequence. When n=4, all the sub-modules of the upper bridge arm can be divided into 2 sub-module groups:
upper bridge arm 1 st sub-module group:
SM ap1 →SM bp3 →SM cp1 →SM ap3 →SM bp1 →SM cp3
upper bridge arm 2 nd sub-module group:
SM ap2 →SM bp4 →SM cp2 →SM ap4 →SM bp2 →SM cp4
further, in the embodiment of the present application, the obtained sub-module driving pulse has the following characteristics:
the driving pulse falling edge of the first sub-module of the a-phase upper bridge arm is at the same time as the driving pulse rising edge of the N/2+l sub-module of the b-phase upper bridge arm, the driving pulse falling edge of the N/2+l sub-module of the b-phase upper bridge arm is at the same time as the driving pulse rising edge of the first sub-module of the c-phase upper bridge arm, the driving pulse falling edge of the first sub-module of the c-phase upper bridge arm is at the same time as the driving pulse rising edge of the N/2+l sub-module of the a-phase upper bridge arm, the driving pulse falling edge of the N/2+l sub-module of the a-phase upper bridge arm is at the same time as the driving pulse rising edge of the first sub-module of the b-phase upper bridge arm, and the driving pulse falling edge of the first sub-module of the b-phase upper bridge arm is at the same time as the driving pulse rising edge of the N/2+l sub-module of the c-phase upper bridge arm.
This is true for the N/2 sub-module groups of the upper leg, and for the lower leg. Such a group of sub-modules always has three sub-modules in the put-in state.
The sum of the numbers of the submodules of the three upper bridge arms in the input state and the sum of the numbers of the submodules of the three lower bridge arms in the input state are 3N/2, namely:
fig. 2 is another flowchart of a pulse-forward carrier phase-shifting sinusoidal pulse width modulation method for eliminating an MMC common-mode voltage according to an embodiment of the application.
As shown in fig. 2, the pulse-forward carrier phase-shifting sinusoidal pulse width modulation method for eliminating the common mode voltage of the MMC includes comparing a sinusoidal wave with a carrier wave to obtain a pulse signal corresponding to each sub-module; capturing the falling edge of the driving pulse of each sub-module; and obtaining the new driving pulse falling edge of each sub-module in a grouping mode according to the falling edge.
Fig. 4 is a schematic diagram of a carrier wave and a modulated wave of a pulse-compliant carrier phase-shifting sinusoidal pulse width modulation according to an embodiment of the present application.
As shown in fig. 4, the pulse-forward carrier phase-shifting sinusoidal pulse width modulation method for eliminating the common mode voltage of the MMC is based on carrier phase-shifting sinusoidal pulse width modulation, and generates driving pulses of each sub-module in a manner of comparing isosceles triangle carriers with sinusoidal modulation waves, for example, three-phase MMC with the number N of sub-modules of each bridge arm being 4, carriers corresponding to the sub-modules are arranged in a phase-shifting manner, so that carrier u corresponding to the sub-module of the upper bridge arm car,p1 、u car,p2 、u car,p3 、u car,p4 The phase difference between the sub-modules is 90 degrees, and the carrier wave u corresponding to the sub-modules in the lower bridge arm car,n1 、u car,n2 、u car,n3 、u car,n4 The phase difference between the first sub-module and the second sub-module is 90 degrees, and the phase difference between the first sub-module in the upper bridge arm and the first sub-module in the lower bridge arm is 45 degrees, wherein l=1, 2,3 and 4. Three-phase upper bridge arm modulation wave u ref,ap 、u ref,bp And u ref,cp Phase difference 120 DEG, three-phase lower bridge arm modulation wave u ref,an 、u ref,bn And u ref,cn The phase difference is 120 degrees, and the modulation wave u corresponding to the upper bridge arm and the lower bridge arm in each phase ref,jp And u ref,jn 180 ° (j=a, b, c).
Fig. 5 is a timing chart illustrating a process of forming a driving pulse of one of the sub-modules in the pulse-sequential carrier-phase-shifting sinusoidal pulse width modulation method for eliminating the common mode voltage of the MMC according to an embodiment of the present application.
As shown in FIG. 5, the pulse-forward carrier phase-shifting sinusoidal pulse width modulation method for eliminating MMC common mode voltage bk(N/2+l) The generation process of the sub-module is as follows, u apl0 For modulating wave u ref,ap And carrier u car,pl Comparing the obtained pulses, u bp(N/2+l)0 For modulating wave u ref,bp And carrier u car,p(N/2+l) Comparing the obtained pulses, u neg,apl0 To capture u apl0 Pulse obtained by falling edge, u neg,bp(N/2+l)0 To capture u bp(N/2+l)0 The resulting pulse is a falling edge.
Fig. 6 is a schematic diagram of driving pulses of all sub-modules of a sub-module group of a pulse-sequential carrier phase-shifting sinusoidal pulse width modulation method for eliminating common mode voltage of MMC according to an embodiment of the present application.
As shown in fig. 6, the driving pulse of the first submodule group of the pulse-forward carrier phase-shifting sinusoidal pulse width modulation method for eliminating the common-mode voltage of the MMC is as follows, and it can be seen that the driving pulse falling edge of the first submodule of the a-phase upper bridge arm is at the same time as the driving pulse rising edge of the N/2+l th submodule of the b-phase upper bridge arm, the driving pulse falling edge of the N/2+l th submodule of the b-phase upper bridge arm is at the same time as the driving pulse rising edge of the first submodule of the c-phase upper bridge arm, the driving pulse falling edge of the first submodule of the c-phase upper bridge arm is at the same time as the driving pulse rising edge of the N/2+l th submodule of the a-phase upper bridge arm, the driving pulse falling edge of the N/2+l th submodule of the a-phase upper bridge arm is at the same time as the driving pulse rising edge of the first submodule of the b-phase upper bridge arm, and the driving pulse falling edge of the N/2+l th submodule of the c-phase upper bridge arm is at the same time as the driving pulse rising edge of the first submodule of the a-phase upper bridge arm. This is true for the N/2 sub-module groups of the upper leg, and for the lower leg. Three sub-modules are always in the input state in the sub-module sequential group.
Fig. 7 is a schematic diagram of a common mode voltage implemented by the MMC with the number of bridge arm submodules of 4 according to carrier phase-shifting sinusoidal pulse width modulation under the working conditions of bus voltage 800V, load current effective value 11.3A and modulation ratio 0.8 in the embodiment of the present application.
Fig. 8 is a schematic diagram of a common mode voltage implemented by the MMC with 4 bridge arm submodules according to the present application under the working conditions of a bus voltage of 800V, a load current effective value of 11.3A, and a modulation ratio of 0.8.
As shown in fig. 7 and fig. 8, both the two diagrams are schematic diagrams of common mode voltage of the MMC with the number of bridge arm submodules being 4 under the working conditions of bus voltage 800V and effective value of load current being 11.3A, the former is realized by carrier phase shifting sinusoidal pulse width modulation of a modulation method commonly used by the MMC, and the latter is realized by using the modulation method of the application. The modulation ratio is 0.8, and the load is a resistive load. When the modulation method is used, the common mode voltage of the MMC is close to zero, so that the leakage current of the MMC is reduced, the common mode noise is reduced, the performance of the MMC is improved, and the technical problems that the leakage current and common mode interference can be generated by stray capacitance in the existing MMC and the motor bearing, the communication system and the like are damaged are effectively solved.
Fig. 9 is a schematic structural diagram of a pulse-forward carrier phase-shifting sinusoidal pulse width modulation device for eliminating common mode voltage of MMC according to a second embodiment of the present application.
As shown in fig. 9, the pulse-sequential carrier phase-shifting sinusoidal pulse width modulation device for eliminating the common mode voltage of the MMC comprises a comparison module, a capturing module and a generating module, wherein,
a comparison module 10, configured to compare the modulated wave with a carrier wave to obtain a pulse signal;
a capturing module 20 for capturing a pulse falling edge of the pulse signal;
a generating module 30 for grouping the sub-modules and generating the driving pulse of the switching tube by the falling edge of the captured pulse.
The pulse-forward carrier phase-shifting sinusoidal pulse width modulation device for eliminating the common mode voltage of the MMC comprises a comparison module, a capturing module and a generating module, wherein the comparison module is used for comparing a modulation wave with a carrier wave to obtain a pulse signal; the capturing module is used for capturing the pulse falling edge of the pulse signal; and the generation module is used for grouping the sub-modules and generating driving pulses of the switching tube through the falling edges of the captured pulses. Therefore, the technical problems that the leakage current and common-mode interference are generated by the high-frequency common-mode voltage through the stray capacitance, the motor bearing, the communication system and the like in the existing MMC can be solved, the common-mode voltage high-frequency jump is eliminated in real time by optimizing the switching sequence of the submodule, and the purposes of effectively reducing the leakage current and the common-mode noise of the MMC and improving the working performance of the MMC are achieved.
In order to implement the above embodiment, the present application further proposes a non-transitory computer readable storage medium having stored thereon a computer program, which when executed by a processor implements the pulse-forward carrier phase-shifting sinusoidal pulse width modulation method for eliminating the common mode voltage of the MMC of the above embodiment.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and additional implementations are included within the scope of the preferred embodiment of the present application in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order from that shown or discussed, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the embodiments of the present application.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable instructions for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above-described embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
Those of ordinary skill in the art will appreciate that all or a portion of the steps carried out in the method of the above-described embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, and where the program, when executed, includes one or a combination of the steps of the method embodiments.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing module, or each unit may exist alone physically, or two or more units may be integrated in one module. The integrated modules may be implemented in hardware or in software functional modules. The integrated modules may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product.
The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, or the like. While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.

Claims (4)

1. The pulse forward carrier phase-shifting sinusoidal pulse width modulation method for eliminating MMC common mode voltage is characterized by comprising the following steps:
step S1: comparing the modulated wave with a carrier wave to obtain a pulse signal;
step S2: capturing a pulse falling edge of the pulse signal;
step S3: grouping the sub-modules and generating driving pulses of the switching tube through the captured pulse falling edges;
when the pulse signal is changed from high level to low level, the falling edge capturing signal outputs high level of one clock period, and at other moments, the falling edge capturing signal output is always low level, which is expressed as:
j＝a,b,c k＝p,n l＝1,2,...,N
wherein u is neg,jkl0 Representing the falling edge acquisition signal, u jkl0 The pulse signal obtained by comparing the modulated wave with the carrier wave is represented by j, k represents the phase unit of the MMC, k represents the upper bridge arm and the lower bridge arm, l represents the serial numbers of the submodules, and T represents the clock period of the digital circuit;
the sub-modules are grouped, specifically, an upper bridge arm and a lower bridge arm are divided into a preset number of sub-module groups with sequences, and driving pulses of six sub-modules in one sub-module group are expressed as follows in sequence:
wherein u is akl Drive signal representing the first sub-module of a-phase k bridge arm, u bkl Drive signal representing the l-th sub-module of the b-phase k bridge arm, u ckl Drive signal representing the first submodule of the c-phase k-arm, u ak(N/2+l) Drive signal representing N/2+l sub-module of a-phase k bridge arm, u bk(N/2+l) Drive signal representing N/2+l sub-module of b-phase k-arm, u ck(N/2+l) N/2+l sub-module representing c-phase k bridge arm, u neg,akl0 A falling edge capturing signal of pulse signal obtained by comparing modulated wave of first submodule of a phase k bridge arm with carrier wave, u neg,bkl0 A falling edge capturing signal of a pulse signal obtained by comparing a modulated wave of an l sub-module of a b-phase k bridge arm with a carrier wave, u neg,ckl0 A falling edge capturing signal representing a pulse signal obtained by comparing a modulated wave of an l sub-module of a c-phase k bridge arm with a carrier wave, u neg,ak(N/2+l)0 A falling edge capturing signal of pulse signal obtained by comparing a modulated wave of N/2+l th submodule of a phase k bridge arm with carrier wave, u neg,bk(N/2+l)0 Capturing a signal on the falling edge of a pulse signal obtained by comparing a modulated wave of a N/2+l th submodule of a b-phase k bridge arm with a carrier wave, and u neg,ck(N/2+l)0 The method comprises the steps that a falling edge capturing signal of a pulse signal obtained by comparing a modulated wave of a c-phase k bridge arm N/2+l th submodule with a carrier wave is represented, N represents the number of the submodules, and T represents the clock period of a digital circuit;
the resulting submodule drive pulse has the following characteristics:
the driving pulse falling edge of the first sub-module of the a-phase upper bridge arm is at the same time as the driving pulse rising edge of the N/2+l sub-module of the b-phase upper bridge arm, the driving pulse falling edge of the N/2+l sub-module of the b-phase upper bridge arm is at the same time as the driving pulse rising edge of the first sub-module of the c-phase upper bridge arm, the driving pulse falling edge of the first sub-module of the c-phase upper bridge arm is at the same time as the driving pulse rising edge of the N/2+l sub-module of the a-phase upper bridge arm, the driving pulse falling edge of the N/2+l sub-module of the a-phase upper bridge arm is at the same time as the driving pulse rising edge of the first sub-module of the b-phase upper bridge arm, and the driving pulse falling edge of the first sub-module of the b-phase upper bridge arm is at the same time as the driving pulse rising edge of the N/2+l sub-module of the c-phase upper bridge arm.
2. The method of claim 1, wherein the comparing the modulated wave with the carrier wave to obtain the pulse signal is based on pulse width modulation, specifically, isosceles triangle carrier waves are adopted, the carrier waves corresponding to the sub-modules are arranged according to phase shift, and the pulse signal corresponding to each sub-module is obtained by comparing the modulated wave signal with the carrier wave signal, wherein when the modulated wave signal is larger than the carrier wave signal, a high level signal is output, and when the modulated wave signal is smaller than the carrier wave signal, a low level signal is output.
3. The pulse-forward carrier phase-shifting sine pulse width modulation device for eliminating MMC common mode voltage is characterized by comprising a comparison module, a capturing module and a generating module, wherein,
the comparison module is used for comparing the modulated wave with the carrier wave to obtain a pulse signal;
the capturing module is used for capturing the pulse falling edge of the pulse signal;
the generation module is used for grouping the sub-modules and generating driving pulses of the switching tube through the captured pulse falling edges;
when the pulse signal is changed from high level to low level, the falling edge capturing signal outputs high level of one clock period, and at other moments, the falling edge capturing signal output is always low level, which is expressed as:
j＝a,b,c k＝p,n l＝1,2,...,N
wherein u is neg,jkl0 Representing the falling edge acquisition signal, u jkl0 The pulse signal obtained by comparing the modulated wave with the carrier wave is represented by j, k represents the phase unit of the MMC, k represents the upper bridge arm and the lower bridge arm, l represents the serial numbers of the submodules, and T represents the clock period of the digital circuit;
the sub-modules are grouped, specifically, an upper bridge arm and a lower bridge arm are divided into a preset number of sub-module groups with sequences, and driving pulses of six sub-modules in one sub-module group are expressed as follows in sequence:
wherein u is akl Represents a phase a k bridge armDrive signals of sub-modules, u bkl Drive signal representing the l-th sub-module of the b-phase k bridge arm, u ckl Drive signal representing the first submodule of the c-phase k-arm, u ak(N/2+l) Drive signal representing N/2+l sub-module of a-phase k bridge arm, u bk(N/2+l) Drive signal representing N/2+l sub-module of b-phase k-arm, u ck(N/2+l) N/2+l sub-module representing c-phase k bridge arm, u neg,akl0 A falling edge capturing signal of pulse signal obtained by comparing modulated wave of first submodule of a phase k bridge arm with carrier wave, u neg,bkl0 A falling edge capturing signal of a pulse signal obtained by comparing a modulated wave of an l sub-module of a b-phase k bridge arm with a carrier wave, u neg,ckl0 A falling edge capturing signal representing a pulse signal obtained by comparing a modulated wave of an l sub-module of a c-phase k bridge arm with a carrier wave, u neg,ak(N/2+l)0 A falling edge capturing signal of pulse signal obtained by comparing a modulated wave of N/2+l th submodule of a phase k bridge arm with carrier wave, u neg,bk(N/2+l)0 Capturing a signal on the falling edge of a pulse signal obtained by comparing a modulated wave of a N/2+l th submodule of a b-phase k bridge arm with a carrier wave, and u neg,ck(N/2+l)0 The method comprises the steps that a falling edge capturing signal of a pulse signal obtained by comparing a modulated wave of a c-phase k bridge arm N/2+l th submodule with a carrier wave is represented, N represents the number of the submodules, and T represents the clock period of a digital circuit;
the resulting submodule drive pulse has the following characteristics:
the driving pulse falling edge of the first sub-module of the a-phase upper bridge arm is at the same time as the driving pulse rising edge of the N/2+l sub-module of the b-phase upper bridge arm, the driving pulse falling edge of the N/2+l sub-module of the b-phase upper bridge arm is at the same time as the driving pulse rising edge of the first sub-module of the c-phase upper bridge arm, the driving pulse falling edge of the first sub-module of the c-phase upper bridge arm is at the same time as the driving pulse rising edge of the N/2+l sub-module of the a-phase upper bridge arm, the driving pulse falling edge of the N/2+l sub-module of the a-phase upper bridge arm is at the same time as the driving pulse rising edge of the first sub-module of the b-phase upper bridge arm, and the driving pulse falling edge of the first sub-module of the b-phase upper bridge arm is at the same time as the driving pulse rising edge of the N/2+l sub-module of the c-phase upper bridge arm.
4. A non-transitory computer readable storage medium, having stored thereon a computer program, which when executed by a processor, implements the method according to any of claims 1-2.
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