CN113794369B - Three-phase PFC and PWM modulation method based on BUCK circuit - Google Patents
Three-phase PFC and PWM modulation method based on BUCK circuit Download PDFInfo
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- CN113794369B CN113794369B CN202111091133.0A CN202111091133A CN113794369B CN 113794369 B CN113794369 B CN 113794369B CN 202111091133 A CN202111091133 A CN 202111091133A CN 113794369 B CN113794369 B CN 113794369B
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- 238000004590 computer program Methods 0.000 claims description 6
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- 238000012986 modification Methods 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
- H02M1/4233—Arrangements for improving power factor of AC input using a bridge converter comprising active switches
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Power Engineering (AREA)
- Rectifiers (AREA)
Abstract
The invention discloses a BUCK debugging circuit for three-phase PFC and PWM technology, comprising: dividing Uan, ubn and Ucn into two paths; the first path respectively passes through three comparators to obtain high-frequency signals; respectively taking one inverse logic signal from the high-frequency signals to obtain three inverse logic high-frequency signals, and finally obtaining A1-A6 modulation signals; the second path is respectively compared in pairs by three comparators in sequence to obtain maximum value signals, and then the maximum value signals are respectively reversely logically obtained to obtain B1-B6; then respectively performing AND logic on B1 and B5, B2 and B6, B3 and B1, B2 and B4, B3 and B5 and B4 and B6 to obtain signals C1-C6, and then performing OR operation on C1 and C2, C3 and C4, and C5 and C6 to obtain D1-D3 respectively; performing OR operation on the modulation signals A1-A6 and performing non-operation to obtain a high-frequency modulation signal E; e and D1-D3 are respectively subjected to AND operation to obtain modulation signals F1-F3; the modulation signals A1, A2 and F1, A3, A4 and F2, and A5, A6 and F3 are respectively subjected to OR operation to obtain 6 finally required modulation logic signals.
Description
Technical Field
The invention relates to the technical field of Power Factor Correction (PFC) and Pulse Width Modulation (PWM), in particular to a three-phase PFC and PWM modulation circuit based on a BUCK circuit and a modulation method.
Background
Along with the wide application of power electronic devices, particularly the use of a plurality of low-power-factor power electronics, a large number of harmonic waves are generated in a power grid, and certain influences are caused on the power supply quality and the power grid loss.
At present, a single PFC technology is mature, and a three-phase PFC technology is becoming a significant research topic in the power supply field because of its technical difficulty. Among the three-phase PFC circuits, the three-phase PFC circuit (shown in figure 1) based on the BUCK circuit has the advantages of no need of a soft start circuit, short circuit resistance, small volume and the like, and becomes a preferred circuit in the power supply field of the PFC module, but due to the fact that the number of switching tubes of the BUCK PFC module is large, the loss is large, the efficiency is low, the defects that a primary circuit is needed to be added at a later stage to realize stable voltage output, PWM modulation is complex and the like are overcome, and mature products in the market are not many.
In the technical difficulty of the three-phase BUCK PFC, the PWM modulation mode is a key technical point which needs to be solved, but due to the fact that universities and companies studied in the field of the three-phase BUCK PFC are not many, the number of journals, papers and patents which can be referred to is small, so that the PWM modulation mode is not mature and a comparison circuit or method can be referred to.
Disclosure of Invention
The invention provides a three-phase PFC and PWM modulation method based on a BUCK circuit, which is based on the existing BUCK circuit and Power Factor Correction (PFC) to carry out PWM modulation, and solves the problem that PWM modulation is difficult to be applied to the three-phase BUCK PFC in the prior art.
To achieve the above and other related objects, the present invention provides a three-phase PFC and PWM modulation method based on a BUCK circuit for modulating sinusoidal modulation signals uon, ubn and Ucn into PWM waveforms, including:
Dividing Uan, ubn and Ucn into two paths;
The first path Uan, ubn and Ucn are respectively compared with a set carrier signal through three comparators, if the first path Uan, ubn and Ucn are larger than the set carrier signal, the first path Uan, ubn and Ucn are logic 1, otherwise the first path Uan, ubn are logic 0, and then high frequency Uan, high frequency Ubn and high frequency Ucn are obtained; respectively taking one inverse logic signal from the high frequency Uan, the high frequency Ubn and the high frequency Ucn to obtain an inverse logic high frequency Uan, an inverse logic high frequency Ubn and an inverse logic high frequency Ucn; performing AND logic on the high frequency Uan and the inverse logic high frequency Ubn to obtain an A1 modulation signal; performing AND logic on the inverse logic high frequency Uan and the high frequency Ubn to obtain an A2 modulation signal; performing AND logic on the high frequency Ubn and the inverse logic high frequency Ucn to obtain an A3 modulation signal; performing AND logic on the inverse logic high frequency Ubn and the high frequency Ucn to obtain an A4 modulation signal; performing AND logic on the high-frequency Ucn and the inverse logic high frequency Uan to obtain an A5 modulation signal; performing AND logic on the inverse logic high frequency Ucn and the high frequency Uan to obtain an A6 modulation signal;
The second way Uan, ubn and Ucn are compared in sequence two by two through three comparators at first, if the former is big, logic 1 is adopted, otherwise logic 0 is adopted, three comparators respectively obtain three maximum logic signals B1, B2 and B3, and then B1, B2 and B3 are respectively subjected to inverse logic to obtain B4, B5 and B6; then respectively performing AND logic on B1 and B5, B2 and B6, B3 and B1, B2 and B4, B3 and B5 and B4 and B6 to obtain signals C1, C2, C3, C4, C5 and C6, and then performing OR operation on C1 and C2, C3 and C4, C5 and C6 to obtain D1, D2 and D3 respectively;
the modulation signals A1, A2, A3, A4, A5 and A6 are subjected to OR operation and then are subjected to NOT operation, so that a high-frequency modulation signal E is obtained; e, D1, D2 and D3 are respectively subjected to AND operation to obtain modulation signals F1, F2 and F3;
The modulation signals A1, A2 and F1, A3, A4 and F2, A5, A6 and F3 are ored, respectively, to obtain the final required modulation logic Gap, gan, gbp, gbn, gcp, gcn.
Preferably, uan, ubn and Ucn are SPWM signal inputs or SVPWM signal inputs.
Preferably, the modulation method is implemented by a digital controller.
Preferably, the modulation method is implemented by digital circuits or a hybrid of digital control and digital circuits.
The invention also provides an electronic device comprising a processor and a memory, the memory having stored thereon a computer program which, when executed by the processor, implements a method according to any of the preceding claims.
Based on the same inventive idea, the present invention also provides a readable storage medium having stored therein a computer program which, when executed by a processor, implements the method of any of the above.
Based on the same inventive idea, the invention also provides an inverter comprising: the system comprises an input unit, an output unit, a power grid voltage detection unit, an alternating current voltage control unit and a PWM modulation unit, wherein the input unit, the output unit, the power grid voltage detection unit and the alternating current voltage control unit are all connected with the PWM modulation unit, and the power grid voltage detection unit is connected with the alternating current voltage control unit; the input unit is used for transmitting the direct-current voltage to the PWM modulation unit; the power grid voltage detection unit is used for transmitting the detected power grid voltage amplitude and phase to the alternating current voltage control unit; the alternating voltage control unit is used for calculating and outputting alternating voltage amplitude and phase according to a preset grid-connected current control instruction, a current power grid current value, the power grid voltage amplitude and phase, wherein the grid-connected current control instruction comprises a target current value during grid connection;
the power grid voltage detection unit is further used for triggering the PWM modulation unit to modulate the direct current voltage into the first alternating current voltage output by the inverter through a two-level PWM modulation mode according to the alternating current voltage amplitude and the phase when the power grid voltage amplitude is lower than a low voltage crossing threshold value; or triggering the PWM modulation unit to modulate the direct current voltage into a second alternating current voltage output by the inverter through a three-level PWM modulation method according to the alternating current voltage amplitude and the phase when the power grid voltage amplitude is higher than or equal to a low voltage crossing threshold value; the output unit outputs the first alternating voltage or the second alternating voltage to a power grid side;
The three-level PWM modulation method is any one of the methods described above.
In summary, the invention provides a three-phase PFC and PWM modulation method based on a BUCK circuit, which is based on the existing BUCK circuit and Power Factor Correction (PFC) to carry out PWM modulation, and solves the problem that PWM modulation is difficult to be applied to the three-phase BUCK PFC in the prior art.
Drawings
FIG. 1 is a schematic diagram of a three-phase BUCK PFC circuit in the prior art;
fig. 2 is a schematic circuit diagram of a three-phase PFC and PWM modulation method based on a BUCK circuit according to an embodiment of the present invention;
FIG. 3 is a logic diagram corresponding to A1 in Uan, ubn, ucn of a three-phase PFC and PWM modulation method based on BUCK circuit according to an embodiment of the present invention;
FIG. 4 is a logic diagram corresponding to B1 and C1 in Uan, ubn, ucn of a three-phase PFC and PWM modulation method based on a BUCK circuit according to an embodiment of the present invention;
FIG. 5 is a logic diagram corresponding to E1 and F1 in Uan, ubn, ucn of a three-phase PFC and PWM modulation method based on a BUCK circuit according to an embodiment of the present invention;
FIG. 6 is a logic diagram of A1, F1 and Gap in a three-phase PFC and PWM modulation method based on BUCK circuit according to an embodiment of the present invention.
Detailed Description
The three-phase PFC and PWM modulation method based on the BUCK circuit according to the present invention is described in further detail below with reference to fig. 1-6 and the detailed description. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for the purpose of facilitating and clearly aiding in the description of embodiments of the invention. For a better understanding of the invention with objects, features and advantages, refer to the drawings. It should be understood that the structures, proportions, sizes, etc. shown in the drawings are for illustration purposes only and should not be construed as limiting the invention to the extent that any modifications, changes in the proportions, or adjustments of the sizes of structures, proportions, or otherwise, used in the practice of the invention, are included in the spirit and scope of the invention which is otherwise, without departing from the spirit or essential characteristics thereof.
Referring to fig. 2, the present aspect provides, in an embodiment, a three-phase PFC and PWM modulation method based on a BUCK circuit for modulating sinusoidal modulation signals uon, ubn and Ucn into PWM waveforms, including:
Dividing Uan, ubn and Ucn into two paths;
the first path Uan, ubn and Ucn are respectively compared with a set carrier signal through three comparators, if the first path Uan, ubn and Ucn are larger than the set carrier signal, the first path Uan, ubn and Ucn are logic 1, otherwise the first path Uan, ubn are logic 0, and then high frequency Uan, high frequency Ubn and high frequency Ucn are obtained; respectively taking one inverse logic signal from the high frequency Uan, the high frequency Ubn and the high frequency Ucn to obtain an inverse logic high frequency Uan, an inverse logic high frequency Ubn and an inverse logic high frequency Ucn; performing AND logic on the high frequency Uan and the inverse logic high frequency Ubn to obtain an A1 modulation signal; performing AND logic on the inverse logic high frequency Uan and the high frequency Ubn to obtain an A2 modulation signal; performing AND logic on the high frequency Ubn and the inverse logic high frequency Ucn to obtain an A3 modulation signal; performing AND logic on the inverse logic high frequency Ubn and the high frequency Ucn to obtain an A4 modulation signal; performing AND logic on the high-frequency Ucn and the inverse logic high frequency Uan to obtain an A5 modulation signal; performing AND logic on the inverse logic high frequency Ucn and the high frequency Uan to obtain an A6 modulation signal, wherein reference waveforms of A1-A6 are shown in figure 3; the second way Uan, ubn and Ucn are compared in sequence two by two through three comparators at first, if the former is big, logic 1 is adopted, otherwise logic 0 is adopted, three comparators respectively obtain three maximum logic signals B1, B2 and B3, and then B1, B2 and B3 are respectively subjected to inverse logic to obtain B4, B5 and B6; then respectively performing AND logic on B1 and B5, B2 and B6, B3 and B1, B2 and B4, B3 and B5 and B4 and B6 to obtain signals C1, C2, C3, C4, C5 and C6, and then performing OR operation on C1 and C2, C3 and C4, C5 and C6 to obtain D1, D2 and D3 respectively; the logical 1 s of D1-D3 correspond to periods of 30 ° to 90 ° and 180 ° to 270 ° of the sinusoidal modulation signal Uan, ubn, ucn, respectively, with reference to the waveforms shown in fig. 4. The modulation signals A1, A2, A3, A4, A5 and A6 are subjected to OR operation and then are subjected to NOT operation, so that a high-frequency modulation signal E is obtained; e, D1, D2 and D3 are respectively subjected to AND operation to obtain modulation signals F1, F2 and F3; the modulation signals A1, A2 and F1, A3, A4 and F2, A5, A6 and F3 are ored, respectively, to obtain the final required modulation logic Gap, gan, gbp, gbn, gcp, gcn. The signals are amplified by the driving circuit and then respectively driven Sap, san, sbp, sbn, scp, scn, the reference waveforms of A1, F1 and Sap are shown in figure 6, the Gap is 180 degrees different from the Sap, and the Gbp, gbn, gcp, gcn waveforms are similar to Gap and Gap, and the phases follow Ubn and Ucn.
In an embodiment, the scheme includes comparator logic COMP 1-COMP 6, NOT gate logic NOT 1-NOT 6, AND gate logic AND1-AND15, OR gate logic OR 1-OR 13, AND nand gate logic NOR1, uan, ubn, ucn are reference modulation voltages, AND a sinusoidal signal is output from a digital controller control loop, AND may be an SPWM signal input OR an SVPWM signal input. Gap, gan, gbp, gbn, gcp, gcn is to debug and output PWM waveforms, and drive Sap, san, sbp, sbn, scp, scn of fig. 1 respectively, so as to achieve the purposes of input currents Ia, ib, ic with sine waveforms, advanced phases Ua, ub, uc by a certain angle, and input power factor correction.
In this embodiment, the modulation method is optimally implemented in a digital controller, and may also be implemented in a digital circuit or a hybrid of digital control and digital circuits. In order to facilitate understanding of the logic flow of the modulation method, the modulation method is drawn in a digital circuit form, and a logic diagram of the specific implementation is shown in fig. 2.
The invention also provides an electronic device comprising a processor and a memory, the memory having stored thereon a computer program which, when executed by the processor, implements a method according to any of the preceding claims.
Based on the same inventive idea, the present invention also provides a readable storage medium having stored therein a computer program which, when executed by a processor, implements the method of any of the above.
Based on the same inventive idea, the invention also provides an inverter comprising: the system comprises an input unit, an output unit, a power grid voltage detection unit, an alternating current voltage control unit and a PWM modulation unit, wherein the input unit, the output unit, the power grid voltage detection unit and the alternating current voltage control unit are all connected with the PWM modulation unit, and the power grid voltage detection unit is connected with the alternating current voltage control unit; the input unit is used for transmitting the direct-current voltage to the PWM modulation unit; the power grid voltage detection unit is used for transmitting the detected power grid voltage amplitude and phase to the alternating current voltage control unit; the alternating voltage control unit is used for calculating and outputting alternating voltage amplitude and phase according to a preset grid-connected current control instruction, a current power grid current value, the power grid voltage amplitude and phase, wherein the grid-connected current control instruction comprises a target current value during grid connection; the power grid voltage detection unit is further used for triggering the PWM modulation unit to modulate the direct current voltage into the first alternating current voltage output by the inverter through a two-level PWM modulation mode according to the alternating current voltage amplitude and the phase when the power grid voltage amplitude is lower than a low voltage crossing threshold value; or triggering the PWM modulation unit to modulate the direct current voltage into a second alternating current voltage output by the inverter through a three-level PWM modulation method according to the alternating current voltage amplitude and the phase when the power grid voltage amplitude is higher than or equal to a low voltage crossing threshold value; the output unit outputs the first alternating voltage or the second alternating voltage to a power grid side; the three-level PWM modulation method is any one of the methods described above. The embodiment of the invention provides an inverter and a PWM modulation method, which are used for solving the problems that the waveform distortion of the output voltage of the inverter is serious and reliable grid connection cannot be realized during low voltage ride through in the prior art.
The invention has the advantages of providing a three-phase PFC and PWM modulation method based on a BUCK circuit, wherein the modulation method is based on the existing BUCK circuit and Power Factor Correction (PFC) to carry out PWM modulation, and the problem that the PWM modulation is difficult to be applied to the three-phase BUCK PFC in the prior art is solved.
While the present invention has been described in detail through the foregoing description of the preferred embodiment, it should be understood that the foregoing description is not to be considered as limiting the invention. Many modifications and substitutions of the present invention will become apparent to those of ordinary skill in the art upon reading the foregoing. Accordingly, the scope of the invention should be limited only by the attached claims.
Claims (7)
1. A three-phase PFC and PWM modulation method based on a BUCK circuit for modulating sinusoidal modulation signals ua, ubn and Ucn into PWM waveforms, comprising:
Dividing Uan, ubn and Ucn into two paths;
The first path Uan, ubn and Ucn are respectively compared with a set carrier signal through three comparators, if the first path Uan, ubn and Ucn are larger than the set carrier signal, the first path Uan, ubn and Ucn are logic 1, otherwise the first path Uan, ubn are logic 0, and then high frequency Uan, high frequency Ubn and high frequency Ucn are obtained; respectively taking one inverse logic signal from the high frequency Uan, the high frequency Ubn and the high frequency Ucn to obtain an inverse logic high frequency Uan, an inverse logic high frequency Ubn and an inverse logic high frequency Ucn; performing AND logic on the high frequency Uan and the inverse logic high frequency Ubn to obtain an A1 modulation signal; performing AND logic on the inverse logic high frequency Uan and the high frequency Ubn to obtain an A2 modulation signal; performing AND logic on the high frequency Ubn and the inverse logic high frequency Ucn to obtain an A3 modulation signal; performing AND logic on the inverse logic high frequency Ubn and the high frequency Ucn to obtain an A4 modulation signal; performing AND logic on the high-frequency Ucn and the inverse logic high frequency Uan to obtain an A5 modulation signal; performing AND logic on the inverse logic high frequency Ucn and the high frequency Uan to obtain an A6 modulation signal;
The second way Uan, ubn and Ucn are compared in sequence two by two through three comparators at first, if the former is big, logic 1 is adopted, otherwise logic 0 is adopted, three comparators respectively obtain three maximum logic signals B1, B2 and B3, and then B1, B2 and B3 are respectively subjected to inverse logic to obtain B4, B5 and B6; then respectively performing AND logic on B1 and B5, B2 and B6, B3 and B1, B2 and B4, B3 and B5 and B4 and B6 to obtain signals C1, C2, C3, C4, C5 and C6, and then performing OR operation on C1 and C2, C3 and C4, C5 and C6 to obtain D1, D2 and D3 respectively;
the modulation signals A1, A2, A3, A4, A5 and A6 are subjected to OR operation and then are subjected to NOT operation, so that a high-frequency modulation signal E is obtained; e, D1, D2 and D3 are respectively subjected to AND operation to obtain modulation signals F1, F2 and F3;
The modulation signals A1, A2 and F1, A3, A4 and F2, A5, A6 and F3 are ored, respectively, to obtain the final required modulation logic Gap, gan, gbp, gbn, gcp, gcn.
2. The BUCK circuit-based three-phase PFC and PWM modulation method according to claim 1, wherein uon, ubn, and Ucn are SPWM signal inputs or SVPWM signal inputs.
3. The BUCK circuit-based three-phase PFC and PWM modulation method according to claim 1, wherein the modulation method is implemented by a digital controller.
4. The BUCK circuit-based three-phase PFC and PWM modulation method according to claim 1, wherein the modulation method is implemented by digital circuitry or a hybrid of digital control and digital circuitry.
5. An electronic device comprising a processor and a memory, the memory having stored thereon a computer program which, when executed by the processor, implements the method of any of claims 1 to 4.
6. A readable storage medium, characterized in that the readable storage medium has stored therein a computer program which, when executed by a processor, implements the method of any one of claims 1 to 4.
7. An inverter, comprising: the system comprises an input unit, an output unit, a power grid voltage detection unit, an alternating current voltage control unit and a PWM modulation unit, wherein the input unit, the output unit, the power grid voltage detection unit and the alternating current voltage control unit are all connected with the PWM modulation unit, and the power grid voltage detection unit is connected with the alternating current voltage control unit; the input unit is used for transmitting the direct-current voltage to the PWM modulation unit; the power grid voltage detection unit is used for transmitting the detected power grid voltage amplitude and phase to the alternating current voltage control unit; the alternating voltage control unit is used for calculating and outputting alternating voltage amplitude and phase according to a preset grid-connected current control instruction, a current power grid current value, the power grid voltage amplitude and phase, wherein the grid-connected current control instruction comprises a target current value during grid connection;
the power grid voltage detection unit is further used for triggering the PWM modulation unit to modulate the direct current voltage into the first alternating current voltage output by the inverter through a two-level PWM modulation mode according to the alternating current voltage amplitude and the phase when the power grid voltage amplitude is lower than a low voltage crossing threshold value; or triggering the PWM modulation unit to modulate the direct current voltage into a second alternating current voltage output by the inverter through a three-level PWM modulation method according to the alternating current voltage amplitude and the phase when the power grid voltage amplitude is higher than or equal to a low voltage crossing threshold value; the output unit outputs the first alternating voltage or the second alternating voltage to a power grid side;
the three-level PWM modulation method is the method according to any one of claims 1 to 4.
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