CN113889410A - Chip for manufacturing transistor, manufacturing method of chip and transistor - Google Patents
Chip for manufacturing transistor, manufacturing method of chip and transistor Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 51
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- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 11
- 229910002804 graphite Inorganic materials 0.000 description 10
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- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
Abstract
The application discloses a manufacturing method of a chip for manufacturing a transistor, which comprises the following steps: forming a doped diamond layer on an upper surface of a substrate; annealing the substrate and the doped diamond layer to convert the doped diamond layer into a graphene layer; forming a buffer layer on the upper surface of the graphene layer; and forming a heterostructure and a device on the upper surface of the buffer layer to obtain the chip. According to the application, the doped diamond layer is formed on the upper surface of the substrate firstly, then annealing treatment is carried out, so that the doped diamond layer is converted into the graphene layer, the buffer layer, the heterostructure and the device are sequentially formed on the upper surface of the graphene layer through in-situ growth, graphene is a two-dimensional crystal material, on one hand, the graphene layer serves as a stress release layer between the substrate and the buffer layer, stress between the substrate and the buffer layer is relieved, on the other hand, the graphene layer serves as a nucleation layer, the dislocation density of the buffer layer is reduced, and the reliability of a chip is improved. In addition, the application also provides a chip and a transistor with the advantages.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a chip for manufacturing a transistor, a manufacturing method thereof, and a transistor.
Background
The wide-bandgap GaN-based semiconductor material has the excellent properties of large bandgap width, high thermal conductivity, high electron saturation drift velocity, easy formation of heterostructure and the like, and the transistor prepared from GaN is widely applied to microwave power devices. Along with the working frequency of the device is higher and higher, the output power is higher and higher, in order to solve the heat radiation performance of the device, diamond with high heat conductivity is selected as a substrate of a high-frequency and high-power gallium nitride-based device, and a gallium nitride heterostructure is formed above the substrate. However, due to the difference of crystal structures, the diamond crystal is in a cubic phase structure, and the gallium nitride material is in a hexagonal wurtzite structure, so that the difficulty of directly performing epitaxy on the gallium nitride material on a diamond substrate is high, and the difference between the lattice constant and the thermal expansion coefficient of gallium nitride and diamond is large, which brings difficulty to directly performing growth of gallium nitride-based heterostructure materials.
Therefore, how to solve the above technical problems should be a great concern to those skilled in the art.
Disclosure of Invention
The invention aims to provide a chip for manufacturing a transistor, a manufacturing method of the chip and the transistor, so that the reliability of the chip is improved.
In order to solve the above technical problem, the present application provides a method for manufacturing a chip for manufacturing a transistor, including:
forming a doped diamond layer on an upper surface of a substrate;
annealing the substrate and the doped diamond layer to convert the doped diamond layer into a graphene layer;
forming a buffer layer on the upper surface of the graphene layer;
and forming a heterostructure and a device on the upper surface of the buffer layer to obtain the chip.
Optionally, when the transistor is a high electron mobility transistor, the forming of the heterostructure on the upper surface of the buffer layer includes:
forming a high mobility layer on an upper surface of the buffer layer;
forming a barrier layer on an upper surface of the high mobility layer;
a cap layer is formed on the upper surface of the barrier layer.
Optionally, after forming the high mobility layer on the upper surface of the buffer layer, the method further includes:
forming an insertion layer on an upper surface of the high mobility layer;
accordingly, forming a barrier layer on an upper surface of the high mobility layer comprises:
forming the barrier layer on an upper surface of the insertion layer.
Optionally, the high mobility layer has a thickness of between 10nm and 100nm, inclusive.
Optionally, the thickness of the graphene layer is between 1nm and 10nm, inclusive.
Optionally, the thickness of the buffer layer is between 1 μm and 3 μm, inclusive.
Optionally, the barrier layer is AlxGa1-xAnd the layer N, wherein x is more than or equal to 0.10 and less than or equal to 0.35.
Optionally, the forming a buffer layer on the upper surface of the graphene layer includes:
and forming the buffer layer on the upper surface of the graphene layer by adopting a metal organic chemical vapor deposition method.
The application also provides a chip for manufacturing the transistor, and the chip is manufactured by adopting any one of the manufacturing methods for manufacturing the chip for manufacturing the transistor.
The application also provides a transistor which comprises the chip.
The application provides a manufacturing method of a chip for manufacturing a transistor, which comprises the following steps: forming a doped diamond layer on an upper surface of a substrate; annealing the substrate and the doped diamond layer to convert the doped diamond layer into a graphene layer; forming a buffer layer on the upper surface of the graphene layer; and forming a heterostructure and a device on the upper surface of the buffer layer to obtain the chip.
Therefore, in the chip manufacturing method, the doped diamond layer is firstly formed on the upper surface of the substrate in the manufacturing process, then annealing treatment is carried out, the doped diamond layer is converted into the graphene layer through the annealing treatment, form graphite alkene layer on the substrate promptly, and then at the upper surface of graphite alkene layer through in situ growth stack formation buffer layer and heterostructure and device in proper order, form one deck graphite alkene layer between substrate and buffer layer in also this application, graphite alkene is a two-dimensional crystal material, can regard as the stress release layer between substrate and the buffer layer on the one hand, effectively alleviate the stress between substrate and the buffer layer, on the other hand can also regard as the nucleation layer, the effectual crystal lattice dislocation density limit that two steps of growth methods can reach of having broken through, reduce the dislocation density of buffer layer more than an order of magnitude, improve the reliability of chip.
In addition, the application also provides a chip and a transistor with the advantages.
Drawings
For a clearer explanation of the embodiments or technical solutions of the prior art of the present application, the drawings needed for the description of the embodiments or prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a flowchart of a method for manufacturing a chip for manufacturing a transistor according to an embodiment of the present disclosure;
FIG. 2 is a flow chart of another method for manufacturing a chip for manufacturing a transistor according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of a chip according to an embodiment of the present disclosure.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the following detailed description will be given with reference to the accompanying drawings. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
As described in the background section, in order to solve the heat dissipation performance of the device, diamond is selected as the substrate, and a gallium nitride structure layer is formed above the substrate. However, due to the difference of crystal structures, the diamond crystal is in a cubic phase structure, and the gallium nitride material is in a hexagonal wurtzite structure, so that the difficulty of directly performing epitaxy on the gallium nitride material on a diamond substrate is high, and the difference between the lattice constant and the thermal expansion coefficient of gallium nitride and diamond is large, which brings difficulty to directly performing growth of gallium nitride-based heterostructure materials.
In view of the above, the present application provides a method for manufacturing a chip for manufacturing a transistor, please refer to fig. 1, where fig. 1 is a flowchart of a method for manufacturing a chip for manufacturing a transistor according to an embodiment of the present application, and the method includes:
step S101: a doped diamond layer is formed on the upper surface of the substrate.
The doping element can be boron, and the diamond layer doped with boron is of an asymmetric structure, so that the graphene layer obtained through subsequent annealing treatment has a band gap, and the application of the transistor manufactured by the chip is improved.
Firstly growing an undoped diamond transition layer on a substrate, placing the treated substrate in a chamber of a hot filament chemical vapor deposition system, introducing methane and hydrogen, and growing the diamond transition layer, wherein the substrate temperature is 700-1000 ℃, the reaction pressure is 3-8 kPa, and the thickness of the diamond transition layer is controlled to be 0.5-1 μm. Then growing boron-doped diamond on the transition layer, introducing methane, hydrogen and hydrogen carrying trimethyl borate, controlling the substrate temperature at 600-900 ℃ and the reaction pressure3-8 kPa, and the boron doping concentration formed on the diamond transition layer is 1021～1023cm-3And the doped diamond layer is 0.5-1 micron thick.
The substrate is a diamond substrate, the heat dissipation performance of the diamond is good, the self-heating effect of the chip can be reduced, the problem that the power density is rapidly reduced along with the increase of the total power and the increase of the frequency is solved, and the substrate has great influence on the performance improvement of the radio frequency power device and the heat dissipation improvement of the device.
Step S102: and annealing the substrate and the doped diamond layer to convert the doped diamond layer into a graphene layer.
The temperature of the annealing treatment was 600 ℃.
To avoid conversion of the graphene layer to graphite, the graphene layer has a thickness of between 1nm and 10nm, inclusive, e.g., 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, etc.
Step S103: and forming a buffer layer on the upper surface of the graphene layer.
The buffer layer can be a GaN layer, and the graphene layer can also solve the problem of large interface heat resistance when the diamond substrate is in direct contact with the GaN layer.
Note that the manner of forming the buffer layer is not particularly limited in the present application and may be selected. For example, a molecular beam epitaxy method, or a hydride vapor phase epitaxy method, or a Metal Organic Chemical Vapor Deposition (MOCVD) method may be employed.
When molecular beam epitaxy is used, the group III MO source used is usually a methyl or ethyl compound, such as Ga (CH)3)3，Ga(C2H5)3Etc. group V source is NH3Or nitrogen plasma, forming the buffer layer on the upper surface of the graphene layer, wherein the growth temperature is 800-850 ℃, the pressure is 300-500 Torr, and the vacuum degree is 10-10Torr。
Adopts hydride vapor phase epitaxy method to take metal Ga as gallium source and NH as nitrogen source3By N2、H2HCl is used as carrier gas, and the growth temperature is 900-1000 DEG CThe pressure 600-.
Preferably, the forming of the buffer layer on the upper surface of the graphene layer includes:
and forming the buffer layer on the upper surface of the graphene layer by adopting a metal organic chemical vapor deposition method, wherein the growth temperature is 900-1100 ℃, and the pressure is 300-500 Torr. The advantages of epitaxial growth of GaN layers using MOCVD include: by accurately controlling parameters such as the flow rate, the temperature and the like of the reaction source gas, not only can the components and the thickness of the epitaxial layer be accurately controlled, but also the physical properties of the material can be controlled, such as the conductivity type, the carrier concentration and the like; in the process, more pollution sources are prevented from being introduced, and the grown GaN layer has higher purity; the material doping efficiency is high, the steep distribution of impurities is easy to realize, and the heterojunction of the thin transition layer is prepared; the method is suitable for large-area GaN material epitaxy and has good uniformity. The deposition rate of the metal organic chemical vapor deposition method is faster than that of the molecular beam epitaxy method, and it is difficult to accurately control the film thickness by the hydride vapor phase epitaxy method.
The buffer layer has a thickness of between 1 μm and 3 μm, inclusive.
Step S104: and forming a heterostructure and a device on the upper surface of the buffer layer to obtain the chip.
The specific structure of the device is well known to those skilled in the art and will not be described in detail herein. The type of heterostructure depends on the type of transistor to be fabricated on the chip, and the transistor is exemplified as a high electron mobility transistor in the present application and is described below.
The chip manufacturing method in this application is in the manufacturing process, form doping diamond layer earlier on substrate upper surface, then carry out annealing treatment, make doping diamond layer change into graphite alkene layer through annealing treatment, form graphite alkene layer on the substrate promptly, and then stack formation buffer layer and heterostructure and device in proper order through the normal position growth at the upper surface of graphite alkene layer, form one deck graphite alkene layer between substrate and buffer layer in this application also, graphite alkene is a two-dimensional crystal material, can regard as the stress release layer between substrate and the buffer layer on the one hand, effectively alleviate the stress between substrate and the buffer layer, on the other hand can also regard as the nucleation layer, the effectual crystal lattice dislocation density limit that two steps of growth methods can reach that has broken through, reduce the dislocation density of buffer layer more than an order of magnitude, improve the reliability of chip.
On the basis of the above embodiments, in an embodiment of the present application, when the Transistor is a High Electron Mobility Transistor (HEMT), the forming of the heterostructure on the upper surface of the buffer layer includes:
forming a high mobility layer on an upper surface of the buffer layer;
forming a barrier layer on an upper surface of the high mobility layer;
a cap layer is formed on the upper surface of the barrier layer.
The material of the high mobility layer is GaN. In the present application, the formation method of the high mobility layer is not particularly limited and may be selected. For example, molecular beam epitaxy, or hydride vapor phase epitaxy, or metalorganic chemical vapor deposition may be employed.
By molecular beam epitaxy, the group III MO sources used are usually methyl or ethyl compounds, such as Ga (CH)3)3，Ga(C2H5)3Etc. group V source is NH3Or nitrogen plasma, the growth temperature of the high mobility layer is 800-850 ℃, the pressure is 300-500 Torr, and the vacuum degree is 10-10torr。
Adopts hydride vapor phase epitaxy method to take metal Ga as gallium source and NH as nitrogen source3By N2、H2HCl is used as carrier gas, the growth temperature is 900-1000 ℃, and the pressure is 600 ℃ and 700 Torr.
In order to improve the deposition speed and performance of the high mobility layer, the high mobility layer is formed by adopting a metal organic chemical vapor deposition method, the growth temperature is 900-1100 ℃, and the pressure is 300-500 Torr. The high mobility layer has a thickness between 10nm and 100nm, inclusive, e.g., 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, 90nm, etc.
The barrier layer is formed by a molecular beam epitaxy method or a metal organic chemical vapor deposition method, wherein the barrier layer is formed by the metal organic chemical vapor deposition method in order to improve the deposition speed and performance of the barrier layer, the growth temperature of the barrier layer is 900-1100 ℃, and the pressure is 300-500 Torr.
The barrier layer is AlxGa1-xN layer of AlxGa1-xThe heterostructure material system formed by the N layer and the high mobility layer has large band step difference and strong polarization effect, and even if no doping is used, the heterostructure material system can generate up to 10 percent in a quantum well of a heterointerface only through polarization stress13cm-2Wherein 0.10 x 0.35, for example, x can be 0.15, 0.20, 0.25, 0.30, and the like.
The barrier layer has a thickness between 10nm and 30nm, inclusive, e.g., 15nm, 20nm, 25nm, etc.
The cap layer is a GaN layer, the cap layer can play a passivation effect, channel electrons can be far away from the surface of the device, the influence of the surface state of the device on channel current is further reduced, the current collapse effect is inhibited, and the thickness of the cap layer is 1 nm-5 nm, including end points, such as 2nm, 3nm, 4nm and the like.
It should be noted that the cap layer is not specifically limited in the present application, as the case may be. For example, molecular beam epitaxy, or hydride vapor phase epitaxy, or metalorganic chemical vapor deposition may be employed. Preferably, the cap layer is formed by a metal organic chemical vapor deposition method so as to improve the forming speed and performance of the cap layer, the growth temperature of the cap layer is 900-1100 ℃, and the pressure is 300-500 Torr.
By molecular beam epitaxy, the group III MO sources used are usually methyl or ethyl compounds, such as Ga (CH)3)3，Ga(C2H5)3Etc. group V source is NH3Or nitrogen plasma, the growing temperature of the cap layer is 800-850 ℃, the pressure is 300-500 Torr, and the vacuum degree is 10-10torr。
Adopts hydride vapor phase epitaxy method to take metal Ga as gallium source and NH as nitrogen source3By N2、H2HCl as carrier gas, giveThe long temperature is 900-1000 ℃, and the pressure is 600-.
When the transistors correspondingly manufactured on the chip are other types of transistors, such as metal-oxide semiconductor field effect transistors or fin field effect transistors, the specific structure of the heterostructure can be set as required.
Referring to fig. 2, fig. 2 is a flowchart of another method for manufacturing a chip for manufacturing a transistor according to an embodiment of the present disclosure, where the method includes:
step S201: a doped diamond layer is formed on the upper surface of the substrate.
Step S202: and annealing the substrate and the doped diamond layer to convert the doped diamond layer into a graphene layer.
Step S203: and forming a buffer layer on the upper surface of the graphene layer.
Step S204: and forming a high mobility layer on the upper surface of the buffer layer.
Step S205: an insertion layer is formed on an upper surface of the high mobility layer.
The formation method of the insertion layer is not particularly limited in this application, and may be set by itself. For example, molecular beam epitaxy, or metal organic chemical vapor deposition may be used.
Preferably, the insertion layer is formed by a metal organic chemical vapor deposition method to improve the forming speed and performance of the insertion layer, the growth temperature of the insertion layer is 900-1100 ℃, and the pressure is 300-500 Torr.
The thickness of the insertion layer is between 0.7nm and 5nm, inclusive, e.g., 1nm, 2nm, 3nm, 4nm, etc.
The insertion layer is the AlN layer, introduces thin insertion layer, can effectively increase the potential barrier height, reduces the electron in the channel and pierces through the probability in the barrier layer, promotes high electron mobility transistor two-bit electron gas confinement nature, has reduced the unordered scattering of alloy that the barrier layer received by two-bit electron gas effectively to improve two-bit electron gas mobility by a wide margin.
By molecular beam epitaxy, the group III MO source used is usually a methyl or ethyl compound,such as Al (CH)3)3Etc. group V source is NH3Or nitrogen plasma, the growth temperature of the insertion layer is 800-850 ℃, the pressure is 300-500 Torr, and the vacuum degree is 10- 10torr。
Step S206: forming the barrier layer on an upper surface of the insertion layer.
Step S207: and forming a cap layer and a device on the upper surface of the barrier layer.
Please refer to the above embodiments for steps S201 to S204, and steps S206 and S207, which are not described herein in detail.
The application also provides a chip for manufacturing the transistor, and the chip is manufactured by adopting the manufacturing method of the chip for manufacturing the transistor in any embodiment.
When the chip is a chip for manufacturing a high electron mobility transistor, a schematic structural diagram of the chip is shown in fig. 3, and the chip includes a substrate 1, a graphene layer 2, a buffer layer 3, a high mobility layer 4, an insertion layer 5, a barrier layer 6, a cap layer 7, and a device 8, which are sequentially stacked from bottom to top.
The application also provides a transistor which comprises the chip in the embodiment.
The type of the transistor is not particularly limited in the present application, as the case may be. For example, the transistor may be a high electron mobility transistor, or a metal-oxide semiconductor field effect transistor, or a fin field effect transistor.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The chip for manufacturing the transistor, the manufacturing method thereof, and the transistor provided by the present application are described in detail above. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
Claims (10)
1. A method of fabricating a chip for fabricating a transistor, comprising:
forming a doped diamond layer on an upper surface of a substrate;
annealing the substrate and the doped diamond layer to convert the doped diamond layer into a graphene layer;
forming a buffer layer on the upper surface of the graphene layer;
and forming a heterostructure and a device on the upper surface of the buffer layer to obtain the chip.
2. The method of manufacturing a chip for manufacturing a transistor according to claim 1, wherein when the transistor is a high electron mobility transistor, the forming of the hetero-structure on the upper surface of the buffer layer includes:
forming a high mobility layer on an upper surface of the buffer layer;
forming a barrier layer on an upper surface of the high mobility layer;
a cap layer is formed on the upper surface of the barrier layer.
3. The method of manufacturing a chip for manufacturing a transistor according to claim 2, further comprising, after forming a high mobility layer on an upper surface of the buffer layer:
forming an insertion layer on an upper surface of the high mobility layer;
accordingly, forming a barrier layer on an upper surface of the high mobility layer comprises:
forming the barrier layer on an upper surface of the insertion layer.
4. The method of manufacturing a chip for manufacturing a transistor according to claim 2, wherein the high mobility layer has a thickness of between 10nm and 100nm, inclusive.
5. The method of fabricating a chip for a transistor according to claim 1, wherein the graphene layer has a thickness of between 1nm and 10nm, inclusive.
6. The method of claim 1, wherein the buffer layer has a thickness of between 1 μm and 3 μm, inclusive.
7. The method of claim 2, wherein the barrier layer is AlxGa1-xAnd the layer N, wherein x is more than or equal to 0.10 and less than or equal to 0.35.
8. The method of manufacturing a chip for manufacturing a transistor according to any one of claims 1 to 7, wherein the forming of the buffer layer on the upper surface of the graphene layer includes:
and forming the buffer layer on the upper surface of the graphene layer by adopting a metal organic chemical vapor deposition method.
9. A chip for manufacturing a transistor, characterized in that the chip is manufactured by the method for manufacturing a chip for manufacturing a transistor according to any one of claims 1 to 8.
10. A transistor, characterized in that the transistor comprises a chip according to claim 9.
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