CN113885391B - Dual-redundancy steering engine switching instruction interface circuit and instruction switching method - Google Patents
Dual-redundancy steering engine switching instruction interface circuit and instruction switching method Download PDFInfo
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- CN113885391B CN113885391B CN202111210628.0A CN202111210628A CN113885391B CN 113885391 B CN113885391 B CN 113885391B CN 202111210628 A CN202111210628 A CN 202111210628A CN 113885391 B CN113885391 B CN 113885391B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
Abstract
The invention discloses a dual-redundancy steering engine switching instruction interface circuit and an instruction switching method, wherein the circuit is respectively provided with an instruction control signal pin and a differential signal pin on two chips; the switching instruction differential output pins of the two chips are connected in parallel, so that a redundant output function of outputting a switching instruction QHOUT1 +/-is realized; the switching instruction output pin of the chip D1 is connected with the input pin, so that the switching instruction readback function is realized; the differential input pin of the chip D2 is connected with an input switching command QHIN2+/-. According to the invention, through the self-checking configuration and the switching configuration method of the switching instruction interface circuit, the functions of switching the main channel software, sending the fault switching instruction signal and receiving the standby channel switching instruction signal are realized, and the requirements of high reliability and strong universality of the dual-redundancy steering engine switching instruction interface circuit are met.
Description
Technical Field
The invention belongs to the technical field of electric servo control, and particularly relates to a main and standby channel switching instruction interface circuit of a dual-redundancy steering engine and an instruction switching method.
Background
The dual-redundancy steering engine switching instruction interface circuit mainly realizes the functions of main channel software switching, fault switching instruction signal sending and standby channel switching instruction signal receiving. The existing steering engine switching instruction sending interface circuit mostly adopts relay output switching value as switching instruction output signals; the switching instruction receiving interface circuit receives switching instruction input signals by adopting an optocoupler. The existing switching instruction interface circuit has the problem of large volume due to the adoption of a relay; parameters of the optical coupler are easily affected by temperature and cable length, so that the stability of a command signal is poor, and main and standby channels are easily switched by mistake; an optical coupler is adopted, one path of isolation power supply is needed to be added, and the complexity of a circuit is increased; the switching instruction sending and receiving interface circuits are different in form, and cannot be generalized.
The existing steering engine switching instruction interface circuit has the problems of large volume, complex circuit, poor reliability, poor universality and the like, and is difficult to meet the requirements of simplicity and reliability of the dual-redundancy steering engine switching instruction interface circuit.
Disclosure of Invention
In order to solve the defects in the prior art, the invention aims to solve the problems of large size, poor reliability and poor universality of a main and standby channel switching instruction interface circuit of a dual-redundancy steering engine, and provides a novel method for realizing the main and standby channel switching instruction interface circuit. The method adopts the differential transceiver to realize the functions of switching the main channel software, sending the fault switching command signal and receiving the standby channel switching command signal, and meets the requirements of high reliability and strong universality of the dual-redundancy steering engine switching command interface circuit.
The invention is realized by the following technical scheme.
In one aspect of the invention, a dual-redundancy steering engine switching instruction interface circuit is provided, which comprises two chips D1 and D2, wherein the two chips are respectively provided with an instruction 1, a control signal pin 2-5 and a differential signal pin 9-12;
the output switching instruction QHOUT1 +/-of the No. 1 steering engine controller is connected with the input switching instruction QHIN2+/-, and the output switching instruction QHOUT1 +/-of the No. 2 steering engine controller is connected with the input switching instruction QHIN2+/-, of the No. 1 steering engine controller.
Preferably, pins 5 of the chips D1 and D2 are connected with CMOS devices in parallel, and the CMOS devices are respectively connected with a CPU fault switching end and a software switching end.
Preferably, the pins 6 and 7 of the chips D1 and D2 are grounded, and the pins 14 of the chips D1 and D2 are connected to a 3.3V power supply.
Preferably, pins 2, 3, 4, 12, 11 of the chip D1 are respectively connected to the switch command 1 to receive the signal QHIN1, the switch command 1 receives the enable signal/REN 1, the switch command 1 sends the enable signal TEN1, and the switch command 1 outputs the signal qhout1+/-.
Preferably, pins 2, 3, 4, 12, 11 of the chip D2 are respectively connected to the switch command 2 receiving signal QHIN2, the switch command 2 receiving enable signal/REN 2, the switch command 1 sending enable signal TEN2, and the switch command 2 inputting signal QHIN2+/-.
Preferably, pins 5 of the chips D1 and D2 are connected with the switch command 1 to send the signal QHOUT1, and pins 9 and 10 are connected with the switch command 1 to output the signal QHOUT1+/-.
Preferably, the switch instruction 1 signal QHOUT1 is a processor software switch instruction or a fault switch instruction given by a processor fault detection circuit.
Preferably, the pull-down resistor R2 is grounded, and the pull-up resistor R1 is connected to a 3.3V power supply.
In another aspect of the present invention, an instruction switching method for a dual-redundancy steering engine switching instruction interface circuit is provided, including self-checking configuration:
firstly, setting signals of REN1, TEN1,/REN 2 and TEN2 to be 0, and turning on receiving functions of chips D1 and D2; reading QHIN2 signal, and the normal value is 0;
setting TEN1 and QHOUT1 signals to be 1; turning on the transmitting function of the chip D1, delaying by 10us, and reading the QHIN1 signal should be "1"; setting the QHOUT1 signal to be 0, delaying for 10us, and reading the QHIN1 signal to be 0, so that the chip D1 is normal in function;
setting TEN1 signal as '0', setting TEN2 and QHOUT1 signals as '1', turning on the transmitting function of the chip D2, delaying for 10us, and reading QHIN1 signal as '1'; setting the QHOUT1 signal to be 0, delaying for 10us, and reading the QHIN1 signal to be 0, so that the chip D2 is normal in function;
the TEN1 signal is set to "1", the TEN2 and QHOUT1 signals are set to "0", the transmission function of the chip D1 is turned on, and the switching instruction 1 output signal QHOUT1 +/-is set to a non-switching state.
In still another aspect of the present invention, an instruction switching method for a dual-redundancy steering engine switching instruction interface circuit is provided, including a switching configuration:
A. software switching main and standby channel flow
The software sets QHOUT1 signal as '1', delays for 10us, reads QHIN1 signal as '1', and indicates that the switching instruction 1 is normally sent, and the switching is finished; otherwise, executing the setting of '1', delaying, and continuously performing the reading operation for three times, if the QHIN1 signal is '1', sending the switching instruction 1 normally, and ending the switching; otherwise, the sending function of the chip D1 is invalid, and the chip D2 is used for sending the switching instruction 1;
the software sets TEN1 signals to be 0, TEN2 and QHOUT1 signals to be 1, delay is carried out by 10us, and if the read QHIN1 signals are 1, the switching instruction 1 sends normally, and switching is finished; otherwise, executing the setting of '1', delaying, and continuously performing the reading operation for three times, if the QHIN1 signal is '1', sending the switching instruction 1 normally, and ending the switching; otherwise, the sending function of the chip D2 is also invalid, and the switching operation is finished;
B. backup channel start workflow
And the software periodically detects the state of the QHIN2 signal, and if 3 pieces of 10us are continuously used, the read QHIN2 signals are all 1, which indicates that the switching instruction 2 signal QHIN2 is in a switching state, and then the standby channel steering engine is started to work.
Due to the adoption of the technical scheme, the invention has the following beneficial effects:
the dual-redundancy steering engine switching instruction interface circuit provided by the invention adopts the instruction redundancy and instruction readback design, and the switching instruction sending reliability is high; in the power-on initialization process, the interface state of the switching instruction is stable, and a false switching instruction cannot occur; the differential signal is adopted to carry out switching instruction transmission, so that the anti-interference capability of the signal is effectively improved; the area of the switching instruction interface circuit is reduced by 50% compared with the area of the prior relay and optocoupler interface circuit by adopting the differential transceiver circuit design, and the reliability is improved by 30%.
The invention has the advantages of simple circuit, flexible configuration, high reliability and the like. The switching instruction interface circuit is a universal dual-redundancy steering engine switching instruction interface circuit and can meet the switching requirements of main and standby channels of a common dual-redundancy steering engine.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate and do not limit the invention, and together with the description serve to explain the principle of the invention:
FIG. 1 is a dual redundancy steering engine system architecture;
fig. 2 is a schematic diagram of a switch instruction interface circuit.
Detailed Description
The present invention will now be described in detail with reference to the drawings and the specific embodiments thereof, wherein the exemplary embodiments and descriptions of the present invention are provided for illustration of the invention and are not intended to be limiting.
Referring to fig. 1, the dual-redundancy steering engine switching instruction interface circuit provided by the invention is used in a dual-redundancy steering engine system, and switching instruction interface circuits are respectively arranged in a 1# steering engine controller and a 2# steering engine controller in the dual-redundancy steering engine system, so that the position closed-loop control function of a throttle and a front wheel steering engine of the dual-redundancy steering engine system is realized. Under normal conditions, the 1# steering engine controller controls the main channel of the throttle steering engine to work, the 2# steering engine controller controls the main channel of the front wheel steering engine to work, and the throttle and the standby channel of the front wheel steering engine are in a hot standby state. If the main channel of the air door steering engine fails or the No. 1 controller receives a software switching instruction through a bus, the No. 1 controller sends a switching instruction 1 to the No. 2 controller through a switching instruction interface circuit. And after the 2# controller receives the switching instruction 1, starting the throttle steering engine standby channel to work. And similarly, after the 1# controller receives the switching instruction 2, starting the front-wheel steering engine standby channel to work.
The output switching instruction QHOUT1 +/-of the No. 1 steering engine controller is connected with the input switching instruction QHIN2+/-, and the output switching instruction QHOUT1 +/-of the No. 2 steering engine controller is connected with the input switching instruction QHIN2+/-, of the No. 1 steering engine controller.
The principle of the switching instruction interface circuit is shown in fig. 2, and a circuit schematic diagram, an initialization configuration and a switching configuration method are described as follows.
The switching instruction interface circuit realizes the sending and receiving functions of the switching instructions of the main and standby channels of the steering engine. The switching instruction interface circuit consists of 2 MAX3491 chips with the bit numbers of D1 and D2 and 0.25W-1KΩ resistor with the bit numbers of R1 and R2. The interface circuit comprises 2 MAX3491 chips with the bit numbers of D1 and D2, wherein instruction 1, 2 control signal pins 2-5 and differential signal pins 9-12 are respectively arranged on the chips D1 and D2, and the pins 5 of the chips D1 and D2 are connected with a CMOS device in parallel; the pins 6 and 7 of the chips D1 and D2 are respectively grounded, and the pins 14 of the chips D1 and D2 are respectively connected with a 3.3V power supply; the pins 10 of the chips D1 and D2 are connected in parallel and connected with the pin 11 of the chip D1, and a switching instruction QHOUT 1-is output; the pins 9 of the chips D1 and D2 are connected in parallel and connected with the pin 12 of the chip D1, and a switching instruction QHOUT1+ is output; pins 11 and 12 of the chip D2 are connected with pull-up resistors R1 and R2, the pull-down resistor R2 is grounded, and the pull-up resistor R1 is connected with a 3.3V power supply; pin 12 of chip D2 receives and inputs switching command QHIN2+; pin 11 of chip D2 receives input of switching command QHIN2-.
Comprises 7 internal signals (1-7) and 4 external signals (8-11). The internal signals are control and status signals between the switching command interface circuit and the control circuit, and the external signals are switching command signals between steering engine controllers. The definition of the input and output signals of the switching command interface circuit is shown in table 1.
Table 1 switching instruction interface circuit signal definition
The circuit signal connection relationship is as follows:
(1) pins 2, 3, 4, 12, 11 of the chip D1 are respectively connected to the switch command 1 to receive the signal QHIN1, the switch command 1 receives the enable signal/REN 1, the switch command 1 sends the enable signal TEN1, and the switch command 1 outputs the signal qhout1+/-.
(2) Pins 2, 3, 4, 12 and 11 of the chip D2 are respectively connected with a switching instruction 2 receiving signal QHIN2, the switching instruction 2 receiving an enabling signal/REN 2, the switching instruction 1 sending an enabling signal TEN2, and the switching instruction 2 inputting a signal QHIN2+/-. Meanwhile, pins 11 and 12 of the chip D2 are connected with pull-up resistors R1 and R2.
(3) The pins D1 and D2 are connected with the switching instruction 1 to send the signal QHOUT1, and the pins 9 and 10 are connected with the switching instruction 1 to output the signal QHOUT1+/-. The signal QHOUT1 sent by the switch instruction 1 may be a processor software switch instruction, or may be a fault switch instruction given by a processor fault detection circuit.
The MAX3491 chip is used for transmitting RS-485/422 bus serial data, and the circuit is only used for receiving and transmitting 1 data bit switching instruction. The chip is responsible for converting a switching instruction output by the control circuit into a differential switching instruction and sending the differential switching instruction; and meanwhile, the received differential switching instruction is converted into TTL level and output to the control circuit. The switch command 2 input signal QHIN2 +/-employs a pull-up resistor to ensure that the switch command initial state is "0".
The switch command 1 signal QHOUT1 is simultaneously connected to the chips D1 and D2, and the redundant output of the switch command 1 can be realized by controlling the transmission enable pins 4 of the chips D1 and D2. The differential output and input end of the chip D1 adopts a loop test connection mode (9, 12 pins are interconnected, 10, 11 pins are interconnected), and readback of the switching instruction 1 can be realized. The two measures can ensure that the switching instruction can be reliably sent out.
The distance of the signal transmission by using the MAX3491 chip is up to kilometers; the differential signal has strong anti-interference capability, and can ensure the reliability of switching instruction transmission.
Self-checking configuration
After the power-on reset of the steering engine controller is completed, the processor software performs self-checking on the switching instruction interface circuit, and the MAX3491 chip is ensured to function normally.
The software firstly sets the signals of REN1, TEN1,/REN 2 and TEN2 to be 0, and opens the receiving functions of the chips D1 and D2; reading QHIN2 signal, and the normal value is 0; then TEN1 and QHOUT1 signals are set as '1', the transmitting function of the chip D1 is started, delay is carried out for 10us, the read QHIN1 signal is set as '1', the QHOUT1 signal is set as '0', delay is carried out for 10us, the read QHIN1 signal is set as '0', and the chip D1 is indicated to be normal in function; then, setting TEN1 signals as 0, setting TEN2 and QHOUT1 signals as 1, turning on the transmitting function of the chip D2, delaying for 10us, setting the read QHIN1 signal as 1, setting the QHOUT1 signal as 0, delaying for 10us, setting the read QHIN1 signal as 0, and indicating that the chip D2 is normal in function; finally, the TEN1 signal is set to be "1", the TEN2 and QHOUT1 signals are set to be "0", the transmitting function of D1 is turned on, and the switching instruction 1 output signal QHOUT1 +/-is set to be in a non-switching state.
Switch configuration
During the working period of the steering engine controller, if the controller receives a software switching instruction issued by a bus or the processor detects a main channel fault, the processor performs main and standby channel switching through the software switching instruction; if the processor fails, the fault detection circuit sets the CPU fault switching signal to be effective, and the main and standby channels are switched independently.
And during the working period of the steering engine controller, if the processor receives the switching instruction, starting the steering engine with the standby channel to work.
(1) Software switching main and standby channel flow
The software sets QHOUT1 signal as '1', delays for 10us, reads QHIN1 signal as '1', and indicates that the switching instruction 1 is normally sent, and the switching is finished; otherwise, executing the setting of '1', delaying, and continuously performing the reading operation for three times, if the QHIN1 signal is '1', sending the switching instruction 1 normally, and ending the switching; otherwise, the sending function of the chip D1 is invalid, and the chip D2 is used for sending the switching instruction 1.
The software sets TEN1 signals to be 0, TEN2 and QHOUT1 signals to be 1, delay is carried out by 10us, and if the read QHIN1 signals are 1, the switching instruction 1 sends normally, and switching is finished; otherwise, executing the setting of '1', delaying, and continuously performing the reading operation for three times, if the QHIN1 signal is '1', sending the switching instruction 1 normally, and ending the switching; otherwise, the sending function of the chip D2 is also invalid, and the switching operation is finished.
(2) Backup channel start workflow
And the software periodically detects the state of the QHIN2 signal, and if 3 pieces of 10us are continuously used, the read QHIN2 signals are all 1, which indicates that the switching instruction 2 signal QHIN2 is in a switching state, and then the standby channel steering engine is started to work.
The method solves the problems that in the prior art, a steering engine switching instruction transmitting interface circuit adopts relay output switching value as a switching instruction output signal, a switching instruction receiving interface circuit adopts an optical coupler device to receive a switching instruction input signal, the switching instruction input signal is large in size and is influenced by temperature and cable length, the stability of an instruction signal is poor, main and standby channels are easy to switch by mistake, the main channel software switching and the sending of a fault switching instruction signal can be realized, and the receiving function of the standby channel switching instruction signal can be realized, so that the requirements of reliability and universality of the dual-redundancy steering engine switching instruction interface circuit are met.
The invention is not limited to the above embodiments, and based on the technical solution disclosed in the invention, a person skilled in the art may make some substitutions and modifications to some technical features thereof without creative effort according to the technical content disclosed, and all the substitutions and modifications are within the protection scope of the invention.
Claims (3)
1. The dual-redundancy steering engine switching instruction interface circuit is characterized by comprising two chips D1 and D2, wherein the two chips are respectively provided with an instruction 1, a control signal pin 2-5 and a differential signal pin 9-12;
pins 10 of the chips D1 and D2 are connected in parallel and connected with a pin 11 of the chip D1, and a switching instruction QHOUT 1-is output;
pins 9 of the chips D1 and D2 are connected in parallel and connected with a pin 12 of the chip D1, and a switching instruction QHOUT1+ is output;
pins 11 and 12 of the chip D2 are connected with pull-up resistors R1 and R2; pin 12 of chip D2 receives and inputs switching command QHIN2+; the pin 11 of the chip D2 is connected with an input switching instruction QHIN2-;
the output switching instruction QHOUT1 +/-of the 1# steering engine controller is connected with the input switching instruction QHIN2+/-, and the output switching instruction QHOUT1 +/-of the 2# steering engine controller is connected with the input switching instruction QHIN2+/-, of the 1# steering engine controller;
the pins 5 of the chips D1 and D2 are connected with CMOS devices in parallel, and the CMOS devices are respectively connected with a CPU fault switching end and a software switching end;
the pins 6 and 7 of the chips D1 and D2 are respectively grounded, and the pins 14 of the chips D1 and D2 are respectively connected with a 3.3V power supply;
pins 2, 3, 4, 12 and 11 of the chip D1 are respectively connected with a switching instruction 1 receiving signal QHIN1, the switching instruction 1 receiving an enabling signal/REN 1, the switching instruction 1 sending an enabling signal TEN1, and the switching instruction 1 outputting a signal QHOUT1+/-;
pins 2, 3, 4, 12 and 11 of the chip D2 are respectively connected with a switching instruction 2 receiving signal QHIN2, the switching instruction 2 receives an enabling signal/REN 2, the switching instruction 1 sends an enabling signal TEN2, and the switching instruction 2 inputs a signal QHIN2+/-;
the 5 pins of the chips D1 and D2 are connected with the switching instruction 1 to send a signal QHOUT1, and the 9 pins and the 10 pins are connected with the switching instruction 1 to output a signal QHOUT1+/-;
the signal QHOUT1 sent by the switching instruction 1 is a processor software switching instruction or a fault switching instruction given by a processor fault detection circuit;
the pull-down resistor R2 is grounded, and the pull-up resistor R1 is connected with a 3.3V power supply.
2. An instruction switching method using the dual-redundancy steering engine switching instruction interface circuit of claim 1, comprising a self-checking configuration:
firstly, setting signals of REN1, TEN1,/REN 2 and TEN2 to be 0, and turning on receiving functions of chips D1 and D2; reading QHIN2 signal, and the normal value is 0;
setting TEN1 and QHOUT1 signals to be 1; turning on the transmitting function of the chip D1, delaying by 10us, and reading the QHIN1 signal should be "1"; setting the QHOUT1 signal to be 0, delaying for 10us, and reading the QHIN1 signal to be 0, so that the chip D1 is normal in function;
setting TEN1 signal as '0', setting TEN2 and QHOUT1 signals as '1', turning on the transmitting function of the chip D2, delaying for 10us, and reading QHIN1 signal as '1'; setting the QHOUT1 signal to be 0, delaying for 10us, and reading the QHIN1 signal to be 0, so that the chip D2 is normal in function;
the TEN1 signal is set to "1", the TEN2 and QHOUT1 signals are set to "0", the transmission function of the chip D1 is turned on, and the switching instruction 1 output signal QHOUT1 +/-is set to a non-switching state.
3. An instruction switching method using the dual redundancy steering engine switching instruction interface circuit of claim 1, comprising a switching configuration:
A. software switching main and standby channel flow
The software sets QHOUT1 signal as '1', delays for 10us, reads QHIN1 signal as '1', and indicates that the switching instruction 1 is normally sent, and the switching is finished; otherwise, executing the setting of '1', delaying, and continuously performing the reading operation for three times, if the QHIN1 signal is '1', sending the switching instruction 1 normally, and ending the switching; otherwise, the sending function of the chip D1 is invalid, and the chip D2 is used for sending the switching instruction 1;
the software sets TEN1 signals to be 0, TEN2 and QHOUT1 signals to be 1, delay is carried out by 10us, and if the read QHIN1 signals are 1, the switching instruction 1 sends normally, and switching is finished; otherwise, executing the setting of '1', delaying, and continuously performing the reading operation for three times, if the QHIN1 signal is '1', sending the switching instruction 1 normally, and ending the switching; otherwise, the sending function of the chip D2 is also invalid, and the switching operation is finished;
B. backup channel start workflow
And the software periodically detects the state of the QHIN2 signal, and if 3 pieces of 10us are continuously used, the read QHIN2 signals are all 1, which indicates that the switching instruction 2 signal QHIN2 is in a switching state, and then the standby channel steering engine is started to work.
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011204266A (en) * | 2011-06-10 | 2011-10-13 | Fujitsu Ltd | Method of managing redundancy of basic input/output program, and data processing device |
| EP2506101A2 (en) * | 2011-03-29 | 2012-10-03 | General Electric Company | Hart channel interface component including redundancy |
| CN102759891A (en) * | 2012-06-07 | 2012-10-31 | 中国航天科技集团公司第九研究院第七七一研究所 | Hard handover dual-redundancy CAN controller |
| CN104697593A (en) * | 2015-03-24 | 2015-06-10 | 合肥工业大学 | Ultrasonic gas flowmeter on basis of FPGA (field programmable gate array) and DSP (digital signal processor) |
| EP3054385A1 (en) * | 2015-02-09 | 2016-08-10 | Bedrock Automation Platforms Inc. | Input/output module with multi-channel switching capability |
| CN205620746U (en) * | 2016-05-09 | 2016-10-05 | 国网宁夏电力公司检修公司 | Accurate intelligent control device of transformer cooler based on AD sampling |
| CN107526289A (en) * | 2016-06-21 | 2017-12-29 | 李福霞 | A kind of two redundancy actuator control systems based on CAN |
| CN210294832U (en) * | 2019-06-26 | 2020-04-10 | 中国航天空气动力技术研究院 | Dual-redundancy CAN bus communication device suitable for autonomous underwater vehicle |
| CN111399416A (en) * | 2020-03-26 | 2020-07-10 | 西安微电子技术研究所 | Double-shaft steering engine controller based on MCU processor |
| CN112182876A (en) * | 2020-09-25 | 2021-01-05 | 西安微电子技术研究所 | Dual-redundancy steering engine channel fault switching system and logic design method |
| CN113447891A (en) * | 2021-04-28 | 2021-09-28 | 中国电子科技集团公司第十四研究所 | Satellite-borne radar exchange interface module |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9780640B2 (en) * | 2015-12-15 | 2017-10-03 | Monolithic Power Systems, Inc. | Multi-phase voltage converter with fault instruction circuit |
-
2021
- 2021-10-18 CN CN202111210628.0A patent/CN113885391B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2506101A2 (en) * | 2011-03-29 | 2012-10-03 | General Electric Company | Hart channel interface component including redundancy |
| JP2011204266A (en) * | 2011-06-10 | 2011-10-13 | Fujitsu Ltd | Method of managing redundancy of basic input/output program, and data processing device |
| CN102759891A (en) * | 2012-06-07 | 2012-10-31 | 中国航天科技集团公司第九研究院第七七一研究所 | Hard handover dual-redundancy CAN controller |
| EP3054385A1 (en) * | 2015-02-09 | 2016-08-10 | Bedrock Automation Platforms Inc. | Input/output module with multi-channel switching capability |
| CN104697593A (en) * | 2015-03-24 | 2015-06-10 | 合肥工业大学 | Ultrasonic gas flowmeter on basis of FPGA (field programmable gate array) and DSP (digital signal processor) |
| CN205620746U (en) * | 2016-05-09 | 2016-10-05 | 国网宁夏电力公司检修公司 | Accurate intelligent control device of transformer cooler based on AD sampling |
| CN107526289A (en) * | 2016-06-21 | 2017-12-29 | 李福霞 | A kind of two redundancy actuator control systems based on CAN |
| CN210294832U (en) * | 2019-06-26 | 2020-04-10 | 中国航天空气动力技术研究院 | Dual-redundancy CAN bus communication device suitable for autonomous underwater vehicle |
| CN111399416A (en) * | 2020-03-26 | 2020-07-10 | 西安微电子技术研究所 | Double-shaft steering engine controller based on MCU processor |
| CN112182876A (en) * | 2020-09-25 | 2021-01-05 | 西安微电子技术研究所 | Dual-redundancy steering engine channel fault switching system and logic design method |
| CN113447891A (en) * | 2021-04-28 | 2021-09-28 | 中国电子科技集团公司第十四研究所 | Satellite-borne radar exchange interface module |
Non-Patent Citations (3)
| Title |
|---|
| 一种多通道双余度舵机控制系统设计;王晴 等;《中国航天电子技术研究院科学技术委员会2020年学术年会优秀论文集》;第155-162页 * |
| 基于3片C8051F020仲裁热备份舵机控制系统硬件设计;茹毅;毛征;刘松松;罗子安;孟灿;;《国外电子测量技术》(03);第93-97页 * |
| 基于FPGA的双余度无刷舵机控制系统的设计;黄健;王强;;《微电机》(12);第45-47和55页 * |
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| CN113885391A (en) | 2022-01-04 |
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