CN113885391A - Dual-redundancy steering engine switching instruction interface circuit and instruction switching method - Google Patents
Dual-redundancy steering engine switching instruction interface circuit and instruction switching method Download PDFInfo
- Publication number
- CN113885391A CN113885391A CN202111210628.0A CN202111210628A CN113885391A CN 113885391 A CN113885391 A CN 113885391A CN 202111210628 A CN202111210628 A CN 202111210628A CN 113885391 A CN113885391 A CN 113885391A
- Authority
- CN
- China
- Prior art keywords
- switching
- signal
- switching instruction
- chip
- steering engine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25257—Microcontroller
Abstract
The invention discloses a dual-redundancy steering engine switching instruction interface circuit and an instruction switching method, wherein the circuit is provided with an instruction control signal pin and a differential signal pin on two chips respectively; the switching instruction differential output pins of the two chips are connected in parallel, so that the redundant output function of outputting the switching instruction QHOUT1 +/-is realized; the switching instruction output pin of the chip D1 is connected with the input pin, so that the switching instruction read-back function is realized; the differential input pin of the chip D2 is connected with the input switching command QHIN2 +/-. According to the invention, through the self-checking configuration and switching configuration method of the switching instruction interface circuit, the functions of main channel software switching, sending of fault switching instruction signals and receiving of standby channel switching instruction signals are realized, and the requirements of high reliability and strong universality of the dual-redundancy steering engine switching instruction interface circuit are met.
Description
Technical Field
The invention belongs to the technical field of electric servo control, and particularly relates to a dual-redundancy steering engine main/standby channel switching instruction interface circuit and an instruction switching method.
Background
The dual-redundancy steering engine switching instruction interface circuit mainly achieves the functions of main channel software switching, sending of fault switching instruction signals and receiving of standby channel switching instruction signals. The existing steering engine switching instruction sending interface circuit mostly adopts a relay to output switching value as a switching instruction output signal; the switching instruction receiving interface circuit mostly adopts an optical coupler device to receive a switching instruction input signal. The existing switching instruction interface circuit has the problem of large volume due to the adoption of a relay; parameters of the optocoupler are easily influenced by temperature and cable length, so that the stability of the command signal is poor, and the main channel and the standby channel are easily subjected to mis-switching; the optical coupler is adopted, one path of isolation power supply needs to be added, and the complexity of the circuit is increased; the switching instruction sending and receiving interface circuits have different forms, and can not realize generalization.
The existing steering engine switching instruction interface circuit has the problems of large volume, complex circuit, poor reliability and universality and the like, and the requirement of simple and reliable dual-redundancy steering engine switching instruction interface circuit is difficult to meet.
Disclosure of Invention
In order to solve the defects in the prior art, the invention aims to solve the problems of large volume, poor reliability and poor universality of a main/standby channel switching instruction interface circuit of a dual-redundancy steering engine, and provides a novel method for realizing the main/standby channel switching instruction interface circuit. The method adopts the differential transceiver to realize the functions of main channel software switching, fault switching instruction signal sending and standby channel switching instruction signal receiving, and meets the requirements of high reliability and strong generalization of a dual-redundancy steering engine switching instruction interface circuit.
The invention is realized by the following technical scheme.
The invention provides a dual-redundancy steering engine switching instruction interface circuit which comprises two chips D1 and D2, wherein the two chips are respectively provided with an instruction 1 control signal pin 2-5 and a differential signal pin 9-12;
the output switching instruction QHOUT1 of the 1# steering engine controller is +/-connected with the input switching instruction QHIN2 +/-of the 2# steering engine controller, and the output switching instruction QHOUT1 of the 2# steering engine controller is +/-connected with the input switching instruction QHIN2 +/-of the 1# steering engine controller.
Preferably, pins 5 of the chips D1 and D2 are connected with CMOS devices in parallel, and the CMOS devices are respectively connected with a CPU fault switching end and a software switching end.
Preferably, pins 6 and 7 of the chips D1 and D2 are grounded, and pins 14 of the chips D1 and D2 are grounded, respectively, to a 3.3V power supply.
Preferably, pins 2, 3, 4, 12 and 11 of the chip D1 are respectively connected to the switch command 1 receiving signal QHIN1, the switch command 1 receiving enable signal/REN 1, the switch command 1 sending enable signal TEN1, the switch command 1 outputting signal QHOUT1 +/-.
Preferably, pins 2, 3, 4, 12 and 11 of the chip D2 are respectively connected to the switch command 2 receiving signal QHIN2, the switch command 2 receiving enable signal/REN 2, the switch command 1 sending enable signal TEN2, and the switch command 2 inputting signal QHIN2 +/-.
Preferably, the 5 pins of the chips D1 and D2 are connected to the switching instruction 1 sending signal QHOUT1, and the 9 and 10 pins are connected to the switching instruction 1 outputting signal QHOUT1 +/-.
Preferably, the switching instruction 1 sending signal QHOUT1 is a processor software switching instruction, or a failover instruction given by a processor failure detection circuit.
Preferably, pull-down resistor R2 is connected to ground, and pull-up resistor R1 is connected to a 3.3V power supply.
In another aspect of the present invention, an instruction switching method for a dual redundancy steering engine switching instruction interface circuit is provided, which includes:
firstly, setting signals of/REN 1, TEN1,/REN 2 and TEN2 as '0', and opening the receiving functions of the chips D1 and D2; then read the QHIN2 signal, the normal value should be "0";
setting signals TEN1 and QHOUT1 as '1'; the send function of chip D1 is turned on, delayed by 10us, and the read QHIN1 signal should be "1"; setting the QHOUT1 signal to be '0', delaying for 10us, and reading the QHIN1 signal to be '0', which indicates that the chip D1 is normal in function;
setting the signal TEN1 to be 0, setting the signals TEN2 and QHOUT1 to be 1, opening the sending function of the chip D2, delaying for 10us, and reading the signal QHIN1 to be 1; setting the QHOUT1 signal to be '0', delaying for 10us, and reading the QHIN1 signal to be '0', which indicates that the chip D2 is normal in function;
the TEN1 signal is set to "1", the TEN2 and QHOUT1 signals are set to "0", the transmit function of the chip D1 is turned on, and the switch command 1 output signal QHOUT1 is set to a non-switching state.
In another aspect of the present invention, a method for switching commands of a dual-redundancy steering engine switching command interface circuit is provided, which includes:
A. software switching main/standby channel flow
Setting a QHOUT1 signal to be 1 by software, delaying for 10us, reading a QHIN1 signal, if the signal is 1, indicating that the switching instruction 1 is sent normally, and ending the switching; otherwise, setting 1, delaying, continuously reading for three times, if the QHIN1 signal is 1, sending a switching instruction 1 normally, and ending the switching; otherwise, the chip D1 sends out a failure function, and the chip D2 is used for sending a switching instruction 1;
setting a TEN1 signal to be 0 by software, setting TEN2 and QHOUT1 signals to be 1, delaying for 10us, reading a QHIN1 signal, if the signal is 1, indicating that the switching instruction 1 is sent normally, and ending the switching; otherwise, setting 1, delaying, continuously reading for three times, if the QHIN1 signal is 1, sending a switching instruction 1 normally, and ending the switching; otherwise, the sending function of the chip D2 is also failed, and the switching operation is finished;
B. backup channel start workflow
And periodically detecting the state of the QHIN2 signal by software, and if the QHIN2 signal is read to be 1 after 3 continuous 10us, indicating that the signal QHIN2 of the switching command 2 is in a switching state, starting the steering engine of the standby channel to work.
Due to the adoption of the technical scheme, the invention has the following beneficial effects:
the dual-redundancy steering engine switching instruction interface circuit provided by the invention adopts the design of instruction redundancy and instruction readback, and the switching instruction sending reliability is high; in the power-on initialization process, the state of a switching instruction interface is stable, and a wrong switching instruction cannot occur; the switching instruction transmission is carried out by adopting the differential signal, so that the anti-interference capability of the signal is effectively improved; by adopting the circuit design of the differential transceiver, the area of the switching instruction interface circuit is reduced by 50% compared with the area of the prior relay and optical coupling interface circuit, and the reliability is improved by 30%.
The invention has the advantages of simple circuit, flexible configuration, high reliability and the like. The switching instruction interface circuit of the dual-redundancy steering engine is universal, and can meet the requirement of switching the main channel and the standby channel of the common dual-redundancy steering engine.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principles of the invention:
FIG. 1 is a dual-redundancy steering engine system architecture;
FIG. 2 is a schematic diagram of a switch command interface circuit.
Detailed Description
The present invention will now be described in detail with reference to the drawings and specific embodiments, wherein the exemplary embodiments and descriptions of the present invention are provided to explain the present invention without limiting the invention thereto.
Referring to fig. 1, the switching instruction interface circuit of the dual-redundancy steering engine provided by the invention is used in a dual-redundancy steering engine system, and switching instruction interface circuits are respectively arranged in a 1# steering engine controller and a 2# steering engine controller in the dual-redundancy steering engine system, so that the position closed-loop control function of an air door and a front wheel steering engine of the dual-redundancy steering engine system is realized. Under the normal condition, 1# steering engine controller control air door steering engine main channel work, 2# steering engine controller control front wheel steering engine main channel work, and the air door is in the hot standby state with the reserve passageway of front wheel steering engine. If the main channel of the air door steering engine is in fault or the 1# controller receives a software cutter cutting instruction through a bus, the 1# controller sends a switching instruction 1 to the 2# controller through a switching instruction interface circuit. And after the 2# controller receives the switching instruction 1, starting the air door steering engine standby channel to work. And similarly, after the 1# controller receives the switching instruction 2, the front wheel steering engine standby channel is started to work.
The output switching instruction QHOUT1 of the 1# steering engine controller is +/-connected with the input switching instruction QHIN2 +/-of the 2# steering engine controller, and the output switching instruction QHOUT1 of the 2# steering engine controller is +/-connected with the input switching instruction QHIN2 +/-of the 1# steering engine controller.
The switching command interface circuit principle is shown in fig. 2, and the circuit principle diagram, initialization configuration and switching configuration method are described as follows.
The switching instruction interface circuit realizes the functions of sending and receiving the steering engine main/standby channel switching instructions. The switching command interface circuit consists of 2 MAX3491 chips with bit numbers of D1 and D2 and 2 resistors with bit numbers of R1 and R2 of 0.25W-1K omega. The interface circuit comprises 2 MAX3491 chips with the bit numbers of D1 and D2, wherein the chips D1 and D2 are respectively provided with an instruction 1, a 2 control signal pin 2-5 and a differential signal pin 9-12, and the pins D1 and D2 5 of the chips are connected with a CMOS device in parallel; pins 6 and 7 of the chip D1 and D2 are grounded respectively, and pins 14 of the chip D1 and D2 are connected with a 3.3V power supply respectively; the chip D1 and the D2 pin 10 are connected in parallel and are connected with the chip D1 pin 11, and a switching instruction QHOUT1 & lt- & gt is output; the chip D1 and the D2 pin 9 are connected in parallel and are connected with the chip D1 pin 12, and a switching instruction QHOUT1+ is output; pins 11 and 12 of the chip D2 are connected with pull-up resistors R1 and R2, the pull-down resistor R2 is grounded, and the pull-up resistor R1 is connected with a 3.3V power supply; pin 12 of chip D2 receives input switching command QHIN2 +; pin 11 of chip D2 receives input of a switch command QHIN 2-.
Including 7 internal signals (1-7) and 4 external signals (8-11). The internal signal is a control and state signal between the switching command interface circuit and the control circuit, and the external signal is a switching command signal between the steering engine controllers. The input and output signals of the switching command interface circuit are defined as shown in table 1.
TABLE 1 switching Command interface Circuit Signal definition
The circuit signal connection relation is as follows:
③ the pin D1 and the pin 5 of the chip D2 are connected to the switching instruction 1 to send a signal QHOUT1, and the pins 9 and 10 are connected to the switching instruction 1 to output a signal QHOUT1 +/-. The handoff instruction 1 sending signal QHOUT1 may be a processor software handoff instruction or a failover instruction given by a processor fault detection circuit.
The MAX3491 chip is used for transmitting RS-485/422 bus serial data, and the circuit is only used for receiving and transmitting a switching instruction of 1 data bit. The chip is responsible for converting the cutter cutting instruction output by the control circuit into a differential switching instruction and sending the differential switching instruction out; and simultaneously, converting the received differential switching instruction into a TTL level and outputting the TTL level to the control circuit. Switch command 2 input signal QHIN2 +/-employs an up-pull down resistor to ensure that the switch command initial state is "0".
The switching instruction 1 signal QHOUT1 is connected to the chips D1 and D2 at the same time, and redundant output of the switching instruction 1 can be realized by controlling the transmission enable pins 4 of the chips D1 and D2. The differential output and input ends of the chip D1 adopt a loop test connection mode (pins 9 and 12 are interconnected, pins 10 and 11 are interconnected), and the read-back of the switching instruction 1 can be realized. The above two measures can ensure that the switching instruction can be reliably sent out.
The MAX3491 chip is used for transmitting signals with long distance reaching kilometers; the differential signal has the advantage of strong anti-interference capability, and the reliability of switching instruction transmission can be ensured.
Self-test configuration
After the steering engine controller is powered on and reset, the processor software performs self-checking on the switching instruction interface circuit to ensure that the MAX3491 chip is normal in function.
Firstly, setting signals of/REN 1, TEN1,/REN 2 and TEN2 as '0' by software, and opening receiving functions of the chips D1 and D2; then read the QHIN2 signal, the normal value should be "0"; setting signals TEN1 and QHOUT1 as '1', opening the sending function of the chip D1, delaying for 10us, reading a signal QHIN1 as '1', setting a signal QHOUT1 as '0', delaying for 10us, reading a signal QHIN1 as '0', indicating that the chip D1 is normal in function; then setting a signal TEN1 to be 0, setting signals TEN2 and QHOUT1 to be 1, opening the sending function of the chip D2, delaying for 10us, reading a signal QHIN1 to be 1, setting a signal QHOUT1 to be 0, delaying for 10us, reading a signal QHIN1 to be 0, and indicating that the chip D2 is normal in function; finally, the TEN1 signal is set to "1", the TEN2 and QHOUT1 signals are set to "0", the send function of D1 is turned on, and the switch command 1 output signal QHOUT1 is set to a non-switching state.
Handover configuration
During the working period of the steering engine controller, if the controller receives a software switching instruction issued by a bus or the processor detects a main channel fault, the processor switches the main channel and the standby channel through the software switching instruction; if the processor fails, the fault detection circuit sets the CPU fault switching signal to be effective, and the switching of the main channel and the standby channel is automatically realized.
And during the working period of the steering engine controller, if the processor receives a switching instruction, starting the steering engine of the standby channel to work.
Software switching main and standby channel flow
Setting a QHOUT1 signal to be 1 by software, delaying for 10us, reading a QHIN1 signal, if the signal is 1, indicating that the switching instruction 1 is sent normally, and ending the switching; otherwise, setting 1, delaying, continuously reading for three times, if the QHIN1 signal is 1, sending a switching instruction 1 normally, and ending the switching; otherwise, the chip D1 fails to send a function, and the chip D2 sends a switching instruction 1.
Setting a TEN1 signal to be 0 by software, setting TEN2 and QHOUT1 signals to be 1, delaying for 10us, reading a QHIN1 signal, if the signal is 1, indicating that the switching instruction 1 is sent normally, and ending the switching; otherwise, setting 1, delaying, continuously reading for three times, if the QHIN1 signal is 1, sending a switching instruction 1 normally, and ending the switching; otherwise, the sending function of the chip D2 is also disabled, and the switching operation is ended.
Second, prepare channel starting working process
And periodically detecting the state of the QHIN2 signal by software, and if the QHIN2 signal is read to be 1 after 3 continuous 10us, indicating that the signal QHIN2 of the switching command 2 is in a switching state, starting the steering engine of the standby channel to work.
The method solves the problems that in the prior art, a steering engine switching instruction sending interface circuit adopts a relay to output switching value as a switching instruction output signal, and a switching instruction receiving interface circuit adopts an optical coupler to receive a switching instruction input signal, so that the steering engine switching instruction sending interface circuit is large in size, influenced by temperature and cable length, poor in instruction signal stability, and prone to error switching of main and standby channels, can achieve the functions of main channel software switching, sending of fault switching instruction signals and receiving of standby channel switching instruction signals, and meets the requirements of reliability and universality of a dual-redundancy steering engine switching instruction interface circuit.
The present invention is not limited to the above-mentioned embodiments, and based on the technical solutions disclosed in the present invention, those skilled in the art can make some substitutions and modifications to some technical features without creative efforts according to the disclosed technical contents, and these substitutions and modifications are all within the protection scope of the present invention.
Claims (10)
1. A dual-redundancy steering engine switching instruction interface circuit is characterized by comprising two chips D1 and D2, wherein instruction 1 and 2 control signal pins 2-5 and differential signal pins 9-12 are respectively arranged on the two chips;
pins 10 of the chips D1 and D2 are connected in parallel and are connected with a pin 11 of a chip D1, and a switching instruction QHOUT1 & lt- & gt is output;
pins 9 of the chips D1 and D2 are connected in parallel and are connected with a pin 12 of the chip D1, and a switching instruction QHOUT1+ is output;
pins 11 and 12 of the chip D2 are connected with pull-up resistors R1 and R2; pin 12 of chip D2 receives input switching command QHIN2 +; pin 11 of chip D2 receives input switching instruction QHIN 2-;
the output switching instruction QHOUT1 of the 1# steering engine controller is +/-connected with the input switching instruction QHIN2 +/-of the 2# steering engine controller, and the output switching instruction QHOUT1 of the 2# steering engine controller is +/-connected with the input switching instruction QHIN2 +/-of the 1# steering engine controller.
2. The dual-redundancy steering engine switching instruction interface circuit according to claim 1, wherein pins 5 of D1 and D2 of the chip are connected in parallel with a CMOS device, and the CMOS device is respectively connected with a CPU fault switching end and a software switching end.
3. The dual-redundancy steering engine switching command interface circuit according to claim 1, wherein pins 6 and 7 of the D1 and D2 of the chip are grounded respectively, and pins 14 of the D1 and D2 of the chip are connected to a 3.3V power supply respectively.
4. The dual-redundancy steering engine switching instruction interface circuit according to claim 1, wherein pins 2, 3, 4, 12 and 11 of the chip D1 are respectively connected with a switching instruction 1 receiving signal QHIN1, a switching instruction 1 receiving enable signal/REN 1, a switching instruction 1 sending enable signal TEN1, and a switching instruction 1 outputting signal QHOUT1 +/-.
5. The dual-redundancy steering engine switching command interface circuit according to claim 1, wherein pins 2, 3, 4, 12 and 11 of the chip D2 are respectively connected with a switching command 2 to receive a signal QHIN2, the switching command 2 to receive an enable signal/REN 2, the switching command 1 to send an enable signal TEN2, and the switching command 2 to input a signal QHIN2 +/-.
6. The dual-redundancy steering engine switching command interface circuit as claimed in claim 1, wherein pins D1 and D2 of the chip are connected to the switching command 1 to send a signal QHOUT1, and pins 9 and 10 are connected to the switching command 1 to output a signal QHOUT1 +/-.
7. The dual-redundancy steering engine switching instruction interface circuit according to claim 1, wherein the switching instruction 1 sending signal QHOUT1 is a processor software switching instruction or a fault switching instruction given by a processor fault detection circuit.
8. The dual-redundancy steering engine switching command interface circuit according to claim 1, wherein a pull-down resistor R2 is grounded, and a pull-up resistor R1 is connected to a 3.3V power supply.
9. A method for switching commands by using the dual-redundancy steering engine switching command interface circuit according to any one of claims 1 to 8, comprising the following steps:
firstly, setting signals of/REN 1, TEN1,/REN 2 and TEN2 as '0', and opening the receiving functions of the chips D1 and D2; then read the QHIN2 signal, the normal value should be "0";
setting signals TEN1 and QHOUT1 as '1'; the send function of chip D1 is turned on, delayed by 10us, and the read QHIN1 signal should be "1"; setting the QHOUT1 signal to be '0', delaying for 10us, and reading the QHIN1 signal to be '0', which indicates that the chip D1 is normal in function;
setting the signal TEN1 to be 0, setting the signals TEN2 and QHOUT1 to be 1, opening the sending function of the chip D2, delaying for 10us, and reading the signal QHIN1 to be 1; setting the QHOUT1 signal to be '0', delaying for 10us, and reading the QHIN1 signal to be '0', which indicates that the chip D2 is normal in function;
the TEN1 signal is set to "1", the TEN2 and QHOUT1 signals are set to "0", the transmit function of the chip D1 is turned on, and the switch command 1 output signal QHOUT1 is set to a non-switching state.
10. A method for switching commands by using the dual-redundancy steering engine switching command interface circuit according to any one of claims 1 to 8, comprising the following steps:
A. software switching main/standby channel flow
Setting a QHOUT1 signal to be 1 by software, delaying for 10us, reading a QHIN1 signal, if the signal is 1, indicating that the switching instruction 1 is sent normally, and ending the switching; otherwise, setting 1, delaying, continuously reading for three times, if the QHIN1 signal is 1, sending a switching instruction 1 normally, and ending the switching; otherwise, the chip D1 sends out a failure function, and the chip D2 is used for sending a switching instruction 1;
setting a TEN1 signal to be 0 by software, setting TEN2 and QHOUT1 signals to be 1, delaying for 10us, reading a QHIN1 signal, if the signal is 1, indicating that the switching instruction 1 is sent normally, and ending the switching; otherwise, setting 1, delaying, continuously reading for three times, if the QHIN1 signal is 1, sending a switching instruction 1 normally, and ending the switching; otherwise, the sending function of the chip D2 is also failed, and the switching operation is finished;
B. backup channel start workflow
And periodically detecting the state of the QHIN2 signal by software, and if the QHIN2 signal is read to be 1 after 3 continuous 10us, indicating that the signal QHIN2 of the switching command 2 is in a switching state, starting the steering engine of the standby channel to work.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111210628.0A CN113885391B (en) | 2021-10-18 | 2021-10-18 | Dual-redundancy steering engine switching instruction interface circuit and instruction switching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111210628.0A CN113885391B (en) | 2021-10-18 | 2021-10-18 | Dual-redundancy steering engine switching instruction interface circuit and instruction switching method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113885391A true CN113885391A (en) | 2022-01-04 |
| CN113885391B CN113885391B (en) | 2023-05-16 |
Family
ID=79003401
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111210628.0A Active CN113885391B (en) | 2021-10-18 | 2021-10-18 | Dual-redundancy steering engine switching instruction interface circuit and instruction switching method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113885391B (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011204266A (en) * | 2011-06-10 | 2011-10-13 | Fujitsu Ltd | Method of managing redundancy of basic input/output program, and data processing device |
| EP2506101A2 (en) * | 2011-03-29 | 2012-10-03 | General Electric Company | Hart channel interface component including redundancy |
| CN102759891A (en) * | 2012-06-07 | 2012-10-31 | 中国航天科技集团公司第九研究院第七七一研究所 | Hard handover dual-redundancy CAN controller |
| CN104697593A (en) * | 2015-03-24 | 2015-06-10 | 合肥工业大学 | Ultrasonic gas flowmeter on basis of FPGA (field programmable gate array) and DSP (digital signal processor) |
| EP3054385A1 (en) * | 2015-02-09 | 2016-08-10 | Bedrock Automation Platforms Inc. | Input/output module with multi-channel switching capability |
| CN205620746U (en) * | 2016-05-09 | 2016-10-05 | 国网宁夏电力公司检修公司 | Accurate intelligent control device of transformer cooler based on AD sampling |
| US20170170714A1 (en) * | 2015-12-15 | 2017-06-15 | Monolithic Power Systems, Inc. | Multi-phase voltage converter with fault instruction circuit |
| CN107526289A (en) * | 2016-06-21 | 2017-12-29 | 李福霞 | A kind of two redundancy actuator control systems based on CAN |
| CN210294832U (en) * | 2019-06-26 | 2020-04-10 | 中国航天空气动力技术研究院 | Dual-redundancy CAN bus communication device suitable for autonomous underwater vehicle |
| CN111399416A (en) * | 2020-03-26 | 2020-07-10 | 西安微电子技术研究所 | Double-shaft steering engine controller based on MCU processor |
| CN112182876A (en) * | 2020-09-25 | 2021-01-05 | 西安微电子技术研究所 | Dual-redundancy steering engine channel fault switching system and logic design method |
| CN113447891A (en) * | 2021-04-28 | 2021-09-28 | 中国电子科技集团公司第十四研究所 | Satellite-borne radar exchange interface module |
-
2021
- 2021-10-18 CN CN202111210628.0A patent/CN113885391B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2506101A2 (en) * | 2011-03-29 | 2012-10-03 | General Electric Company | Hart channel interface component including redundancy |
| JP2011204266A (en) * | 2011-06-10 | 2011-10-13 | Fujitsu Ltd | Method of managing redundancy of basic input/output program, and data processing device |
| CN102759891A (en) * | 2012-06-07 | 2012-10-31 | 中国航天科技集团公司第九研究院第七七一研究所 | Hard handover dual-redundancy CAN controller |
| EP3054385A1 (en) * | 2015-02-09 | 2016-08-10 | Bedrock Automation Platforms Inc. | Input/output module with multi-channel switching capability |
| CN104697593A (en) * | 2015-03-24 | 2015-06-10 | 合肥工业大学 | Ultrasonic gas flowmeter on basis of FPGA (field programmable gate array) and DSP (digital signal processor) |
| US20170170714A1 (en) * | 2015-12-15 | 2017-06-15 | Monolithic Power Systems, Inc. | Multi-phase voltage converter with fault instruction circuit |
| CN205620746U (en) * | 2016-05-09 | 2016-10-05 | 国网宁夏电力公司检修公司 | Accurate intelligent control device of transformer cooler based on AD sampling |
| CN107526289A (en) * | 2016-06-21 | 2017-12-29 | 李福霞 | A kind of two redundancy actuator control systems based on CAN |
| CN210294832U (en) * | 2019-06-26 | 2020-04-10 | 中国航天空气动力技术研究院 | Dual-redundancy CAN bus communication device suitable for autonomous underwater vehicle |
| CN111399416A (en) * | 2020-03-26 | 2020-07-10 | 西安微电子技术研究所 | Double-shaft steering engine controller based on MCU processor |
| CN112182876A (en) * | 2020-09-25 | 2021-01-05 | 西安微电子技术研究所 | Dual-redundancy steering engine channel fault switching system and logic design method |
| CN113447891A (en) * | 2021-04-28 | 2021-09-28 | 中国电子科技集团公司第十四研究所 | Satellite-borne radar exchange interface module |
Non-Patent Citations (3)
| Title |
|---|
| 王晴 等: "一种多通道双余度舵机控制系统设计", 《中国航天电子技术研究院科学技术委员会2020年学术年会优秀论文集》 * |
| 茹毅;毛征;刘松松;罗子安;孟灿;: "基于3片C8051F020仲裁热备份舵机控制系统硬件设计", 《国外电子测量技术》 * |
| 黄健;王强;: "基于FPGA的双余度无刷舵机控制系统的设计", 《微电机》 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113885391B (en) | 2023-05-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107995079B (en) | Hot standby vehicle-mounted ATP (automatic train protection) equipment based on MVB (multifunction vehicle bus) | |
| CN101271332B (en) | Compact integrated redundancy controller and control method thereof | |
| CN100492223C (en) | Switch circuit for engine redundant electrically-controlled system | |
| CN107942820B (en) | High-reliability analog quantity redundant output device and method | |
| JP2754922B2 (en) | Transmission system and transmission method | |
| JP2023539613A (en) | Functionally safe switch quantity output module and diagnostic processing method | |
| CN110932645A (en) | High-voltage frequency converter dual-control machine redundancy topology structure and control method | |
| CN101741532B (en) | Two-computer switching device for redundant server switching | |
| CN112182876A (en) | Dual-redundancy steering engine channel fault switching system and logic design method | |
| CN113885391A (en) | Dual-redundancy steering engine switching instruction interface circuit and instruction switching method | |
| US5140691A (en) | Adapter-bus switch for improving the availability of a control unit | |
| CN109306875A (en) | A kind of synchronous hot backup redundancy switching device of steam turbine DEH dual controller and method | |
| CN110727220B (en) | Master-slave dual-redundancy FPGA switching control circuit | |
| CN101430550B (en) | Switch control method of engine redundancy electric-control system | |
| CN111915869B (en) | High-reliability RS422 serial port communication circuit device | |
| WO2021170047A1 (en) | Electric motor control system and vehicle | |
| CN115113516A (en) | Master-slave redundancy control system and control method | |
| CN111463895B (en) | Display system for realizing double-core double-channel control of single liquid crystal screen | |
| JPH06175868A (en) | Duplex computer fault monitoring method | |
| CN216014243U (en) | Dual-core peripheral digital interface switching system | |
| US20030076557A1 (en) | Fault tolerant optical switch architecture | |
| KR20010038483A (en) | Apparatus for error recovery the Inter Processor Communication path in the ATM switching system | |
| CN103457879A (en) | Method for master-slave election of management module, management module and modularized equipment | |
| JPH0622020B2 (en) | Peripheral bus controller in redundant information processing system | |
| JP3125864B2 (en) | Redundant system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |