CN113840454A - Printed circuit board and QSFP-DD high-speed cable assembly - Google Patents

Printed circuit board and QSFP-DD high-speed cable assembly Download PDF

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Publication number
CN113840454A
CN113840454A CN202111428595.7A CN202111428595A CN113840454A CN 113840454 A CN113840454 A CN 113840454A CN 202111428595 A CN202111428595 A CN 202111428595A CN 113840454 A CN113840454 A CN 113840454A
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China
Prior art keywords
row
layer
wires
circuit board
bonding pads
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Granted
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CN202111428595.7A
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Chinese (zh)
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CN113840454B (en
Inventor
彭新星
张雪亮
卢玉华
沈诗明
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Pengyuansheng High Tech Co Ltd
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Pengyuansheng High Tech Co Ltd
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Priority to CN202111428595.7A priority Critical patent/CN113840454B/en
Publication of CN113840454A publication Critical patent/CN113840454A/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
    • H01R13/6461—Means for preventing cross-talk
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/646—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00 specially adapted for high-frequency, e.g. structures providing an impedance match or phase match
    • H01R13/6461—Means for preventing cross-talk
    • H01R13/6463—Means for preventing cross-talk using twisted pairs of wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R13/00—Details of coupling devices of the kinds covered by groups H01R12/70 or H01R24/00 - H01R33/00
    • H01R13/66—Structural association with built-in electrical component
    • H01R13/665—Structural association with built-in electrical component with built-in electronic circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R9/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, e.g. terminal strips or terminal blocks; Terminals or binding posts mounted upon a base or in a case; Bases therefor
    • H01R9/11—End pieces for multiconductor cables supported by the cable and for facilitating connections to other conductive members, e.g. for liquid cooled welding cables

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

The invention discloses a QSFP-DD high-speed cable, which comprises a circuit board body, an upper-layer bonding pad arranged on the upper layer surface of the circuit board body and a lower-layer bonding pad arranged on the lower layer surface of the circuit board body, wherein the upper-layer bonding pad comprises a first row of upper-layer bonding pads, a second row of upper-layer bonding pads and a third row of upper-layer bonding pads which are distributed in sequence, the upper-layer bonding pads respectively and correspondingly comprise two groups of butt-joint bonding pads, three groups of butt-joint bonding pads and four groups of butt-joint bonding pads, and the first row of upper-layer bonding pads, the second row of upper-layer bonding pads and the third row of upper-layer bonding pads are distributed in a staggered manner; the lower-layer bonding pads comprise a first row of lower-layer bonding pads and a second row of lower-layer bonding pads which are distributed in sequence, the first row of lower-layer bonding pads and the second row of lower-layer bonding pads correspondingly comprise three groups of butt-joint bonding pads and four groups of butt-joint bonding pads respectively, and the first row of lower-layer bonding pads and the second row of lower-layer bonding pads are distributed in a staggered mode; and four sets of docking pads of the second row of lower pads are adjacent or abut the rear edge of the lower surface.

Description

Printed circuit board and QSFP-DD high-speed cable assembly
Technical Field
The invention relates to the technical field of printed circuit boards, in particular to a printed circuit board suitable for connecting a QSFP-DD high-speed cable and a QSFP-DD high-speed cable assembly.
Background
Printed Circuit Boards (PCBs) are important electronic components, support bodies of electronic components, and carriers for electrical connection of electronic components, and with continuous progress and increased demand of modern information processing technologies and increasing popularization of technologies such as big data, cloud computing, internet of things and the like, demands for ultra-high-speed and large-broadband communication products are stronger, and the rational optimization of differential signal integrity in the field of high-speed PCB design becomes a key to success of current system design.
The QSFP-DD (Quad Small Form-factor plug-Double Small plug) package is a package of a high-speed plug-pull module, and is the first choice of 400G optical module packages, so that the data center can effectively increase and expand the cloud capacity as required. QSFP-DD packages increase the number of lanes to eight, up to 25Gbps per lane operating rate by NRZ modulation or 50Gbps per lane operating rate by PAM4 modulation, thereby supporting 200Gbps or 400 Gbps.
In QSFP-DD, QSFP-DD high speed cables are typically soldered to a printed circuit board and then connected to a housing of a QSFP-DD connector. The QSFP-DD high speed cable includes 16 conductors (each conductor including a pair of signal lines) to form eight lanes.
The inventor finds that the prior art has at least the following problems in the process of implementing the invention:
16 wires in the existing QSFP-DD high-speed cable are symmetrically distributed in parallel in 4 rows, and in order to realize welding of a printed circuit board connected with the QSFP-DD high-speed cable, the currently adopted pad arrangement structure mainly comprises the following two modes:
the first method is as follows: 8 groups of connection pads are respectively arranged on the upper layer surface and the lower layer surface of the printed circuit board and are respectively correspondingly connected with 8 wires, and the 8 groups of connection pads on the upper layer surface and the lower layer surface are respectively distributed in 2 rows which are symmetrical front and back, so that the 2 rows of wires connected to the upper layer surface/the lower layer surface are stacked in the 4 wires on the lower row, and thus, a vertically symmetrical double-layer wire stacking structure is formed on the upper layer surface and the lower layer surface of the printed circuit board. However, the QSFP-DD connector has a feature of high density and small space, and the internal space of the connector connected to the QSFP-DD high-speed cable is insufficient, and particularly, the height of the lower layer space (specifically, the height of the space formed between the lower layer surface of the printed circuit board and the inner surface of the connector housing after the printed circuit board connected to the QSFP-DD high-speed cable is inserted into the connector) is low. The double-layer wire stacking structure formed on the lower surface of the printed circuit board is higher (not lower than the sum of the heights of two wires), so that the lower space inside the connector cannot accommodate wires with larger diameters.
The second method comprises the following steps: all 8 pairs of the pair of the group of the bonding pads on the lower layer surface of the printed circuit board in the first mode are arranged on the upper layer surface of the printed circuit board, namely 16 pairs of the group of the bonding pads are arranged on the upper layer surface of the printed circuit board, and 4 rows of the wires which are symmetrically arranged in parallel are correspondingly connected in a front-back symmetrical mode. The problem caused by the low height of the lower layer space inside the connector in the first mode can be solved by adopting the second mode, but the problem of front-back crosstalk generated between signal lines connected with the front row and the rear row is caused by the fact that all the bonding pads are distributed on the upper layer surface of the printed circuit board and the front row and the rear row are densely distributed, and the influence on the high-frequency performance of signal transmission is large.
Disclosure of Invention
An object of the present invention is to provide a printed circuit board and a QSFP-DD high-speed cable assembly which can effectively solve the above-mentioned technical problems occurring in the prior art.
In order to achieve the above object, an embodiment of the present invention provides a printed circuit board, which is suitable for connecting a QSFP-DD high-speed cable, and includes a circuit board body, an upper pad disposed on an upper surface of the circuit board body, and a lower pad disposed on a lower surface of the circuit board body, where the upper pad is used to connect nine wires in the QSFP-DD high-speed cable, and the lower pad is used to connect the remaining seven wires in the QSFP-DD high-speed cable; each conducting wire comprises two signal wires and two grounding wires, and the transverse section of each conducting wire is hexagonal;
the upper-layer bonding pads comprise a first row of upper-layer bonding pads, a second row of upper-layer bonding pads and a third row of upper-layer bonding pads, wherein the first row of upper-layer bonding pads, the second row of upper-layer bonding pads and the third row of upper-layer bonding pads are sequentially distributed from the front edge to the back edge of the upper surface of the circuit board body; the lower-layer bonding pads comprise a first row of lower-layer bonding pads and a second row of lower-layer bonding pads which are sequentially distributed from the front edge to the back edge of the lower-layer surface of the circuit board body, the first row of lower-layer bonding pads comprise three groups of butt-joint bonding pads, the second row of lower-layer bonding pads comprise four groups of butt-joint bonding pads, the first row of lower-layer bonding pads and the second row of lower-layer bonding pads are distributed in a staggered mode, and the four groups of butt-joint bonding pads of the second row of lower-layer bonding pads are close to the back edge of the lower-layer surface or are adjacent to the back edge of the lower-layer surface; each group of the butt joint bonding pads is correspondingly connected with one wire;
when the QSFP-DD high-speed cable is connected with the printed circuit board, in the QSFP-DD high-speed cable, a second row of upper-layer wires correspondingly connected with a second row of upper-layer bonding pads respectively span between two adjacent wires in a third row of upper-layer wires correspondingly connected with a third row of upper-layer bonding pads, and the left lower side surface and the right lower side surface of each wire in the second row of upper-layer wires are correspondingly attached to the right upper side surface and the left upper side surface of two adjacent wires in the third row of upper-layer wires respectively; the first row of upper-layer wires correspondingly connected with the first row of upper-layer bonding pads respectively span between two adjacent wires or two sides of the second row of upper-layer wires, and the left lower side surface and/or the right lower side surface of each wire in the first row of upper-layer wires are correspondingly attached to the right upper side surface and/or the left upper side surface of the adjacent wire in the second row of upper-layer wires; with first row lower floor's wire that first row lower floor's pad corresponds the connection stride respectively with the second row lower floor's pad corresponds between two adjacent wires in the second row lower floor's wire of connecting, just the upper left side surface, the upper right side surface of every wire in the first row lower floor's wire correspond the laminating with the lower right side surface, the lower left side surface of two adjacent wires in the second row lower floor's wire respectively.
Preferably, the width of the upper left surface, the upper right surface, the lower left surface and the lower right surface of each conducting wire is the same, and the width of the upper surface and the lower surface of each conducting wire is the same and is greater than or equal to the width of the upper left surface, the upper right surface, the lower left surface and the lower right surface;
the distance between two adjacent wires in the third row of upper wires is consistent with the width of the upper surface/lower surface of each wire, so that the left lower side surface and the right lower side surface of each wire in the second row of upper wires are completely attached to the right upper side surface and the left upper side surface of two adjacent wires in the third row of upper wires, and the left lower side surface and/or the right lower side surface of each wire in the first row of upper wires are completely attached to the right upper side surface and/or the left upper side surface of the adjacent wire in the second row of upper wires;
the distance between two adjacent wires in the second row of lower layer wires is consistent with each width of the upper surface/lower surface of the wires, so that the upper left side surface and the upper right side surface of each wire in the first row of lower layer wires are completely attached to the lower right side surface and the lower left side surface of two adjacent wires in the second row of lower layer wires.
Preferably, in a transverse cross section of each of the conductive wires, an inner angle formed by the upper left side, the upper right side and the upper side, and an inner angle formed by the lower left side, the lower right side and the lower side are R1, and satisfy: r1 is more than 120 degrees and less than or equal to 150 degrees; the interior angle that upper left side and lower left side constitute and the interior angle that upper right side and lower right side constitute are R2, and satisfy: 60 DEG-R2 < 120 DEG, so that the transverse section of each wire is in a flat hexagon shape.
Preferably, R1 further satisfies: 135 DEG-R1-150 DEG, said R2 further satisfying: r2 is more than or equal to 60 degrees and less than or equal to 90 degrees.
Preferably, the third row of upper layer pads is located on the upper surface of the circuit board body opposite to the first row of lower layer pads.
Preferably, distances between four sets of butt-joint bonding pads of the third row of upper bonding pads and the rear edge of the upper surface are greater than lengths of signal lines and grounding lines exposed out of the third row of upper leads correspondingly connected with the third row of upper bonding pads and used for realizing welding.
Preferably, the upper layer bonding pad is located in a rear area, close to the rear edge, of the surface of the upper layer, an upper layer golden finger is arranged in a front area, close to the front edge, of the surface of the upper layer, and the upper layer golden finger is correspondingly connected with the upper layer bonding pad; the lower-layer bonding pad is positioned in a rear area, close to the rear edge, of the lower-layer surface, a front area, close to the front edge, of the lower-layer surface is provided with a lower-layer golden finger, and the lower-layer golden finger is correspondingly connected with the lower-layer bonding pad.
Preferably, each group of the butt-joint bonding pads comprises four bonding pads, and two signal wires and two grounding wires which are respectively correspondingly connected with each conducting wire; the two signal lines of each wire are correspondingly connected with the middle two bonding pads in each group of the butt-joint bonding pads, and the two grounding lines of each wire are correspondingly connected with the two side bonding pads in each group of the butt-joint bonding pads, so that the butt-joint bonding pads in each group form grounding-signal-grounding arrangement from left to right or from right to left on a printed circuit board, and the rows on the upper layer surface/the lower layer surface of the circuit board body form grounding-signal staggered arrangement.
Preferably, the thickness of each conducting wire is the same as that of the printed circuit board.
Another embodiment of the present invention further provides a QSFP-DD high-speed cable assembly, which includes the printed circuit board according to any of the above embodiments and a QSFP-DD high-speed cable correspondingly connected to the printed circuit board.
Compared with the prior art, the printed circuit board and QSFP-DD high-speed cable assembly provided by the embodiment of the invention have the following technical effects: through improving the scheme of respectively arranging eight pairs of butt-joint pads on the upper layer surface and the lower layer surface of the prior art, nine pairs of butt-joint pads are arranged on the upper layer surface of the printed circuit board to be connected with nine wires in the QSFP-DD high-speed cable, seven pairs of butt-joint pads are arranged on the lower layer surface of the printed circuit board to be connected with the rest seven wires in the QSFP-DD high-speed cable, three rows of the nine pairs of butt-joint pads arranged on the upper layer surface are sequentially distributed from the front edge to the rear edge of the upper layer surface of the circuit board body and correspondingly distributed into two groups, three groups and four groups of butt-joint pads, the three rows of butt-joint pads are distributed in a staggered way, meanwhile, two rows of the seven pairs of butt-joint pads arranged on the lower layer surface are sequentially distributed from the front edge to the rear edge of the lower layer surface of the circuit board body and correspondingly distributed into three groups and four groups of butt-joint pads, and the two rows of butt-joint pads are distributed in a staggered way, so that when the QSFP-DD high-speed cable is connected with the printed circuit board, the 9 wires that correspond the connection with the nine sets of joint pads on upper layer surface are three rows (correspond to 2, 3 and 4) and crisscross the piling up and arrange from the top down on the upper layer surface of printed circuit board, and the 7 wires that correspond the connection with the seven sets of joint pads on lower floor surface are two rows (correspond to 3 and 4) and are crisscross the piling up and arrange from the bottom up on the upper layer surface of printed circuit board. Therefore, the arrangement structure of all the wires in the QSFP-DD high-speed cable connected to the printed circuit board can be firmer, the total height (lower than the sum of the heights of the two wires) of the stacked wires connected to the lower surface of the printed circuit board can be effectively reduced, and the technical problem caused by the low height of the lower space inside the connector in the prior art can be effectively solved. In addition, the last row of butt-joint welding pads positioned on the surface of the lower layer is close to the back of the surface of the lower layer or is adjacent to the back of the surface of the lower layer, and the last row of butt-joint welding pads positioned on the surface of the upper layer is not close to the back of the surface of the upper layer, so that the thickness of the board body of the printed circuit board can be effectively utilized to place the leads connected with the last row of butt-joint welding pads on the surface of the lower layer, the total height of the stacked leads connected to the surface of the lower layer of the printed circuit board is further reduced, and the problem of up-and-down crosstalk between signal wires connected with the welding pads on the surface of the upper layer and the lower layer of the printed circuit board can be effectively avoided.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a QSFP-DD high-speed cable assembly according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of another angle of a QSFP-DD high-speed cable assembly according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a printed circuit board according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of another angle of a printed circuit board according to an embodiment of the present invention.
Fig. 5 is a top view of a printed circuit board showing a pad structure on an upper surface of the printed circuit board according to an embodiment of the present invention.
Fig. 6 is a partially enlarged view shown by an arrow a in fig. 5, showing the structure of a set of landing pads.
Fig. 7 is a bottom view of a printed circuit board showing a pad structure on a lower surface of the printed circuit board, in accordance with an embodiment of the present invention.
Fig. 8 is a partial top view of a printed circuit board after being connected to a QSFP-DD high-speed cable according to an embodiment of the present invention, showing a connection structure of a pad structure and a conductive wire on an upper surface of the printed circuit board.
Fig. 9 is a partial bottom view of a printed circuit board after being connected to a QSFP-DD high-speed cable according to an embodiment of the present invention, showing a connection structure of a pad structure and a conductive wire on a lower surface of the printed circuit board.
FIG. 10 is a partial side view of a printed circuit board after connection to a QSFP-DD high-speed cable according to an embodiment of the present invention, showing the connection structure of the land structures and the wires on the upper and lower surfaces of the printed circuit board.
Fig. 11 is a partially enlarged view shown by an arrow B in fig. 10.
Fig. 12 is a cross-sectional view of a QSFP-DD high-speed cable according to an embodiment of the present invention.
Fig. 13 is a cross-sectional view of each conductor of a QSFP-DD high-speed cable according to an embodiment of the present invention.
Fig. 14 shows a stacked arrangement of 16 wires of the QSFP-DD high speed cable of fig. 12.
Fig. 15 is a schematic structural diagram of a QSFP-DD high-speed cable assembly according to an embodiment of the present invention after being connected to a QSFP-DD connector.
Fig. 16 is a sectional view of a QSFP-DD high-speed cable assembly according to an embodiment of the present invention after being connected to a QSFP-DD connector.
The attached drawings indicate the following:
100. a QSFP-DD high-speed cable assembly;
1. a printed circuit board; 11. a circuit board body; 111. the upper layer surface; 1111. the front side of the upper layer surface; 1112. behind the upper surface; 112. a lower layer surface; 1121. the front side of the lower layer surface; 1122. behind the surface of the lower layer;
12. an upper layer pad; 121. a first row of upper layer pads; 122. a second row of upper layer pads; 123. a third row of upper layer pads;
13. a lower layer pad; 131. a first row of lower layer pads; 132. a second row of lower layer pads;
14. an upper layer of golden fingers;
15. a lower layer of golden fingers;
120. butting the bonding pads;
2. QSFP-DD high-speed cable, 21 conducting wire, 22 fixing layer, 23 shielding layer; 24. a cable cover;
211. a signal line; 212. a ground wire; 213. a first insulating layer; 214. a second insulating layer; 215. a double-layer shielding tape;
2101. a left upper side surface; 2102. an upper right side surface; 2103. a left underside surface; 2104. a right underside surface; 2105. an upper surface; 2106. a lower surface;
201. a first row of upper conductors; 202. a second row of upper conductors; 203. a third row of upper conductors; 204. a second row of lower conductors; 205. a first row of lower conductors;
a QSFP-DD connector; 301. a housing.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically connected, electrically connected or can communicate with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Referring to fig. 1 to 2, an embodiment of the invention provides a QSFP-DD high-speed cable assembly 100, where the QSFP-DD high-speed cable assembly 100 includes a printed circuit board 1 and a QSFP-DD high-speed cable 2 correspondingly connected to the printed circuit board 1. Wherein the QSFP-DD high speed cable 2 comprises sixteen wires, sixteen sets of pads are provided on the surface of the printed circuit board 1 to enable connection (e.g., soldering) with the sixteen wires of the QSFP-DD high speed cable 2, nine sets of pads are provided on the upper surface of the printed circuit board 1 to connect the nine wires in the QSFP-DD high speed cable 2, and seven sets of pads are provided on the lower surface of the printed circuit board 1 to connect the remaining seven wires in the QSFP-DD high speed cable 2.
The specific structures of the printed circuit board 1 and the QSFP-DD high-speed cable 2 will be described below with reference to the accompanying drawings, so as to describe in detail how the printed circuit board 1 and the QSFP-DD high-speed cable 2 are correspondingly connected.
Referring to fig. 3 to 4, an embodiment of the present invention provides a printed circuit board 1, where the printed circuit board 1 is suitable for connecting a QSFP-DD high-speed cable, the printed circuit board 1 includes a circuit board body 11, an upper pad 12 disposed on an upper surface 111 of the circuit board body 11, and a lower pad 13 disposed on a lower surface 112 of the circuit board body 11, the upper pad 12 is used to connect nine wires in the QSFP-DD high-speed cable, and the lower pad 13 is used to connect the remaining seven wires in the QSFP-DD high-speed cable.
The upper layer bonding pad 12 is located in a rear area of the upper layer surface 111 close to the upper layer surface rear edge 1112, an upper layer golden finger 14 is arranged in a front area of the upper layer surface 111 close to the upper layer surface front edge 1111, and the upper layer golden finger 14 is correspondingly connected with the upper layer bonding pad 12. The lower layer pads 13 are located in the rear region of the lower layer surface 112 close to the lower layer surface rear edge 1122, and the front region of the lower layer surface 112 close to the lower layer surface front edge 1121 is provided with lower layer gold fingers 15, and the lower layer gold fingers 15 are correspondingly connected with the lower layer pads 13.
Referring to fig. 5 and 7, the upper layer lands 12 include a first row of upper layer lands 121, a second row of upper layer lands 122, and a third row of upper layer lands 123 that are sequentially distributed from an upper layer surface front side 1111 to an upper layer surface rear side 1112 of the upper layer surface 111 of the circuit board body 11. The first row of upper bonding pads 121 comprises two groups of butt-joint bonding pads, the second row of upper bonding pads 122 comprises three groups of butt-joint bonding pads, the third row of upper bonding pads 123 comprises four groups of butt-joint bonding pads, and the first row of upper bonding pads 121, the second row of upper bonding pads 122 and the third row of upper bonding pads 123 are distributed in a staggered mode. The lower layer pads 13 include a first row of lower layer pads 131 and a second row of lower layer pads 132 which are distributed in sequence from a lower layer surface front edge 1121 to a lower layer surface rear edge 1122 of the lower layer surface 112 of the circuit board body 11, the first row of lower layer pads 131 includes three sets of butt-joint pads, the second row of lower layer pads 132 includes four sets of butt-joint pads, and the first row of lower layer pads 131 and the second row of lower layer pads 132 are distributed in a staggered manner.
It is understood that, in the present embodiment, in conjunction with fig. 6, each set of the docking pads 120 is connected to one wire of the QSFP-DD high-speed cable. Each group of the docking pads 120 includes four pads arranged in parallel and at the same interval, and the four pads are respectively and correspondingly connected with two signal lines and two ground lines of one conductor in the QSFP-DD high-speed cable. Two middle bonding pads in each group of the bonding pads 120 are correspondingly connected with two signal wires in each wire, and two side bonding pads in each group of the bonding pads 120 are correspondingly connected with two grounding wires of each wire, so that each group of the bonding pads 120 form a grounding bonding pad 120 b-a signal bonding pad 120 a-a grounding bonding pad 120b arrangement from left to right or from right to left on a printed circuit board.
It can be understood that, in the present embodiment, in the upper surface 111 of the circuit board body 11, the staggered distribution among the first row of upper layer pads 121, the second row of upper layer pads 122, and the third row of upper layer pads 123 specifically means: the symmetry line (bilateral symmetry) of each group of the upper-layer pads 122 in the second row coincides with the symmetry line (bilateral symmetry) between two adjacent groups of the upper-layer pads 123 in the third row, and the symmetry line (bilateral symmetry) of each group of the upper-layer pads 121 in the first row coincides with the symmetry line (bilateral symmetry) between two adjacent groups of the upper-layer pads 122 in the second row (or the two groups of the upper-layer pads 121 in the first row may be symmetrically distributed with any two groups of the upper-layer pads 123 in the third row). Correspondingly, the staggered distribution between the first row of lower layer pads 131 and the second row of lower layer pads 132 specifically means: the symmetry line (bilateral symmetry) of each set of landing pads in the first row of lower pads 131 coincides with the symmetry line (bilateral symmetry) between two adjacent sets of landing pads in the second row of lower pads 132.
Preferably, in this embodiment, in three rows of upper pads on the upper surface 111 of the circuit board body 11, a distance L1 between two adjacent sets of the pads in the same row of upper pads is substantially equal to a distance L2 between two adjacent pads in the same set of the pads, so that, in combination with the design that the three rows of upper pads on the upper surface 111 of the circuit board body 11 are distributed in a staggered manner, two adjacent rows of upper pads on the upper surface 111 of the circuit board body 11 form a ground-signal staggered arrangement. That is, a ground connection pad of the second row upper layer pad 122 is distributed behind any one of the first row upper layer pads 121 connected to the signal line, and a ground connection pad of the third row upper layer pad 123 is distributed behind any one of the second row upper layer pads 122 connected to the signal line. Similarly, in the two rows of lower pads on the lower surface 112 of the circuit board body 11, the distance L1 between two adjacent sets of the landing pads in the same row of lower pads is substantially equal to the distance L2 between two adjacent pads in the same pair of landing pads, so that, in combination with the design of staggered distribution between two rows of lower pads on the lower surface 112 of the circuit board body 11, two rows of lower pads on the lower surface 112 of the circuit board body 11 form a ground-signal staggered arrangement. That is, the ground connection pad of the second row lower layer pad 132 is distributed behind any one of the first row lower layer pads 131 connected to the signal line. Due to the arrangement, when the printed circuit board is connected with the QSFP-DD high-speed cable, the signal lines connected with the front row of pads and the rear row of pads can be staggered, so that front-rear crosstalk between the signal lines connected with the front row of pads and the rear row of pads is effectively avoided, and the high-frequency performance of electrical transmission is improved. It will be appreciated that a certain distance is required between two adjacent rows of pads to facilitate bonding between the pads and the wires.
Referring to fig. 5, 8 and 11 in combination, in the present embodiment, four sets of landing pads of the second row of lower pads 132 are close to the lower surface back side 1122 of the lower surface 112, or four sets of landing pads of the second row of lower pads 132 are adjacent to the lower surface back side 1122 of the lower surface 112. Thus, when the wires (corresponding to the second row of lower-layer wires) in the QSFP-DD high-speed cable are soldered to the second row of lower-layer pads 132, after the portions (i.e., soldering terminals or soldering pins) of the signal lines and the ground lines exposed from the second row of lower-layer wires are soldered to the second row of lower-layer pads 132, the entire second row of lower-layer wires can be bent downward and then accommodated in the space parallel to the circuit board body 11 at the rear side of the circuit board body 11, so that the thickness of the board body of the printed circuit board 1 is effectively used to place the second row of lower-layer wires, thereby further reducing the total height of the stacked wires connected to the lower-layer surface 112 of the printed circuit board 1. Preferably, the thickness of the printed circuit board 1 is the same as the thickness of each wire in the connected QSFP-DD high-speed cable.
In addition, in the upper surface 111 of the circuit board body 11, the distance between four sets of butt-joint pads of the third row of upper-layer pads 123 and the rear edge 1112 of the upper surface 111 is greater than the length of the signal lines and the ground lines (i.e., the welding terminals or the welding pins) exposed from the wires (corresponding to the third row of upper-layer wires) in the QSFP-DD high-speed cable correspondingly connected to the third row of upper-layer pads 123 for realizing welding. That is, the third row of lower layer pads 123 in the upper layer surface 111 is not close to the upper layer surface back edge 1112 of the upper layer surface 111, and is spaced from the upper layer surface back edge 1112 of the upper layer surface 111 by a distance that satisfies: the third row of upper layer wires and the third row of upper layer pads 123 can be integrally arranged on the upper layer surface 111 after being welded, so that the problem of vertical crosstalk between the signal lines connected with the third row of lower layer pads 123 on the upper layer surface 111 and the signal lines connected with the second row of lower layer pads 132 on the lower layer surface 112 can be effectively avoided.
Preferably, the third row of upper pads 123 is located on the upper surface 111 of the circuit board body 11 opposite to the first row of lower pads 131 on the lower surface 112 of the circuit board body 11.
Referring to fig. 8 to 11 and fig. 16 in combination, a transverse cross section of each of the wires in the QSFP-DD high-speed cable is hexagonal (preferably, flat hexagonal), when the QSFP-DD high-speed cable 2 is connected to the printed circuit board 1, in the QSFP-DD high-speed cable, the second row upper layer wires 202 connected to the second row upper layer pads 122 respectively straddle between two adjacent wires in the third row upper layer wires 203 connected to the third row upper layer pads 123, and a left lower side surface and a right lower side surface of each of the second row upper layer wires 202 respectively and correspondingly attach to a right upper side surface and a left upper side surface of two adjacent wires in the third row upper layer wires 203. The first row upper layer wires 201 correspondingly connected with the first row upper layer bonding pads 121 respectively span between two adjacent wires or two sides of the second row upper layer wires 202, and the left lower side surface and/or the right lower side surface of each wire in the first row upper layer wires 201 are correspondingly attached to the right upper side surface and/or the left upper side surface of the adjacent wire in the second row upper layer wires 202. The first row lower layer wires 205 correspondingly connected with the first row lower layer pads 131 respectively span between two adjacent wires in the second row lower layer wires 204 correspondingly connected with the second row lower layer pads 132, and the upper left side surface and the upper right side surface of each wire in the first row lower layer wires 205 are correspondingly attached to the lower right side surface and the lower left side surface of two adjacent wires in the second row lower layer wires 204 respectively.
It can be seen that, in the printed circuit board 1 suitable for connecting QSFP-DD high-speed cables provided in this embodiment, by improving the scheme of respectively providing eight pairs of docking pads on the upper and lower layer surfaces in the prior art, nine pairs of docking pads are provided on the upper layer surface of the printed circuit board 1 to connect nine wires in the QSFP-DD high-speed cables, seven pairs of docking pads are provided on the lower layer surface of the printed circuit board 1 to connect the remaining seven wires in the QSFP-DD high-speed cables, and the nine pairs of docking pads provided on the upper layer surface are sequentially distributed in three rows from the front to the rear of the upper layer surface of the circuit board body, corresponding to two, three and four sets of docking pads, and the three rows of docking pads are distributed in a staggered manner, and meanwhile, the seven pairs of docking pads provided on the lower layer surface are sequentially distributed in two rows from the front to the rear of the lower layer surface of the circuit board body, corresponding to three and four sets of docking pads, and the two rows of butt-joint welding pads are distributed in a staggered manner, so that when the QSFP-DD high-speed cable is connected with the printed circuit board 1, 9 wires correspondingly connected with the nine groups of butt-joint welding pads on the upper layer surface are arranged in a staggered manner in three rows (corresponding to 2, 3 and 4 wires) from top to bottom on the upper layer surface of the printed circuit board, and 7 wires correspondingly connected with the seven groups of butt-joint welding pads on the lower layer surface are arranged in a staggered manner in two rows (corresponding to 3 and 4 wires) from bottom to top on the upper layer surface of the printed circuit board. Therefore, the arrangement structure of all the wires in the QSFP-DD high-speed cable connected to the printed circuit board 1 can be firmer, the total height (lower than the sum of the heights of the two wires) of the stacked wires connected to the lower surface 112 of the printed circuit board 1 can be effectively reduced, and the technical problem caused by the low height of the lower space inside the connector in the prior art can be effectively solved. In addition, the last row of the docking pads on the lower surface 112 is close to or adjacent to the lower surface back 1122 of the lower surface 112, and the last row of the docking pads on the upper surface 111 is not close to the upper surface back 1112 of the upper surface 111, so that the thickness of the board body of the printed circuit board can be effectively used for placing the wires connected with the last row of the docking pads on the lower surface 112, thereby further reducing the total height of the stacked wires connected to the lower surface 112 of the printed circuit board 1, and effectively avoiding the problem of vertical crosstalk between the signal wires connected with the pads on the upper and lower surfaces of the printed circuit board 1.
Referring to fig. 12, an embodiment of the present invention provides a QSFP-DD high-speed cable 2, where the QSFP-DD high-speed cable 2 includes sixteen conductors 21, a fixed layer 22 wound around and covering the sixteen conductors 21, a shielding layer 23 covering the fixed layer 22, and a cable jacket 24 covering the shielding layer 23. The sixteen wires 21 are covered and fixed inside the cable through the fixing layer 22, and it can be understood that in order to make the sixteen wires 21 more firm inside the cable, an adhesive layer may be provided inside the fixing layer 22 and between the sixteen wires 21.
As shown in fig. 13, each of the conductive wires 21 includes two signal wires 211, two ground wires 212, two first insulating layers 213, a second insulating layer 214, an outer layer aluminum foil, and a PET tape (the PET tape is wrapped outside the outer layer aluminum foil to form a double-layer shielding tape 215). Each first insulating layer 213 cladding is respectively at the skin of a signal line 211, second insulating layer 214 cladding is respectively outward two signal lines 211 of first insulating layer 213 encircle the cladding, two ground wires 212 are located respectively the both sides of second insulating layer 214, just the center of two ground wires 212 with the center of two signal lines 211 is located same horizontal plane, double-deck shielding area 215 winding cladding is in two ground wires 212 and the outer 214 of second insulating layer are in order to form the conductor, and make the transverse section of wire 21 is the hexagon.
Preferably, the widths of the upper left surface 2101, the upper right surface 2102, the lower left surface 2103 and the lower right surface 2104 of each of the wires 21 are the same, and the widths of the upper surface 2105 and the lower surface 2106 of each of the wires 21 are the same and are greater than or equal to the widths of the upper left surface 2101, the upper right surface 2102, the lower left surface 2103 and the lower right surface 2104.
In addition, in the transverse cross section of each of the wires 21, an inner angle formed by the upper left side, the upper right side and the upper side and an inner angle formed by the lower left side, the lower right side and the lower side are R1, and satisfy: r1 is more than 120 degrees and less than or equal to 150 degrees. The interior angle that upper left side and lower left side constitute and the interior angle that upper right side and lower right side constitute are R2, and satisfy: 60 DEG-R2 < 120 DEG, so that the transverse section of each of the wires 21 is in the shape of a flat hexagon.
More preferably, R1 further satisfies: 135 DEG-R1-150 DEG, said R2 further satisfying: r2 is more than or equal to 60 degrees and less than or equal to 90 degrees.
With combined reference to fig. 13 and 14, in the QSFP-DD high-speed cable 2 provided in the present embodiment, the sixteen conductors wrapped by the fixed layer include a first row of upper conductors 201, a second row of upper conductors 202, a third row of upper conductors 203, a second row of lower conductors 204, and a first row of lower conductors 205, which are stacked from top to bottom. The third row of upper layer wires 203 and the second row of lower layer wires 204 respectively include four wires, and the four wires of the third row of upper layer wires 203 and the four wires of the second row of lower layer wires 204 are symmetrically distributed in parallel.
The second row of upper conductors 202 includes three conductors and spans between two adjacent conductors in the third row of upper conductors 203, and a left lower surface and a right lower surface of each conductor in the second row of upper conductors 202 are correspondingly attached to a right upper surface and a left upper surface of two adjacent conductors in the third row of upper conductors 203. The first row of upper layer conducting wires 201 comprise two conducting wires and respectively span between two adjacent conducting wires or two sides of the second row of upper layer conducting wires 202, and the left lower side surface and/or the right lower side surface of each conducting wire 201 in the first row of upper layer conducting wires are correspondingly attached to the right upper side surface and/or the left upper side surface of the adjacent conducting wire in the second row of upper layer conducting wires 202 respectively.
The first row of lower layer wires 205 comprises three wires and spans between two adjacent wires in the second row of lower layer wires 204, and the upper left side surface and the upper right side surface of each wire in the first row of lower layer wires 205 are correspondingly attached to the lower right side surface and the lower left side surface of two adjacent wires in the second row of lower layer wires 204.
Preferably, the distance between two adjacent wires in the third row of upper wires 203 is the same as the width of the upper/lower surface of each wire 21, so that the lower left and lower right surfaces of each wire in the second row of upper wires 202 can be completely attached to the upper right and upper left surfaces of two adjacent wires in the third row of upper wires 203, and the lower left and/or lower right surfaces of each wire in the first row of upper wires 201 can be completely attached to the upper right and/or upper left surfaces of two adjacent wires in the second row of upper wires 202.
Accordingly, the distance between two adjacent wires in the second row of lower layer wires 204 is the same as the width of the upper/lower surface of each wire, so that the upper left surface and the upper right surface of each wire in the first row of lower layer wires 205 can be completely attached to the lower right surface and the lower left surface of two adjacent wires in the second row of lower layer wires 204.
It can be seen that, in the 16 wires included in the QSFP-DD high-speed cable 2 provided in this embodiment, the structure of each wire is improved to make the transverse cross section of each wire be in a hexagonal structure (preferably, a flat hexagon), so that the thickness (height) of each wire can be effectively reduced, and the QSFP-DD high-speed cable is favorably accommodated in a housing of a QSFP-DD connector. In addition, 16 wires in the cable are stacked and arranged into 5 rows from top to bottom, the upper three rows (corresponding to 2, 3 and 4 wires) are stacked and arranged in a staggered mode, and the lower two rows are corresponding to 3 and 4 wires) are stacked and arranged in a staggered mode, so that the arrangement structure of all the wires in the QSFP-DD high-speed cable is firmer, the total thickness (height) of the QSFP-DD high-speed cable can be effectively reduced, and the flat QSFP-DD high-speed cable is formed. Moreover, the design of the upper three rows of leads which are arranged in a staggered and stacked manner and the lower two rows of leads which are arranged in a staggered and stacked manner is adopted, so that the design is beneficial to being respectively connected to the pads (three rows of butt-joint pads which are distributed in a staggered manner) on the upper surface of the printed circuit board 1 and the pads (two rows of butt-joint pads which are distributed in a staggered and stacked manner) on the lower surface of the printed circuit board 1, the total height (lower than the sum of the heights of the two leads) after the leads which are connected to the lower surface of the printed circuit board 1 are stacked is effectively reduced, and the technical problem caused by the low height of the lower-layer space inside the connector in the prior art can be solved.
As can be seen, according to the QSFP-DD high-speed cable assembly 100 provided by this embodiment, by using the printed circuit board 1 and the QSFP-DD high-speed cable 2 according to any of the above embodiments, a technical problem that a conductor cannot be accommodated due to a low height of a lower layer space inside a connector in the prior art can be solved, and a problem of vertical crosstalk between signal lines connected to pads on upper and lower layer surfaces of the printed circuit board can be effectively avoided. As shown in fig. 15 and 16, when the QSFP-DD high-speed cable assembly 100 provided by the present embodiment is inserted into the inside of the housing 301 of the QSFP-DD connector 300, the wires 21 connected to the pads on the lower-layer surface of the printed circuit board 1 can be completely accommodated in the internal lower-layer space of the connector 300.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A printed circuit board is suitable for being connected with a QSFP-DD high-speed cable and is characterized by comprising a circuit board body, an upper layer bonding pad and a lower layer bonding pad, wherein the upper layer bonding pad is arranged on the upper layer surface of the circuit board body, the lower layer bonding pad is arranged on the lower layer surface of the circuit board body, the upper layer bonding pad is used for being connected with nine wires in the QSFP-DD high-speed cable, and the lower layer bonding pad is used for being connected with the rest seven wires in the QSFP-DD high-speed cable; each conducting wire comprises two signal wires and two grounding wires, and the transverse section of each conducting wire is hexagonal;
the upper-layer bonding pads comprise a first row of upper-layer bonding pads, a second row of upper-layer bonding pads and a third row of upper-layer bonding pads, wherein the first row of upper-layer bonding pads, the second row of upper-layer bonding pads and the third row of upper-layer bonding pads are sequentially distributed from the front edge to the back edge of the upper surface of the circuit board body; the lower-layer bonding pads comprise a first row of lower-layer bonding pads and a second row of lower-layer bonding pads which are sequentially distributed from the front edge to the back edge of the lower-layer surface of the circuit board body, the first row of lower-layer bonding pads comprise three groups of butt-joint bonding pads, the second row of lower-layer bonding pads comprise four groups of butt-joint bonding pads, the first row of lower-layer bonding pads and the second row of lower-layer bonding pads are distributed in a staggered mode, and the four groups of butt-joint bonding pads of the second row of lower-layer bonding pads are close to the back edge of the lower-layer surface or are adjacent to the back edge of the lower-layer surface; each group of the butt joint bonding pads is correspondingly connected with one wire;
when the QSFP-DD high-speed cable is connected with the printed circuit board, in the QSFP-DD high-speed cable, a second row of upper-layer wires correspondingly connected with a second row of upper-layer bonding pads respectively span between two adjacent wires in a third row of upper-layer wires correspondingly connected with a third row of upper-layer bonding pads, and the left lower side surface and the right lower side surface of each wire in the second row of upper-layer wires are correspondingly attached to the right upper side surface and the left upper side surface of two adjacent wires in the third row of upper-layer wires respectively; the first row of upper-layer wires correspondingly connected with the first row of upper-layer bonding pads respectively span between two adjacent wires or two sides of the second row of upper-layer wires, and the left lower side surface and/or the right lower side surface of each wire in the first row of upper-layer wires are correspondingly attached to the right upper side surface and/or the left upper side surface of the adjacent wire in the second row of upper-layer wires; with first row lower floor's wire that first row lower floor's pad corresponds the connection stride respectively with the second row lower floor's pad corresponds between two adjacent wires in the second row lower floor's wire of connecting, just the upper left side surface, the upper right side surface of every wire in the first row lower floor's wire correspond the laminating with the lower right side surface, the lower left side surface of two adjacent wires in the second row lower floor's wire respectively.
2. The printed circuit board according to claim 1, wherein the width of the upper left surface, the upper right surface, the lower left surface and the lower right surface of each of the conductive wires is uniform, and the width of the upper surface and the lower surface of each of the conductive wires is uniform and greater than or equal to the width of the upper left surface, the upper right surface, the lower left surface and the lower right surface;
the distance between two adjacent wires in the third row of upper wires is consistent with the width of the upper surface/lower surface of each wire, so that the left lower side surface and the right lower side surface of each wire in the second row of upper wires are completely attached to the right upper side surface and the left upper side surface of two adjacent wires in the third row of upper wires, and the left lower side surface and/or the right lower side surface of each wire in the first row of upper wires are completely attached to the right upper side surface and/or the left upper side surface of the adjacent wire in the second row of upper wires;
the distance between two adjacent wires in the second row of lower layer wires is consistent with each width of the upper surface/lower surface of the wires, so that the upper left side surface and the upper right side surface of each wire in the first row of lower layer wires are completely attached to the lower right side surface and the lower left side surface of two adjacent wires in the second row of lower layer wires.
3. The printed circuit board according to claim 1 or 2, wherein in a transverse cross section of each of the wires, an inner angle formed by the upper left side, the upper right side and the upper side and an inner angle formed by the lower left side, the lower right side and the lower side are R1, and satisfy: r1 is more than 120 degrees and less than or equal to 150 degrees; the interior angle that upper left side and lower left side constitute and the interior angle that upper right side and lower right side constitute are R2, and satisfy: 60 DEG-R2 < 120 DEG, so that the transverse section of each wire is in a flat hexagon shape.
4. The printed circuit board of claim 3, wherein R1 further satisfies: 135 DEG-R1-150 DEG, said R2 further satisfying: r2 is more than or equal to 60 degrees and less than or equal to 90 degrees.
5. The printed circuit board of claim 1, wherein the third row of upper layer pads is located opposite the first row of lower layer pads on the upper surface of the circuit board body.
6. The printed circuit board of claim 1, wherein four sets of docking pads of the third row of upper pads are spaced from the rear edge of the upper surface by a distance greater than the length of the signal and ground wires exposed in the third row of upper leads corresponding to the third row of upper pads for soldering.
7. The printed circuit board of claim 1, wherein the upper layer pad is located in a rear region of the upper layer surface near the rear edge, and an upper layer golden finger is arranged in a front region of the upper layer surface near the front edge and is correspondingly connected with the upper layer pad; the lower-layer bonding pad is positioned in a rear area, close to the rear edge, of the lower-layer surface, a front area, close to the front edge, of the lower-layer surface is provided with a lower-layer golden finger, and the lower-layer golden finger is correspondingly connected with the lower-layer bonding pad.
8. The printed circuit board of claim 1, wherein each set of the docking pads comprises four pads, two signal lines and two ground lines respectively connected to each of the conductive lines; the two signal lines of each wire are correspondingly connected with the middle two bonding pads in each group of the butt-joint bonding pads, and the two grounding lines of each wire are correspondingly connected with the two side bonding pads in each group of the butt-joint bonding pads, so that the butt-joint bonding pads in each group form grounding-signal-grounding arrangement from left to right or from right to left on a printed circuit board, and the adjacent two rows of bonding pads on the upper layer surface/the lower layer surface of the circuit board body form grounding-signal staggered arrangement.
9. The printed circuit board of claim 1, wherein the thickness of each of the conductive lines is the same as the thickness of the printed circuit board.
10. A QSFP-DD high-speed cable assembly, comprising a printed circuit board according to any one of claims 1 to 9 and a QSFP-DD high-speed cable correspondingly connected with the printed circuit board.
CN202111428595.7A 2021-11-29 2021-11-29 Printed circuit board and QSFP-DD high-speed cable assembly Active CN113840454B (en)

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