CN113839657A - Power-on self-locking switch circuit - Google Patents
Power-on self-locking switch circuit Download PDFInfo
- Publication number
- CN113839657A CN113839657A CN202111134868.7A CN202111134868A CN113839657A CN 113839657 A CN113839657 A CN 113839657A CN 202111134868 A CN202111134868 A CN 202111134868A CN 113839657 A CN113839657 A CN 113839657A
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- Prior art keywords
- power
- key
- trigger
- self
- terminal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K2017/515—Mechanical switches; Electronic switches controlling mechanical switches, e.g. relais
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Abstract
The invention discloses a power-on self-locking switch circuit, which comprises a key SW, a trigger U1 and an MOS tube Q5; the input end of the KEY SW is connected to a power supply VCC, the output end of the KEY SW is grounded GND0 and is simultaneously connected to the CP end of the trigger U1 through a SYS _ KEY line, and the VDD end of the trigger U1 is connected to the power supply VCC and is grounded GND; the Q end of the trigger U1 is communicated to an MOS tube Q5 through a SYS _ ON line, and the MOS tube Q5 is located between VCC _ OUT and a power supply VCC and used for realizing the ON-off of VCC _ OUT and the power supply VCC. The invention realizes the power-on and power-off functions of the circuit by using the self-locking circuit consisting of the trigger and the electronic switch, has simple circuit principle, smaller volume and strong driving capability, can select a power-off MOS tube to switch on and off a large current working condition, and effectively avoids the key switch from working all the time when the key is powered on, thereby effectively prolonging the service life of the key and improving the reliability of power supply.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a power-on self-locking switch circuit which is applied to a product, does not need a mechanical self-locking switch and does not have microprocessor control requirements, and can realize power-on and power-off state maintenance of the circuit through a trigger and an electronic switch.
Background
The self-locking switch generally has a mechanical locking function, and after the switch is pressed and released, the button cannot be completely jumped up, can be in a locking state, and needs to be pressed once again to be unlocked and completely jumped up. Most of the button power-on switches are used for connecting or disconnecting a circuit when being pressed, the state is recovered after being released, and in order to achieve the purpose of keeping the 'pressed' state of the button switches, the button switches are required to be provided with a self-locking device like a mechanical self-locking switch, and can also keep the connection or disconnection state by self-locking performance, namely the switch with self-locking.
The existing self-locking switch for power-on and power-off of the circuit mainly uses a mechanical self-locking switch, and a button switch is matched with a corresponding self-locking circuit for use. The self-locking circuit is kept in a connection or disconnection state by a magnetic latching relay or a microprocessor control circuit.
For some product circuits, the low-temperature performance and the switch size and weight are large due to the fact that the mechanical structure inside the mechanical power-on switch is complex, a non-self-locking button needs to use a self-locking circuit to keep the switch state, and the self-locking circuit uses a microprocessor to control and occupy microprocessor resources. Frequent switching of mechanical switches can lead to contact aging, and arcing contacts are easily generated when a large current is cut off, thereby affecting the service life of the switches.
Disclosure of Invention
In order to solve the technical problem, the invention provides a power-on self-locking switch circuit, which comprises a key SW, a trigger U1 and an MOS tube Q5;
the input end of the KEY SW is connected to a power supply VCC, the output end of the KEY SW is grounded GND0 and is simultaneously connected to the CP end of the trigger U1 through a SYS _ KEY line, and the VDD end of the trigger U1 is connected to the power supply VCC and is grounded GND;
the Q end of the trigger U1 is communicated to an MOS tube Q5 through a SYS _ ON line, and the MOS tube Q5 is located between VCC _ OUT and a power supply VCC and used for realizing the ON-off of VCC _ OUT and the power supply VCC.
A capacitor C1 is arranged between the output end of the key SW and the ground GND 0. Further, a resistor R2 is disposed on the SYS _ KEY line and between the output terminal of the KEY SW and the CP terminal of the flip-flop U1. Further, a resistor R1 is disposed between the output terminal of the capacitor C1 and the input terminal of the resistor R2.
The Q # terminal, the CD terminal, the SD terminal and the VSS terminal of the flip-flop U1 are simultaneously grounded to GND, and the D terminal of the flip-flop U1 is connected to the Q # terminal and then grounded. Further, the D terminal of the flip-flop U1 is connected to the Q # terminal of the flip-flop U1 via a resistor R3. Further, a capacitor C3 is disposed between the Q # terminal of the flip-flop U1 and the ground GND, and the input terminal of the capacitor C3 and the output terminal of the resistor R # are both connected to the Q # terminal of the flip-flop U1.
A capacitor C2 is arranged between the VDD end of the trigger U1 and the ground GND.
The SYS _ ON line is provided with a resistor R4 and a resistor R5. Further, the transistor also includes a resistor R6, one end of the resistor R6 is connected to the power VCC corresponding to the MOS transistor Q5, and the other end is connected to the SYS _ ON line and located between the resistor R4 and the resistor R5.
Through the technical scheme, the invention has the following beneficial effects:
1. the self-locking circuit composed of the trigger and the electronic switch is used for realizing the power-on and power-off functions of the circuit, the circuit principle is simple, the size is small, the driving capability is strong, and a power-off MOS tube can be selected to switch on and off a large current working condition;
2. if the rated current of the contact is not large enough, the contact can be burnt or the contact is poor after a long time, and the technical scheme effectively avoids the situation that the key switch works all the time when the key switch is electrified, thereby effectively prolonging the service life of the key and improving the reliability of power supply.
Drawings
Fig. 1 is a schematic circuit diagram according to an embodiment of the present invention.
Detailed Description
Referring to fig. 1, the power-on self-locking switch circuit provided by the invention includes a key SW, a trigger U1 and a MOS transistor Q5; the input end of the KEY SW is connected to a power supply VCC, the output end of the KEY SW is grounded GND0 and is simultaneously connected to the CP end of the trigger U1 through a SYS _ KEY line, the VDD end of the trigger U1 is connected to the power supply VCC and grounded GND, and a capacitor C2 is arranged between the VDD end of the trigger U1 and the grounded GND; the Q end of the trigger U1 is communicated to an MOS tube Q5 through a SYS _ ON line, and the MOS tube Q5 is located between VCC _ OUT and a power supply VCC and used for realizing the ON-off of VCC _ OUT and the power supply VCC.
A capacitor C1 is arranged between the output end of the KEY SW and the ground GND0, a resistor R2 is arranged on the SYS _ KEY line and is located between the output end of the KEY SW and the CP end of the flip-flop U1, and a resistor R1 is arranged between the output end of the capacitor C1 and the input end of the resistor R2.
The Q # end, the CD end, the SD end and the VSS end of the trigger U1 are simultaneously grounded to GND, the D end of the trigger U1 is connected to the Q # end and then grounded, the D end of the trigger U1 is connected to the Q # end of the trigger U1 through a resistor R3, a capacitor C3 is arranged between the Q # end of the trigger U1 and the grounded GND, and the input end of the capacitor C3 and the output end of the resistor R # are both connected to the Q # end of the trigger U1.
Wherein, a resistor R4 and a resistor R5 are arranged ON the SYS _ ON circuit; the transistor also comprises a resistor R6, wherein one end of the resistor R6 is connected to a power supply VCC corresponding to the MOS transistor Q5, and the other end is connected to a SYS _ ON line and is positioned between the resistor R4 and the resistor R5.
The working principle of the invention is as follows:
a level signal is generated by the key SW, and a trigger U1 receives a pulse level and keeps and inverts the output level to drive a MOS tube Q5 so as to realize the on-off of the power supply VCC;
when the KEY SW is pressed down, the level of the SYS _ KEY line is changed from low to high, a rising edge signal is generated, the CP end of the trigger U1 receives the rising edge signal, the Q end of the trigger U1 outputs the state of the D end, the Q # end of the trigger U1 outputs the inverse logic state of the D end, and when the SD end and the CD end of the trigger U1 are connected with low levels, the state of the Q end of the trigger U1 can be defaulted to be high level when the self-locking circuit is electrified; when the CP end of the flip-flop U1 receives the rising edge signal for the first time, the Q end of the flip-flop U1 outputs a low level and keeps the low level, and the low level of the Q end drives the MOS transistor Q5 to be turned on, so that VCC _ OUT is connected to the power VCC;
when the key SW is pressed again, the CP end of the flip-flop U1 receives the rising edge signal, and the Q end of the flip-flop U1 outputs the last state of the Q # end, that is, the level state is inverted, so that the MOS transistor Q5 is turned off, and VCC _ OUT is turned off.
Various modifications to the above-described embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A power-on self-locking switch circuit is characterized by comprising a key SW, a trigger U1 and an MOS tube Q5;
the input end of the KEY SW is connected to a power supply VCC, the output end of the KEY SW is grounded GND0 and is simultaneously connected to the CP end of the trigger U1 through a SYS _ KEY line, and the VDD end of the trigger U1 is connected to the power supply VCC and is grounded GND;
the Q end of the trigger U1 is communicated to an MOS tube Q5 through a SYS _ ON line, and the MOS tube Q5 is located between VCC _ OUT and a power supply VCC and used for realizing the ON-off of VCC _ OUT and the power supply VCC.
2. The power-on self-locking switch circuit as claimed in claim 1, wherein a capacitor C1 is provided between the output terminal of the key SW and the ground GND 0.
3. The power-on self-locking switch circuit as claimed in claim 2, wherein a resistor R2 is provided on the SYS _ KEY line between the output terminal of the KEY SW and the CP terminal of the flip-flop U1.
4. A power-on self-locking switch circuit as claimed in claim 3, wherein a resistor R1 is provided between the output terminal of the capacitor C1 and the input terminal of the resistor R2.
5. The power-on self-locking switch circuit as claimed in claim 1, wherein the Q # terminal, the CD terminal, the SD terminal and the VSS terminal of the flip-flop U1 are simultaneously grounded to GND, and the D terminal of the flip-flop U1 is connected to the Q # terminal and then grounded.
6. The power-on self-locking switch circuit as claimed in claim 5, wherein the D terminal of the trigger U1 is connected to the Q # terminal of the trigger U1 via a resistor R3.
7. The power-on self-locking switch circuit as claimed in claim 6, wherein a capacitor C3 is disposed between the Q # terminal of the flip-flop U1 and the ground GND, and the input terminal of the capacitor C3 and the output terminal of the resistor R # are both connected to the Q # terminal of the flip-flop U1.
8. The power-on self-locking switch circuit as claimed in claim 1, wherein a capacitor C2 is provided between the VDD terminal of the trigger U1 and the ground GND.
9. The power-ON self-locking switch circuit as claimed in claim 1, wherein a resistor R4 and a resistor R5 are disposed ON the SYS _ ON line.
10. The power-ON self-locking switch circuit according to claim 9, further comprising a resistor R6, wherein one end of the resistor R6 is connected to the power source VCC corresponding to the MOS transistor Q5, and the other end is connected to the SYS _ ON line and located between the resistor R4 and the resistor R5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111134868.7A CN113839657A (en) | 2021-09-27 | 2021-09-27 | Power-on self-locking switch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111134868.7A CN113839657A (en) | 2021-09-27 | 2021-09-27 | Power-on self-locking switch circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113839657A true CN113839657A (en) | 2021-12-24 |
Family
ID=78970590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111134868.7A Pending CN113839657A (en) | 2021-09-27 | 2021-09-27 | Power-on self-locking switch circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113839657A (en) |
-
2021
- 2021-09-27 CN CN202111134868.7A patent/CN113839657A/en active Pending
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