CN219066134U

CN219066134U - Board-level communication bus circuit and household appliance

Info

Publication number: CN219066134U
Application number: CN202222110238.2U
Authority: CN
Inventors: 吕杨; 高秋英; 梁青; 沈政军
Original assignee: Qingdao Haier Washing Electric Appliance Co Ltd; Haier Smart Home Co Ltd
Current assignee: Qingdao Haier Washing Electric Appliance Co Ltd; Haier Smart Home Co Ltd
Priority date: 2022-08-11
Filing date: 2022-08-11
Publication date: 2023-05-23
Anticipated expiration: 2032-08-11

Abstract

The utility model discloses a board-level communication bus circuit and a household appliance, wherein the board-level communication bus circuit comprises a transmitting circuit and a receiving circuit, and the receiving circuit comprises: the voltage dividing circuit comprises a third resistor, a first diode and a ninth resistor which are sequentially connected in series, and the receiving end of the control board is connected between the third resistor and the first diode; and the control end of the first switch circuit is positioned between the first end of the first switch circuit and the first direct current power supply, and the control end of the first switch circuit is connected with the communication bus through the second resistor. According to the board-level communication bus circuit, the transmitting circuit and the receiving circuit can realize communication by adopting the first-level triode respectively, so that the problems of large time delay and low communication speed caused by the fact that the conventional multi-level triode is sequentially opened or closed when being opened or closed can be avoided.

Description

Board-level communication bus circuit and household appliance

Technical Field

The utility model belongs to the technical field of communication circuits, and particularly relates to a board-level high-speed communication bus circuit and household electrical appliances adopting the same.

Background

The interior of the home appliance often includes a plurality of control boards that communicate with each other via a communication bus.

As shown in fig. 1, a schematic diagram of a conventional communication bus circuit is commonly used for a plurality of control boards, and the circuit is used in each control board to form a communication bus. According to the scheme, when communication is stopped, all the triodes are in the off state, so that standby power consumption is avoided, but when communication is performed, all the triodes are simultaneously turned on at the falling edge of the BUS level, and are simultaneously turned off at the rising edge of the BUS level. Since the 4 transistors are turned on or off sequentially, the on time and the off time of the transistors are accumulated. And because the triode is opened at a speed significantly faster than the turn-off speed, the rising edge delay of the RXD received waveform is less than the falling edge delay. This delay difference cannot be ignored when the communication speed is high, and causes waveform distortion and communication failure.

As shown in fig. 2, the schematic diagram of another conventional communication bus circuit is shown, compared with scheme 1, when the scheme is not in communication, two transistors Q3 and Q4 are continuously turned on, when in communication, 2 transistors are turned on and 2 transistors are turned off no matter in rising edge or falling edge, and the rising edge and the falling edge caused by the transistors have the same delay time, so that the two transistors are offset, and the communication speed higher than that of scheme 1 can be realized, but the 2 transistors are always turned on, so that the standby power consumption is larger.

In addition, some schemes such as logic chips and high-speed triodes can be realized, but the cost is higher.

The above information disclosed in this background section is only for enhancement of understanding of the background section of the application and therefore it may not form the prior art that is already known to those of ordinary skill in the art.

Disclosure of Invention

The utility model provides a board-level communication bus circuit, which aims at the technical problems that a plurality of triodes are arranged in an existing inter-board communication circuit, so that the triodes are sequentially turned on or turned off, the communication speed is low, and a plurality of triodes are normally on when the existing inter-board communication circuit is in standby state, so that larger standby power consumption can be caused.

In order to achieve the aim of the utility model, the utility model is realized by adopting the following technical scheme:

a board-level communication bus circuit comprises a transmitting circuit and a receiving circuit,

the receiving circuit includes:

the voltage dividing circuit comprises a third resistor, a first diode and a ninth resistor which are sequentially connected in series, the other end of the third resistor is connected with a second direct current power supply, the other end of the ninth resistor is connected with ground, and a control board receiving end is connected between the third resistor and the first diode;

the first end of the first switch circuit is connected with a first direct current power supply, the second end of the first switch circuit is connected with the ground through the ninth resistor, the control end of the first switch circuit is located between the first end of the first switch circuit and the first direct current power supply, and the control end of the first switch circuit is connected with the communication bus through the second resistor.

In some embodiments of the present utility model, the first switching circuit includes a PNP transistor, an emitter of the PNP transistor is connected to the first dc power supply, a collector of the NPN transistor is connected to ground through the ninth resistor, a base of the PNP transistor is connected to ground through the seventh resistor, and a control terminal of the first switching circuit is located between the emitter of the PNP transistor and the first dc power supply.

In some embodiments of the present utility model, a first RC circuit is connected in parallel to two ends of the seventh resistor, and the first RC circuit includes a fourth resistor and a second capacitor connected in series.

In some embodiments of the present utility model, a second diode is connected between the base electrode and the collector electrode of the PNP triode, the anode of the second diode is connected with the collector electrode of the PNP triode, and the cathode of the second diode is connected with the base electrode of the PNP triode.

In some embodiments of the present utility model, a fourth capacitor is connected in parallel to two ends of the ninth resistor.

In some embodiments of the utility model, the receiving circuit comprises:

and the first end of the second switch circuit is connected with the communication bus through a sixth resistor, the second end of the second switch circuit is connected with the ground, and the control end of the second switch circuit is connected with the emitting end of the control board through a tenth resistor.

In some embodiments of the present utility model, the second switching circuit includes an NPN triode, a collector of the NPN triode is connected to the communication bus through a sixth resistor, an emitter of the NPN triode is connected to ground, and a base of the NPN triode is connected to the emission end of the control board through a tenth resistor.

In some embodiments of the present utility model, two ends of the tenth resistor are connected in parallel to a second RC circuit, and the second RC circuit includes an eighth resistor and a fifth capacitor connected in series.

In some embodiments of the present utility model, a third diode is connected between the base electrode and the collector electrode of the NPN triode, the anode of the third diode is connected with the base electrode of the NPN triode, and the cathode of the third diode is connected with the collector electrode of the NPN triode.

The utility model also provides a household appliance which is provided with a plurality of control boards, wherein the household appliance comprises the board-level communication bus circuit, and the control boards are communicated through the board-level communication bus circuit.

Compared with the prior art, the utility model has the advantages and positive effects that:

according to the board-level communication bus circuit, the transmitting circuit and the receiving circuit can realize communication by adopting the first-level triode respectively, so that the problems of large time delay and low communication speed caused by the fact that the conventional multi-level triode is sequentially opened or closed when being opened or closed can be avoided.

In the receiving circuit of the scheme, the receiving end of the control board is connected through the voltage dividing circuit, a first diode is arranged in the voltage dividing circuit, when no communication and high level of the sending BUS exist, the communication BUS is pulled up to a first direct current power supply VCC1, the first switching circuit is turned off, the first diode is turned on, the second direct current power supply VCC2 is pulled down to a low level after being divided by a third resistor and a ninth resistor, and the voltage division of the ninth resistor plus the forward voltage drop of the first diode are smaller than the level identification threshold of the control board. When no communication exists, only the second direct current power supply VCC2 to the third resistor-first diode-ninth resistor path has current, so that the purpose of reducing power consumption is achieved.

Other features and advantages of the present utility model will become apparent upon review of the detailed description of the utility model in conjunction with the drawings.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic circuit diagram of one prior art board-level communication bus circuit;

FIG. 2 is a schematic circuit diagram of another prior art board-level communication bus circuit;

FIG. 3 is a circuit schematic of one embodiment of a board-level communication bus circuit in accordance with the present utility model;

fig. 4 is a schematic block diagram of a communication connection between control boards in an embodiment of the home device according to the present utility model.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments of the present utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be noted that, in the description of the present utility model, terms such as "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate directions or positional relationships based on the directions or positional relationships shown in the drawings, which are merely for convenience of description, and do not indicate or imply that the apparatus or elements must have a specific orientation, be constructed and operated in a specific orientation, and thus are not to be construed as limiting the present utility model. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In the description of the present utility model, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.

In the present utility model, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.

Example 1

The embodiment provides a board-level communication bus circuit, which comprises a transmitting circuit and a receiving circuit, wherein the receiving circuit comprises a voltage dividing circuit and a first voltage dividing circuit, the voltage dividing circuit comprises a third resistor R3, a first diode D1 and a ninth resistor R9 which are sequentially connected in series, the other end of the third resistor R3 is connected with a second direct current power supply VCC2, the other end of the ninth resistor R9 is connected with a ground VDD, and a control board receiving end RXD is connected between the third resistor R3 and the first diode D1.

The first end of the first switch circuit is connected with the first direct current power supply VCC1, the second end of the first switch circuit is connected with the ground VDD through a ninth resistor R9, the control end of the first switch circuit is located between the first end of the first switch circuit and the first direct current power supply VCC, and the control end of the first switch circuit is connected with the communication BUS BUS through a second resistor R2.

According to the board-level communication bus circuit, the transmitting circuit and the receiving circuit can realize communication by adopting the first-level triode respectively, so that the problems of large time delay and low communication speed caused by the fact that the conventional multi-level triode is sequentially opened or closed when being opened or closed can be avoided. By providing the first diode D1 between the third resistor R3 and the ninth resistor R9, for example, it can be realized with 1N4148W, which is larger than the transistor in turn-off speed, a fast turn-off can be realized.

The transmitting end MCU TXD and the receiving end MCU RXD of the control board adopt the phase inversion function, so when the communication BUS BUS transmits a high level, the communication BUS BUS is pulled up to VCC1, the receiving end MCU RXD of the control board is low level, and after the low level received by the receiving end MCU RXD is subjected to phase inversion, the control board is high level which is consistent with the high level transmitted by the communication BUS BUS in actual analysis processing.

Similarly, the control board transmitting end MCU TXD is to send a high level signal to the communication BUS, its transmitting end inverts the high level to send it as a low level, and the transmitting circuit inverts the signal to the high level, and finally the signal received by the communication BUS is the high level, consistent with the signal to be sent by the control board.

In the receiving circuit of the scheme, the receiving circuit is connected with a control board receiving end MCU RXD through a voltage dividing circuit, a first diode D1 is arranged in the voltage dividing circuit, the anode of the first diode D1 is connected with the control board receiving end MCU RXD, the cathode of the first diode D1 is connected with a ninth resistor R9, when no communication exists, the communication BUS BUS is pulled up to a first direct current power supply VCC1, the first switching circuit is turned off, the first diode D1 is turned on at the moment, the second direct current power supply VCC2 is pulled down to a low level after being divided by a third resistor R3 and a ninth resistor R9, and the voltage division of the ninth resistor R9 and the forward voltage drop of the first diode D1 are smaller than the level identification threshold of the control board. Therefore, when no communication exists, only the paths from the second direct current power supply VCC2 to the third resistor R3 to the first diode D1 to the ninth resistor R9 have current, so that the purpose of reducing the power consumption is achieved.

By setting the resistance ratio of the third resistor R3 and the ninth resistor R9, the third resistor R3 can be designed to have a larger resistance value, thereby realizing low-power consumption design

In some embodiments of the utility model, the first switching circuit may be implemented using a PNN triode. As shown in fig. 3, the first switching circuit includes a PNP transistor Q1, an emitter of the PNP transistor Q1 is connected to the first dc power supply VCC1, a collector of the NPN transistor Q1 is connected to ground through a ninth resistor R9, a base of the PNP transistor Q1 is connected to ground through a seventh resistor R7, and a control end of the first switching circuit is located between the emitter of the PNP transistor Q1 and the first dc power supply VCC 1.

The communication principle of the receiving circuit in this embodiment is: when the communication BUS sends high level, the communication BUS is pulled up to VCC1, PNP triode Q1 is cut off, first diode D1 is switched on, second power VCC2 forms a loop through third resistor R3, first diode D1, ninth resistor R9, because the voltage division of third resistor R3, control board receiving end MCU RXD is low level, because it has the reverse phase function, after the low level received by receiving end MCU RXD is reversed phase, the control board actual analysis is high level, and is consistent with the high level sent by communication BUS BUS.

When the communication BUS BUS sends a low level, the PNP triode Q1 is conducted, the first diode D1 is cut off, the MCU RXD at the receiving end of the control board is pulled up to a high level by the second power supply, and the control board actually analyzes and processes the low level after the high level received by the MCU RXD at the receiving end is inverted due to the inversion function, and the low level is consistent with the low level sent by the communication BUS BUS.

In some embodiments of the present utility model, a first RC circuit is connected in parallel to two ends of the seventh resistor R7, and the first RC circuit includes a fourth resistor R4 and a second capacitor C2 connected in series.

The seventh resistor R7 is the base resistor of the PNP triode Q1, and the base resistor is connected with the first RC circuit in parallel, so that the BE junction capacitor of the triode can BE charged and discharged with larger driving capability when the level jumps, and the switching speed of the PNP triode Q1 is increased.

Specifically, when the PNP triode Q1 is turned off, the base voltage of the PNP triode Q1 is transient, and the second diode D2 is turned on, so that the base voltage of the PNP triode Q1 can be quickly lowered, and the turn-off speed of the PNP triode Q1 is further increased.

In some embodiments of the present utility model, a second diode D2 is connected between the base electrode and the collector electrode of the PNP triode Q1, the anode of the second diode D2 is connected with the collector electrode of the PNP triode Q1, and the cathode of the second diode D2 is connected with the base electrode of the PNP triode Q1.

The second diode D2 may be implemented by using a schottky diode, and the schottky diode is added between the base and the collector of the PNP triode Q1, so that the PNP triode Q1 is forced to work in a non-saturated state, and the turn-off speed of the PNP triode Q1 is accelerated.

In some embodiments of the present utility model, a fourth capacitor C4 is connected in parallel across the ninth resistor R9, and is used for filtering signals.

In some embodiments of the present utility model, the board-level communication BUS circuit further includes a third capacitor C3, where the control board receiving end RXD is connected to ground through the third capacitor C3, where the third capacitor C3 charges through a third resistor R3 at a falling edge of the communication BUS, and discharges through a ninth resistor R9 at a rising edge of the communication BUS, and according to a proportional configuration of the third resistor R3 and the ninth resistor R9, a resistance value of the third resistor R3 is greater than the ninth resistor R9, so that compensation of rising edge delay and falling edge delay can be performed by adjusting a capacitance value of the third capacitor C3, thereby realizing faster communication speed.

In some embodiments of the utility model, the receiving circuit comprises:

and the first end of the second switching circuit is connected with the communication BUS BUS through a sixth resistor R6, the second end of the second switching circuit is connected with the ground, and the control end of the second switching circuit is connected with the control panel transmitting end MCU TXD through a tenth resistor R10.

When the control board sends low level to the communication BUS BUS, the control board transmitting end MCU TXD jumps from low level to high level, the second switch circuit is conducted, the first power supply VCC1 is divided by the second resistor R2 and the sixth resistor R6 after the second switch circuit is conducted, and the low level is output to the communication BUS BUS after the first power supply VCC1 is divided.

When the control board sends a high level to the communication BUS BUS, the control board transmitting end MCU TXD jumps from the high level to the low level, the second switching circuit is cut off, and the communication BUS BUS is pulled up to the high level by the first power supply VCC1 after cut-off.

In some embodiments of the present utility model, the second switching circuit may be implemented using an NPN transistor. As shown in fig. 3, the second switching circuit includes an NPN triode Q2, a collector of the NPN triode Q2 is connected to the communication BUS through a sixth resistor R6, an emitter of the NPN triode Q2 is connected to ground, and a base of the NPN triode Q2 is connected to the control board transmitting end MCU TXD through a tenth resistor R10.

With the second switching circuit of this embodiment, when the control board sends a low level to the communication BUS, the control board transmitting end MCU TXD jumps from the low level to the high level, and the base voltage of the NPN triode Q2 is higher than the emitter voltage, so that the NPN triode Q2 is turned on, and after the turn-on, the first power VCC1 is divided by the second resistor R2 and the sixth resistor R6, and the divided voltage outputs a low level to the communication BUS.

The sixth resistor R6 is used for preventing the NPN triode Q2 from being damaged too much when the first power supply VCC1 is shorted with the communication BUS.

When the control board sends a high level to the communication BUS, the transmitting end MCU TXD of the control board jumps from the high level to the low level, and the base voltage of the NPN triode Q2 is smaller than the emitter voltage, so that the NPN triode Q2 is cut off, and the communication BUS is pulled up to the high level by the first power supply VCC1 after the cut-off.

In some embodiments of the present utility model, the two ends of the tenth resistor R10 are connected in parallel to a second RC circuit, and the second RC circuit includes an eighth resistor R8 and a fifth capacitor C5 connected in series.

The tenth resistor R10 is used as the base resistor of the NPN triode Q2, and the second RC circuits are connected in parallel at the two ends of the tenth resistor R10, so that the BE junction capacitor of the triode can BE charged and discharged with larger driving capability during level jump, and the switching speed of the NPN triode Q2 is accelerated.

In some embodiments of the present utility model, a third diode D3 is connected between the base electrode and the collector electrode of the NPN triode Q2, the anode of the third diode D3 is connected with the base electrode of the NPN triode Q2, and the cathode of the third diode D3 is connected with the collector electrode of the NPN triode Q2.

The third diode D3 may be implemented by using a schottky diode, and a schottky diode is added between the base and the collector of the NPN triode Q2, so that the NPN triode Q2 is forced to work in a non-saturated state, and the turn-off speed of the NPN triode Q2 is increased.

Specifically, when the transmission communication BUS is at a low level, the control board transmitting end MCU TXD jumps from a low level to a high level, the NPN transistor Q2 is turned on and clamped in the unsaturated conduction mode by the third diode D3, and at this time, the collector of the NPN transistor Q2 is about 0.3V. Meanwhile, the PNP triode Q1 is conducted and clamped in a non-saturated conduction mode by the second diode D2, after the PNP triode Q1 is conducted, the first capacitor VCC1 is divided by the fifth resistor R5 and the ninth resistor R9, the voltage after the division is set to be higher than the second power supply VCC2, at the moment, the first diode D1 is cut off, and the control panel receiving end MCU RXD is pulled up to the second power supply VCC2 by the third resistor R3.

And a clamping diode D4 is further connected between the collector of the NPN triode Q2 and the sixth resistor R6, one end of the clamping diode D4 is connected with a 12V direct current power supply, and the other end of the clamping diode D4 is connected with the ground for clamping the level, so that overvoltage failure caused by line coupling and the like of the PNP triode Q1 and the NPN triode Q2 is prevented.

Example two

The utility model also provides a household appliance, as shown in fig. 4, the household appliance is provided with a plurality of control boards, namely, a control board 1, a control board 2 and a control board … …, the household appliance further comprises board-level communication bus circuits, and the control boards are respectively connected with one board-level communication bus circuit for communication between the control boards through buses.

The board-level communication bus circuit of the present embodiment may be specifically described in the first embodiment, and will not be described herein.

It should be noted that, the home appliance in this embodiment may be, but is not limited to, a device including a plurality of control boards in a system such as a washing machine, a clothes dryer, a refrigerator, an air conditioner, a television, a nursing machine, a dish washer, and the like.

The above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; although the utility model has been described in detail with reference to the foregoing embodiments, it will be apparent to one skilled in the art that modifications may be made to the technical solutions described in the foregoing embodiments, or equivalents may be substituted for some of the technical features thereof; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.

Claims

1. A board-level communication bus circuit is characterized by comprising a transmitting circuit and a receiving circuit,

the receiving circuit includes:

2. The board-level communication bus circuit of claim 1, wherein the first switching circuit comprises a PNP transistor, an emitter of the PNP transistor is connected to the first dc power supply, a collector of the PNP transistor is connected to ground through the ninth resistor, a base of the PNP transistor is connected to ground through the seventh resistor, and a control terminal of the first switching circuit is located between the emitter of the PNP transistor and the first dc power supply.

3. The board-level communication bus circuit of claim 2, wherein a first RC circuit is connected in parallel across the seventh resistor, the first RC circuit comprising a fourth resistor and a second capacitor connected in series.

4. The board-level communication bus circuit of claim 2, wherein a second diode is connected between the base of the PNP transistor and the collector thereof, the anode of the second diode is connected with the collector of the PNP transistor, and the cathode of the second diode is connected with the base of the PNP transistor.

5. The board-level communication bus circuit of claim 1, wherein a fourth capacitor is connected in parallel across the ninth resistor.

6. The board level communication bus circuit of any one of claims 1-5, wherein the receive circuit comprises:

7. The board-level communication bus circuit of claim 6, wherein the second switching circuit comprises an NPN triode, a collector of the NPN triode is connected to the communication bus through a sixth resistor, an emitter of the NPN triode is connected to ground, and a base of the NPN triode is connected to the control board transmitting terminal through a tenth resistor.

8. The board-level communication bus circuit of claim 7, wherein a second RC circuit is connected in parallel across the tenth resistor, the second RC circuit comprising an eighth resistor and a fifth capacitor connected in series.

9. The board-level communication bus circuit of claim 7, wherein a third diode is connected between the base of the NPN triode and the collector thereof, the anode of the third diode is connected with the base of the NPN triode, and the cathode of the third diode is connected with the collector of the NPN triode.

10. An appliance having a plurality of control boards, wherein the appliance includes the board level communication bus circuit of any one of claims 1-9, the control boards communicating therebetween via the board level communication bus circuit.