CN219107285U - Interlocking drive circuit and electronic equipment - Google Patents
Interlocking drive circuit and electronic equipment Download PDFInfo
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- CN219107285U CN219107285U CN202223518857.1U CN202223518857U CN219107285U CN 219107285 U CN219107285 U CN 219107285U CN 202223518857 U CN202223518857 U CN 202223518857U CN 219107285 U CN219107285 U CN 219107285U
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Abstract
The application provides an interlocking driving circuit and electronic equipment. The interlocking driving circuit is used for driving the upper bridge arm switching tube and the lower bridge arm switching tube. The interlocking driving circuit comprises a driving module, a current limiting module and an interlocking module which are electrically connected in sequence, and the interlocking module is also electrically connected with an upper bridge arm switch tube and a lower bridge arm switch tube. The driving module is used for outputting a first driving signal and a second driving signal to the interlocking module through the current limiting module; the current limiting module is used for protecting the interlocking module; the interlocking module is used for controlling the upper bridge arm switching tube and the lower bridge arm switching tube to be not conducted simultaneously according to the first driving signal and the second driving signal, so that the failure rate of the upper bridge arm switching tube and the lower bridge arm switching tube during working is reduced.
Description
Technical Field
The application relates to the technical field of circuit control, in particular to an interlocking driving circuit and electronic equipment.
Background
In circuit design, a half-bridge circuit or a full-bridge circuit formed by MOS transistors is often used, and thus, the driving design of the MOS transistors in the half-bridge circuit or the full-bridge circuit is also indispensable. At present, a separated device such as a totem pole push-pull structure is often adopted for driving; or directly driven with an integrated IC. Whichever is used, it is desirable to avoid the occurrence of a situation where the upper and lower bridges are simultaneously on. The current common method is to set dead time by programming to prevent the upper bridge and the lower bridge from conducting simultaneously. However, the method of setting the dead zone by the software often has the phenomenon of misleading outside the dead zone in some special occasions such as high-power and serious-interference designs.
Disclosure of Invention
In view of this, the present application provides an interlocking driving circuit, a half-bridge driving circuit, a full-bridge driving circuit and an electronic device, which reduce the occurrence of the situation that upper and lower bridges are simultaneously turned on by mistake through hardware structural design.
The first aspect of the application provides an interlocking driving circuit, which is used for driving an upper bridge arm switching tube and a lower bridge arm switching tube, and comprises a driving module, a current limiting module and an interlocking module which are electrically connected in sequence, wherein the interlocking module is also electrically connected to the upper bridge arm switching tube and the lower bridge arm switching tube. The driving module is used for outputting a first driving signal and a second driving signal to the interlocking module through the current limiting module; the current limiting module is used for protecting the interlocking module; the interlocking module is used for controlling the upper bridge arm switching tube and the lower bridge arm switching tube to be not conducted simultaneously according to the first driving signal and the second driving signal.
In an embodiment, the interlocking module includes a first interlocking unit and a second interlocking unit, the first interlocking unit is electrically connected between the current-limiting module and the upper bridge arm switching tube, the second interlocking unit is electrically connected between the current-limiting module and the lower bridge arm switching tube, the first interlocking unit is used for controlling the upper bridge arm switching tube to be turned on or turned off according to a first driving signal and a second driving signal, the second interlocking unit is used for controlling the lower bridge arm switching tube to be turned on or turned off according to the first driving signal and the second driving signal, and the upper bridge arm switching tube and the lower bridge arm switching tube are not turned on at the same time.
In an embodiment, the driving module includes a first output end and a second output end, the current limiting module includes a first current limiting unit and a second current limiting unit, a first end of the first current limiting unit is electrically connected to the first output end, a second end of the first current limiting unit is electrically connected to the first interlocking unit and the second interlocking unit, the first output end outputs a first driving signal to the first interlocking unit and the second interlocking unit through the first current limiting unit, a first end of the second current limiting unit is electrically connected to the second output end, a second end of the second current limiting unit is electrically connected to the first interlocking unit and the second interlocking unit, and the second output end outputs a second driving signal to the first interlocking unit and the second interlocking unit through the second current limiting unit.
In an embodiment, the first interlocking unit includes a first switch tube, a first diode, and a second switch tube, where a first end of the first switch tube is electrically connected to a second end of the first current limiting unit, a second end of the first switch tube is electrically connected to a second end of the second current limiting unit, a third end of the first switch tube is grounded, an anode of the first diode is electrically connected to a first end of the first switch tube, a cathode of the first diode is electrically connected to a second end of the upper bridge arm switch tube, a first end of the second switch tube is electrically connected between the cathode of the first diode and the upper bridge arm switch tube, a second end of the second switch tube is electrically connected between the first end of the second switch tube and the anode of the first diode, and a third end of the second switch tube is electrically connected between the third end of the first switch tube and ground.
In an embodiment, the first switching tube is an NMOS tube, a first end of the first switching tube is a drain, a second end of the first switching tube is a gate, and a third end of the first switching tube is a source; the second switching tube is a PNP triode, the first end of the second switching tube is an emitter, the second end of the second switching tube is a base, and the third end of the second switching tube is a collector.
In an embodiment, the second interlocking unit includes a third switching tube, a second diode and a fourth switching tube, the first end of the third switching tube is electrically connected to the second end of the second current limiting unit, the second end of the third switching tube is electrically connected to the second end of the first current limiting unit, the third end of the third switching tube is grounded, the anode of the second diode is electrically connected to the first end of the third switching tube, the cathode of the second diode is electrically connected to the second end of the lower bridge arm switching tube, the first end of the fourth switching tube is electrically connected between the cathode of the second diode and the lower bridge arm switching tube, the second end of the fourth switching tube is electrically connected between the first end of the fourth switching tube and the anode of the second diode, and the third end of the fourth switching tube is electrically connected between the third end of the third switching tube and ground.
In an embodiment, the second interlocking unit further includes a first voltage dividing resistor and a second voltage dividing resistor, the second end of the third switching tube is electrically connected to the second end of the first current limiting unit through the first voltage dividing resistor, and the second end of the third switching tube is grounded through the second voltage dividing resistor.
In an embodiment, the third switching tube is an NMOS tube, the first end of the third switching tube is a drain, the second end of the third switching tube is a gate, and the third end of the third switching tube is a source; the fourth switching tube is a PNP triode, the first end of the fourth switching tube is an emitter, the second end of the fourth switching tube is a base, and the third end of the fourth switching tube is a collector.
In an embodiment, the first current limiting unit includes a first current limiting resistor, the second current limiting unit includes a second current limiting resistor, and a first end of the first current limiting resistor is electrically connected to the first output terminal, a second end of the first current limiting resistor is electrically connected to the first interlocking unit and the second interlocking unit, a first end of the second current limiting resistor is electrically connected to the second output terminal, and a second end of the second current limiting resistor is electrically connected to the first interlocking unit and the second interlocking unit.
A second aspect of the present application provides an electronic device comprising an upper leg switching tube, a lower leg switching tube, and an interlocking drive circuit as described in any one of the above.
According to the interlocking driving circuit, the interlocking module is arranged to control the upper bridge arm switching tube and the lower bridge arm switching tube to be not conducted simultaneously from the hardware circuit, so that the failure rate of the upper bridge arm switching tube and the lower bridge arm switching tube is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the present application, the drawings that are required for the embodiments will be briefly described, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope of protection of the present application. Like elements are numbered alike in the various figures.
Fig. 1 is a circuit block diagram of an interlock driving circuit according to another embodiment of the present application.
Fig. 2 is a circuit diagram of an interlock driving circuit according to an embodiment of the present application.
Fig. 3 is a circuit diagram of a power supply module for supplying power to the driving module shown in fig. 2 according to an embodiment of the present application.
Description of the main reference signs
Upper bridge arm switch tube Q1
Lower bridge arm switch tube Q2
Interlocking drive circuit 100
First output terminal HO
A second output terminal LO
Current limiting module 20
First current limiting unit 21
First current limiting resistor R3
Second current limiting unit 22
Second current limiting resistor R4
First switching tube T1
First diode D1
Second switching tube T2
Third switching tube T3
Second diode D2
Fourth switching tube T4
First voltage dividing resistor R1
Second voltage-dividing resistor R2
First power supply unit 41
First voltage conversion chip 411
Second power supply unit 42
Second voltage conversion chip 412
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments.
It is noted that when one component is considered to be "connected" to another component, it may be directly connected to the other component or intervening components may also be present.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Some embodiments will be described below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
In circuit design, a half-bridge circuit or a full-bridge circuit formed by MOS transistors is often used, and thus, the driving design of the MOS transistors in the half-bridge circuit or the full-bridge circuit is also indispensable. At present, a separated device such as a totem pole push-pull structure is often adopted for driving; or directly driven with an integrated IC. Whichever is used, it is desirable to avoid the occurrence of a situation where the upper and lower bridges are simultaneously on. The current common method is to set dead zone by programming to prevent the upper bridge and the lower bridge from conducting simultaneously. However, the method of setting the dead zone by the software often has the phenomenon of misleading outside the dead zone in some special occasions such as high-power and serious-interference designs.
For this reason, referring to fig. 1, an embodiment of the present application provides an interlocking driving circuit 100 for reducing the occurrence of the situation that the upper bridge arm switching tube Q1 and the lower bridge arm switching tube Q2 are simultaneously misled while driving the upper bridge arm switching tube Q1 and the lower bridge arm switching tube Q2.
The interlock driving circuit 100 includes a driving module 10, a current limiting module 20, and an interlock module 30 electrically connected in sequence. The interlock module 30 is also electrically connected to the upper arm switching tube Q1 and the lower arm switching tube Q2. The driving module 10 is configured to output a first driving signal and a second driving signal to the interlocking module 30 through the current limiting module 20. The current limiting module 20 is used for limiting the current of the first driving signal and the second driving signal, so as to protect the interlocking module 30, and reduce the probability of damage of the interlocking module 30 due to excessive current. The interlock module 30 is configured to control the upper bridge arm switching tube Q1 and the lower bridge arm switching tube Q2 not to be turned on at the same time according to the first driving signal and the second driving signal.
In this way, in the interlocking driving circuit 100 provided in the present application, by setting the interlocking module 30, the upper bridge arm switching tube Q1 and the lower bridge arm switching tube Q2 are controlled from the hardware circuit to be not turned on at the same time, so that the failure rate of the upper bridge arm switching tube Q1 and the lower bridge arm switching tube Q2 is reduced.
Further, in an embodiment of the present application, the driving module 10 includes a first output terminal and a second output terminal. The current limiting module 20 includes a first current limiting unit 21 and a second current limiting unit 22. The interlock module 30 includes a first interlock unit 31 and a second interlock unit 32.
Wherein a first end of the first current limiting unit 21 is electrically connected to the first output terminal. The second end of the first current limiting unit 21 is electrically connected to the first and second interlocking units 31 and 32. The first output terminal is configured to output a first driving signal to the first interlocking unit 31 and the second interlocking unit 32 through the first current limiting unit 21. The first end of the second current limiting unit 22 is electrically connected to the second output end, the second end of the second current limiting unit 22 is electrically connected to the first interlocking unit 31 and the second interlocking unit 32, and the second output end is used for outputting the second driving signal to the first interlocking unit 31 and the second interlocking unit 32 through the second current limiting unit 22.
The first interlocking unit 31 is electrically connected between the current limiting module 20 and the upper bridge arm switching tube Q1. Second interlock element 32 is electrically connected between current limiting module 20 and lower leg switching tube Q2. The first interlocking unit 31 is used for controlling the upper bridge arm switching tube Q1 to be switched on or switched off according to the received first driving signal and the second driving signal, the second interlocking unit 32 is used for controlling the lower bridge arm switching tube Q2 to be switched on or switched off according to the received first driving signal and the received second driving signal, and the upper bridge arm switching tube Q1 and the lower bridge arm switching tube Q2 are not switched on at the same time. In this way, in the embodiment of the present application, the interlock module 30 sets the first interlock unit 31 and the second interlock unit 32 to jointly control the upper bridge arm switching tube Q1 and the lower bridge arm switching tube Q2 to be not turned on simultaneously through the first interlock unit 31 and the second interlock unit 32, so as to reduce occurrence of faults.
With continued reference to fig. 2, fig. 2 is a specific circuit diagram of an interlock driving circuit according to an embodiment of the present application.
Wherein the driving module 10 may be a driving chip. And the driving module 10 includes a first output terminal HO and a second output terminal LO. And the first output terminal HO is electrically connected to the first interlock unit 31 and the second interlock unit 32 through the first current limiting unit 21. The second output terminal LO is electrically connected to the first interlock unit 31 and the second interlock unit 32 through the second current limiting unit 22.
The first interlock unit 31 includes a first switching tube T1, a first diode D1, and a second switching tube T2. Wherein, the first end of the first switching tube T1 is electrically connected to the second end of the first current limiting unit 21. The second end of the first switching tube T1 is electrically connected to the second end of the second current limiting unit 22. The third end of the first switching tube T1 is grounded. The anode of the first diode D1 is electrically connected to the first terminal of the first switching tube T1. The cathode of the first diode D1 is electrically connected to the second end of the upper arm switching tube Q1. The first end of the second switching tube T2 is electrically connected between the cathode of the first diode D1 and the upper bridge arm switching tube Q1. The second end of the second switching tube T2 is electrically connected between the first end of the second switching tube T2 and the anode of the first diode D1. The third terminal of the second switching tube T2 is electrically connected between the third terminal of the first switching tube T1 and ground.
The second interlocking unit 32 includes a third switching tube T3, a second diode D2, and a fourth switching tube T4. The first end of the third switching tube T3 is electrically connected to the second end of the second current limiting unit 22, the second end of the third switching tube T3 is electrically connected to the second end of the first current limiting unit 21, and the third end of the third switching tube T3 is grounded. The anode of the second diode D2 is electrically connected to the first end of the third switching tube T3. The cathode of the second diode D2 is electrically connected to the second end of the lower arm switching tube Q2. The first end of the fourth switching tube T4 is electrically connected between the cathode of the second diode D2 and the lower bridge arm switching tube Q2. The second end of the fourth switching tube T4 is electrically connected between the first end of the fourth switching tube T4 and the anode of the second diode D2, and the third end of the fourth switching tube T4 is electrically connected between the third end of the third switching tube T3 and ground.
The first end of the upper arm switching tube Q1 is electrically connected to the power source VIN. The second terminal of the upper bridge arm switching tube Q1 is electrically connected between the cathode of the first diode D1 of the first interlock unit 31 and the first terminal of the second switching tube T2. The third terminal of the upper arm switching tube Q1 is electrically connected to the first terminal of the lower arm switching tube Q2. A second terminal of lower leg switching tube Q2 is electrically connected between the cathode of second diode D2 of second interlock element 32 and the first terminal of fourth switching tube T4. The third end of the lower bridge arm switch tube Q2 is grounded. Thus, in the embodiment of the present application, the upper arm switching tube Q1 and the lower arm switching tube Q2 together form a half-bridge circuit.
The second interlocking unit 32 further includes a first voltage dividing resistor R1 and a second voltage dividing resistor R2. The second end of the third switching tube T3 is electrically connected to the second end of the first current limiting unit 21 through the first voltage dividing resistor R1. The second end of the third switching tube T3 is also grounded through a second voltage dividing resistor R2.
Further, in the present application, the first switching tube T1 and the third switching tube T3 are NMOS tubes. The first ends of the first switching tube T1 and the third switching tube T3 are drain electrodes, the second ends of the first switching tube T1 and the third switching tube T3 are grid electrodes, and the first ends of the first switching tube T1 and the third switching tube T3 are source electrodes. The second switching tube T2 and the fourth switching tube T4 are PNP triodes, the first ends of the second switching tube T2 and the fourth switching tube T4 are emitters, the second ends of the second switching tube T2 and the fourth switching tube T4 are bases, and the third ends of the second switching tube T2 and the fourth switching tube T4 are collectors.
The upper bridge arm switching tube Q1 and the lower bridge arm switching tube Q2 are NMOS tubes, the first ends of the upper bridge arm switching tube Q1 and the lower bridge arm switching tube Q2 are drain electrodes, the second ends of the upper bridge arm switching tube Q1 and the lower bridge arm switching tube Q2 are grid electrodes, and the third ends of the upper bridge arm switching tube Q1 and the lower bridge arm switching tube Q2 are source electrodes.
It can be understood that the interlocking driving circuit provided in fig. 2 operates as follows:
in the first scenario, when the level of the first driving signal output by the driving module 10 through the first current limiting unit 21 is a first level (e.g., a high level), the level of the second driving signal output by the driving module 10 through the second current limiting unit 22 is a second level (e.g., a low level),
1) In the first interlocking unit 31, the first diode D1 is turned on, so that the potential of the second end of the upper bridge arm switching tube Q1 is greater than the potential of the third end of the upper bridge arm switching tube Q1, and the upper bridge arm switching tube Q1 is turned on; meanwhile, the potential of the second end of the first switching tube T1 is smaller than that of the third end, and thus the first switching tube T1 is disconnected; the potential of the first end of the second switching tube T2 is smaller than that of the second end, so that the second switching tube T2 is also disconnected;
2) In the second interlocking unit 32, the second diode D2 is turned off, the potential of the second end of the third switching tube T3 is greater than the potential of the third end, so that the third switching tube T3 is turned on, the potential of the second end of the fourth switching tube T4 is pulled down, so that the potential of the second end of the fourth switching tube T4 is smaller than the potential of the first end, the fourth switching tube T4 is turned on, and the potential of the second end of the lower bridge arm switching tube Q2 is pulled down, so that the lower bridge arm switching tube Q2 is turned off;
in this way, when the level of the first driving signal is the first level and the level of the second driving signal is the second level, the upper arm switching tube Q1 is turned on and the lower arm switching tube Q2 is turned off.
In the second scenario, when the level of the first driving signal output by the driving module 10 through the first current limiting unit 21 is a second level (e.g., a low level), the level of the second driving signal output by the driving module 10 through the second current limiting unit 22 is a first level (e.g., a high level),
1) In the first interlock unit 31, the first diode D1 is turned off; the potential of the second end of the first switching tube T1 is larger than that of the third end, so that the first switching tube T1 is conducted, the potential of the second end of the second switching tube T2 is pulled down, so that the potential of the second end of the second switching tube T2 is smaller than that of the first end, the second switching tube T2 is conducted, and then the potential of the second end of the upper bridge arm switching tube Q1 is pulled down, and the upper bridge arm switching tube Q1 is disconnected;
2) In the second interlocking unit 32, the second diode D2 is turned on, so that the potential of the second end of the lower bridge arm switching tube Q2 is greater than the potential of the third end of the lower bridge arm switching tube Q2, and the lower bridge arm switching tube Q2 is turned on; meanwhile, the potential of the second end of the third switching tube T3 is not more than that of the third end, and thus, the third switching tube T3 is disconnected; the potential of the first end of the fourth switching tube T4 is smaller than that of the second end, so that the fourth switching tube T4 is also disconnected;
in this way, when the level of the first driving signal is the second level and the level of the second driving signal is the first level, the upper arm switching tube Q1 is turned off and the lower arm switching tube Q2 is turned on.
In the third scenario, when the levels of the first driving signal and the second driving signal output by the driving module 10 through the first current limiting unit 21 are the first level (e.g., the high level), the first switching tube T1 and the second switching tube T2 are both turned on, so that the levels of the first output terminal HO and the second output terminal LO are simultaneously pulled down by the first switching tube T1 and the second switching tube T2, so that the upper bridge arm switching tube Q1 and the lower bridge arm switching tube Q2 cannot be turned on, and the upper bridge arm switching tube Q1 and the lower bridge arm switching tube Q2 cannot be turned on simultaneously.
It can be appreciated that, in the interlocking driving circuit 100 provided by the present application, by setting the first interlocking unit 31 between the first output end HO of the driving module 10 and the upper bridge arm switching tube Q1, and setting the second interlocking unit 32 between the second output end LO and the lower bridge arm switching tube Q2, when the first output end HO and the second output end LO output corresponding first driving signals and second driving signals, the circuit design in the first interlocking unit 31 and the second interlocking unit 32 controls the upper bridge arm switching tube Q1 and the lower bridge arm switching tube Q2 not to be turned on simultaneously, so that any dead zone driving can be realized, the probability of occurrence of short circuit faults between the upper bridge arm switching tube Q1 and the lower bridge arm switching tube Q2 is reduced, and the anti-interference capability of the circuit is increased.
Further, in the interlocking module 30 of the present application, by setting the second switching tube T2 electrically connected to the gate of the upper bridge arm switching tube Q1 and setting the fourth switching tube T4 electrically connected to the gate of the lower bridge arm switching tube Q2, rapid discharging can be achieved, and the speed of the falling edge of the driving waveform can be increased.
It will be appreciated that in some embodiments, the first current limiting unit 21 in the current limiting module 20 includes a first current limiting resistor R3, and the second current limiting unit 22 includes a second current limiting resistor R4. And a first end of the first current limiting resistor R3 is electrically connected to the first output terminal HO, and a second end of the first current limiting resistor R3 is electrically connected between a first end of the first switching tube T1 of the first interlock unit 31 and the first voltage dividing resistor R1 of the second interlock unit 32. The first end of the second current limiting resistor R4 is electrically connected to the second output terminal LO, the second end of the second current limiting resistor R4 is electrically connected to the second end of the first switching tube T1 of the first interlock unit 31, and the first end of the third switching tube T3 of the second interlock unit 32.
It is understood that the present application is not limited to the types of the first to fourth switching transistors T1 to T4 mentioned above, and in other embodiments, the first to fourth switching transistors T1 to T4 may be replaced by other switching transistors, such as insulated gate bipolar transistors (Insulated Gate Bipolar Transistor, IGBTs), P-type MOS transistors, NPN transistors, or the like, based on the concepts of the present application.
It is understood that the circuit structures of the first current limiting unit 21 and the second current limiting unit 22 may be the same or different. And the first current limiting unit 21 and the second current limiting unit 22 are not limited to the current limiting resistor of the present application, in other embodiments, the first current limiting unit 21 and the second current limiting unit 22 may respectively include a combination of one or more passive elements (such as a resistor, a capacitor, or an inductor); the first current limiting unit 21 and the second current limiting unit 22 may also include other circuits or electronic components with current limiting function, respectively.
It can be appreciated that the upper bridge arm switching tube Q1 and the lower bridge arm switching tube Q2 in fig. 2 form a half-bridge circuit, that is, the interlocking driving circuit 100 provided in the embodiment of the present application may be used to drive the half-bridge circuit. It can be appreciated that in other embodiments, when the two upper bridge arm switching tubes Q1 and the two lower bridge arm switching tubes Q2 form a full bridge circuit, the full bridge circuit can be driven to operate by the two interlocking driving circuits 100 provided in the embodiments of the present application.
Referring to fig. 3, in an embodiment of the present application, the interlocking driving circuit 100 further includes a power supply module 40 for supplying power to the driving module 10. The power supply module 40 includes a first power supply unit 41 and a second power supply unit 42. The driving module 10 includes a first power pin VB and a second power pin VCC. The first power supply unit 41 and the second power supply unit 42 are respectively configured to convert the voltage of the voltage source V3 into a corresponding first voltage V1 and a second voltage V2, so as to respectively supply power to the first power supply pin VB and the second power supply pin VCC.
Further, the driving module 10 further includes a first reference pin VS and a second reference pin COM. The first power supply pin VB is electrically connected to an output terminal of the first power supply unit 41 for receiving the first voltage V1. The first reference pin VS is grounded. A first capacitor C1 and a second capacitor C2 are connected in parallel between the first power pin VB and the first reference pin VS. The second power supply pin VCC is electrically connected to an output terminal of the second power supply unit 42 for receiving the second voltage V2. The second reference pin COM is grounded. A third capacitor C3 and a fourth capacitor C4 are connected in parallel between the second power supply pin VS and the second reference pin COM. Therefore, the voltage stabilizing effect can be achieved and the interference can be reduced by arranging the first capacitor C1 to the fourth capacitor C4.
The first power supply unit 41 includes a first voltage conversion chip 411, and the first voltage conversion chip 411 receives a voltage input by the voltage source V3 and converts the voltage into a corresponding first voltage V1 to supply power to the driving module 10 through a first power pin VB of the driving module 10. Similarly, the second power supply unit 42 includes a second voltage conversion chip 412, and the second voltage conversion chip 412 receives the voltage input by the voltage source V3 and converts the voltage into a corresponding second voltage V2 to supply power to the driving module 10 through the second power pin VCC of the driving module 10.
It is understood that the power supply module 40 is not limited to the circuit design shown in fig. 3, and in other embodiments, the corresponding power supply module 40 may be provided according to different driving modules 10.
The present application also provides an electronic device (not shown). The electronic device includes an upper arm switching tube Q1, a lower arm switching tube Q2, and an interlock driving circuit 100. The interlocking driving circuit 100 is used for driving the upper bridge arm switching tube Q1 and the lower bridge arm switching tube Q2, and the upper bridge arm switching tube Q1 and the lower bridge arm switching tube Q2 are not turned on at the same time.
In addition, those of ordinary skill in the art will recognize that the above embodiments are presented for purposes of illustration only and are not intended to be limiting, and that suitable modifications and variations of the above embodiments are within the scope of the disclosure of the present application.
Claims (10)
1. An interlocking driving circuit is used for driving an upper bridge arm switch tube and a lower bridge arm switch tube and is characterized by comprising a driving module, a current limiting module and an interlocking module which are electrically connected in sequence, wherein the interlocking module is also electrically connected to the upper bridge arm switch tube and the lower bridge arm switch tube,
the driving module is used for outputting a first driving signal and a second driving signal to the interlocking module through the current limiting module;
the current limiting module is used for protecting the interlocking module;
the interlocking module is used for controlling the upper bridge arm switching tube and the lower bridge arm switching tube to be not conducted simultaneously according to the first driving signal and the second driving signal.
2. The interlocking drive circuit of claim 1, wherein the interlocking module comprises a first interlocking unit and a second interlocking unit, the first interlocking unit is electrically connected between the current-limiting module and the upper bridge arm switching tube, the second interlocking unit is electrically connected between the current-limiting module and the lower bridge arm switching tube, the first interlocking unit is used for controlling the upper bridge arm switching tube to be turned on or off according to the first drive signal and the second drive signal, the second interlocking unit is used for controlling the lower bridge arm switching tube to be turned on or off according to the first drive signal and the second drive signal, and the upper bridge arm switching tube and the lower bridge arm switching tube are not turned on at the same time.
3. The interlock driving circuit of claim 2, wherein the driving module includes a first output terminal and a second output terminal, the current limiting module includes a first current limiting unit and a second current limiting unit, the first end of the first current limiting unit is electrically connected to the first output terminal, the second end of the first current limiting unit is electrically connected to the first interlock unit and the second interlock unit, the first output terminal outputs the first driving signal to the first interlock unit and the second interlock unit through the first current limiting unit, the first end of the second current limiting unit is electrically connected to the second output terminal, the second end of the second current limiting unit is electrically connected to the first interlock unit and the second interlock unit, and the second output terminal outputs the second driving signal to the first interlock unit and the second interlock unit through the second current limiting unit.
4. The interlock driving circuit of claim 3 wherein the first interlock unit comprises a first switch tube, a first diode, and a second switch tube, a first end of the first switch tube is electrically connected to a second end of the first current limiting unit, a second end of the first switch tube is electrically connected to a second end of the second current limiting unit, a third end of the first switch tube is grounded, an anode of the first diode is electrically connected to the first end of the first switch tube, a cathode of the first diode is electrically connected to a second end of the upper bridge arm switch tube, a first end of the second switch tube is electrically connected between a cathode of the first diode and the upper bridge arm switch tube, a second end of the second switch tube is electrically connected between the first end of the second switch tube and an anode of the first diode, and a third end of the second switch tube is electrically connected between the third end of the first switch tube and the ground.
5. The interlock driving circuit of claim 4, wherein the first switching tube is an NMOS tube, a first end of the first switching tube is a drain, a second end of the first switching tube is a gate, and a third end of the first switching tube is a source; the second switching tube is a PNP triode, the first end of the second switching tube is an emitter, the second end of the second switching tube is a base, and the third end of the second switching tube is a collector.
6. The interlock driving circuit of claim 3 wherein the second interlock unit comprises a third switching tube, a second diode and a fourth switching tube, the first end of the third switching tube is electrically connected to the second end of the second current limiting unit, the second end of the third switching tube is electrically connected to the second end of the first current limiting unit, the third end of the third switching tube is grounded, the anode of the second diode is electrically connected to the first end of the third switching tube, the cathode of the second diode is electrically connected to the second end of the lower bridge arm switching tube, the first end of the fourth switching tube is electrically connected between the cathode of the second diode and the lower bridge arm switching tube, the second end of the fourth switching tube is electrically connected between the first end of the fourth switching tube and the anode of the second diode, and the third end of the fourth switching tube is electrically connected between the third end of the third switching tube and the ground.
7. The interlock driving circuit of claim 6, wherein said second interlock unit further comprises a first voltage dividing resistor and a second voltage dividing resistor, wherein said second end of said third switching tube is electrically connected to said second end of said first current limiting unit through said first voltage dividing resistor, and wherein said second end of said third switching tube is further grounded through said second voltage dividing resistor.
8. The interlock driving circuit of claim 6 wherein the third switching tube is an NMOS tube, the first end of the third switching tube is a drain, the second end of the third switching tube is a gate, and the third end of the third switching tube is a source; the fourth switching tube is a PNP triode, the first end of the fourth switching tube is an emitter, the second end of the fourth switching tube is a base, and the third end of the fourth switching tube is a collector.
9. The interlock driving circuit of claim 3, wherein the first current limiting unit comprises a first current limiting resistor, the second current limiting unit comprises a second current limiting resistor, and a first end of the first current limiting resistor is electrically connected to the first output terminal, a second end of the first current limiting resistor is electrically connected to the first interlock unit and the second interlock unit, a first end of the second current limiting resistor is electrically connected to the second output terminal, and a second end of the second current limiting resistor is electrically connected to the first interlock unit and the second interlock unit.
10. An electronic device comprising an upper leg switch tube, a lower leg switch tube, and an interlock drive circuit according to any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223518857.1U CN219107285U (en) | 2022-12-28 | 2022-12-28 | Interlocking drive circuit and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223518857.1U CN219107285U (en) | 2022-12-28 | 2022-12-28 | Interlocking drive circuit and electronic equipment |
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| Publication Number | Publication Date |
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| CN219107285U true CN219107285U (en) | 2023-05-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202223518857.1U Active CN219107285U (en) | 2022-12-28 | 2022-12-28 | Interlocking drive circuit and electronic equipment |
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| CN (1) | CN219107285U (en) |
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- 2022-12-28 CN CN202223518857.1U patent/CN219107285U/en active Active
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