CN113823683A - HEMT device based on double heterojunction and composite passivation layer and preparation method thereof - Google Patents
HEMT device based on double heterojunction and composite passivation layer and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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Abstract
The invention discloses a HEMT device based on a double heterojunction and a composite passivation layer and a preparation method thereof, wherein the preparation method comprises the following steps: performing ion implantation on the upper surface of the first substrate to form a second substrate; forming a bonding interlayer on the upper surface of the second substrate, and mixing the beta-Ga2O3Transferring to the upper surface of the bonding intermediate layer to form a heterojunction substrate; growing a layer of beta-Ga on the upper surface of the heterojunction substrate2O3As a buffer layer; sequentially growing a secondary barrier layer, a first doping layer, a first heterojunction layer, a quantum well layer, a second heterojunction layer, a second doping layer and a primary barrier layer on the upper surface of the buffer layer; performing ion implantation on two sides of the upper surface of the main barrier layer to form a source electrode ohmic contact region and a drain electrode ohmic contact region; forming a source electrode on the source electrode ohmic contact region and a drain electrode on the drain electrode ohmic contact region; sequentially growing an oxide layer and a dielectric layer on the upper surface of the main barrier layer; betweenForming a grid electrode on the layer; and growing a passivation layer on the upper surface of the dielectric layer, and etching the dielectric layer and two sides of the passivation layer.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to an HEMT device based on a double heterojunction and a composite passivation layer and a preparation method thereof.
Background
β-Ga2O3As a new generation of semiconductor materials, due to beta-Ga2O3The forbidden band width and the theoretical breakdown electric field intensity of the silicon nitride are both higher than those of SiC and GaN, and the silicon nitride is resistant to high temperature and high temperatureThe pressure and the radiation resistance are superior to SiC and GaN, so that the beta-Ga2O3Is considered to be suitable for preparing next generation power devices such as diodes, field effect transistors and the like.
However, in high power or high frequency applications, β -Ga2O3The substrate has the problems of insufficient Electron transfer rate, low thermal conductivity and the like, so that the self-heating effect is serious, and the performance of a High Electron Mobility Transistor (HEMT) device is greatly influenced.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides an HEMT device based on a double heterojunction and a composite passivation layer and a preparation method thereof. The technical problem to be solved by the invention is realized by the following technical scheme:
the first embodiment of the invention provides a preparation method of an HEMT device based on a double heterojunction and a composite passivation layer, which comprises the following steps:
providing a first substrate, and performing ion implantation on the upper surface of the first substrate to form a second substrate;
forming a bonding interlayer on the upper surface of the second substrate, and mixing beta-Ga2O3Transferred to the upper surface of the bonding interlayer, for beta-Ga2O3Thinning the layer to form a heterojunction substrate;
growing a layer of beta-Ga on the upper surface of the heterojunction substrate2O3As a buffer layer;
sequentially growing a secondary barrier layer, a first doping layer, a first heterojunction layer, a quantum well layer, a second heterojunction layer, a second doping layer and a primary barrier layer on the upper surface of the buffer layer;
performing ion implantation on two sides of the upper surface of the main barrier layer to form a source electrode ohmic contact region and a drain electrode ohmic contact region; the source electrode ohmic contact region and the drain electrode ohmic contact region extend to the buffer layer;
forming a source electrode on the source electrode ohmic contact region, and forming a drain electrode on the drain electrode ohmic contact region;
growing an oxide layer on the upper surface of the main barrier layer, and growing a dielectric layer on the upper surface of the oxide layer;
forming a grid electrode on the dielectric layer, and covering the grid electrode with a material which is the same as that of the dielectric layer;
and growing a passivation layer on the upper surface of the dielectric layer, and etching the dielectric layer and two sides of the passivation layer to expose at least one part of the upper surfaces of the source electrode and the drain electrode.
Optionally, the material of the oxide layer includes HfO2、HfxAl1-xO、HfxSi1-xO、HfxZr1-xO、La2O3Or ZrO2The thickness of the oxide layer is 20 nm-30 nm.
Optionally, the material of the first substrate includes: beta-Ga2O3Si, SiC or sapphire.
Optionally, the reaction of beta-Ga2O3Transferred to the upper surface of the bonding interlayer, for beta-Ga2O3The layer is thinned to form a heterojunction substrate, comprising:
beta-Ga with the thickness of 300 nm-800 nm2O3Transferring to an upper surface of the bonding interlayer;
etching process is utilized to etch beta-Ga2O3The layer is thinned to less than 100nm to form a heterojunction substrate.
Optionally, the process for forming the buffer layer includes:
growing 100 nm-500 nm beta-Ga by molecular beam epitaxial growth process in oxygen plasma atmosphere2O3As a buffer layer.
Optionally, the ion implantation process is performed on the upper surface of the first substrate, the type of implanted ions includes helium, iron, or magnesium, and the implantation angle is 7 °.
Optionally, the materials of the secondary barrier layer and the primary barrier layer include beta- (Al)xGa1-x)2O3X is in the range of 0.1-0.5, and the growth temperature is in the range of700℃～750℃；
The materials of the first and second heterojunction layers include: beta-Ga2O3And beta- (Al)xGa1-x)2O3The growth temperature range is 700-750 ℃;
the doping materials of the first doping layer and the second doping layer comprise silicon doping, and the growth temperature range is 870-900 ℃.
Optionally, the process of forming the source ohmic contact region or the drain ohmic contact region includes:
performing ion implantation on two sides of the upper surface of the main barrier layer, wherein the implanted ions comprise silicon, tin or germanium, the range of the implantation angle is 0-90 degrees, the implantation energy is 20-300 keV, and the implantation dosage is 1 multiplied by 1014cm-3～1×1015cm-3；
Annealing for 30-60 min under the atmosphere of neon or argon, wherein the annealing temperature range is 900-1050 ℃, and the doping concentration of the formed source electrode ohmic contact region or the drain electrode ohmic contact region is more than 1 multiplied by 1019cm-3。
Optionally, the thickness of the dielectric layer is 80nm to 120nm, and the material of the dielectric layer includes: BaTiO 23、SrTiO3、LaMnO3、KTaO3Or BiFeO3。
The second embodiment of the present invention further provides a HEMT device based on a double heterojunction and a composite passivation layer, including:
the heterojunction substrate, the buffer layer, the secondary barrier layer, the first doping layer, the first heterojunction layer, the quantum well layer, the second heterojunction layer, the second doping layer and the main barrier layer are sequentially formed from bottom to top; the heterojunction substrate and the buffer layer have the same length, the secondary barrier layer, the first doping layer, the first heterojunction layer, the quantum well layer, the second heterojunction layer, the second doping layer and the primary barrier layer have the same length, and the heterojunction substrate has a length greater than that of the secondary barrier layer; wherein the heterojunction substrate comprisesA first substrate, a second substrate, a bonding interlayer and beta-Ga sequentially formed on the substrate2O3A layer;
the source electrode ohmic contact region and the drain electrode ohmic contact region are positioned on two sides of the main barrier layer and extend to the buffer layer;
the source electrode is positioned on the upper surface of the source electrode ohmic contact region;
the drain electrode is positioned on the upper surface of the drain electrode ohmic contact region;
an oxide layer on the primary barrier layer;
the dielectric layer and the passivation layer are sequentially positioned on the oxide layer, and the dielectric layer covers at least one part of the upper surfaces of the source electrode and the drain electrode;
and the grid electrode is positioned in the dielectric layer and is close to the source electrode.
Compared with the prior art, the technical scheme provided by the invention has the following advantages:
the invention provides an HEMT device based on a double heterojunction and a composite passivation layer and a preparation method thereof, wherein a heterojunction substrate adopts beta-Ga2O3The double heterojunction structure improves the electron transmission rate and the channel mobility of the device, thereby improving the working current of the device. The scheme of the invention can realize beta-Ga2O3The heterogeneous integration of the substrate improves the heat dissipation, the working temperature and the preparation cost of the device, inhibits the self-heating effect and improves the high-temperature reliability of the device.
In addition, the composite passivation layer structure formed by the oxide layer and the dielectric layer can improve the electric field distribution in the device, further relieve the electric field concentration effect and greatly improve the breakdown voltage.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
Fig. 1 to 13 are schematic structural diagrams corresponding to steps of a method for manufacturing an HEMT device based on a double heterojunction and a composite passivation layer according to a first embodiment of the present invention;
fig. 14 is a top view of a HEMT device based on a double heterojunction and composite passivation layer according to a first embodiment of the present invention;
fig. 15 to 19 show a photolithography plate used in a method for manufacturing a HEMT device based on a double heterojunction and a composite passivation layer according to a first embodiment of the present invention.
Detailed Description
In order to improve the high-temperature reliability of the device, embodiments of the present invention provide a HEMT device based on a double heterojunction and a composite passivation layer and a method for manufacturing the HEMT device, and the scheme provided in the embodiments will be described in detail below with reference to the accompanying drawings.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in various embodiments of the invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
A first embodiment of the present invention provides a method for manufacturing an HEMT device based on a double heterojunction and a composite passivation layer, referring to fig. 1 to 19, fig. 1 to 13 are schematic structural diagrams corresponding to the steps of the method for manufacturing an HEMT device based on a double heterojunction and a composite passivation layer according to the first embodiment of the present invention, fig. 14 is a top view of an HEMT device based on a double heterojunction and a composite passivation layer according to the first embodiment of the present invention, and fig. 15 to 19 are photolithography masks used in the method for manufacturing an HEMT device based on a double heterojunction and a composite passivation layer according to the first embodiment of the present invention, and the method includes the following steps:
step one, referring to fig. 1, a first substrate 101a is provided, and ion implantation is performed on an upper surface of the first substrate 101a to form a second substrate 101 b.
Wherein the material of the first substrate 101a may include beta-Ga2O3The thickness is 200-600 μm, and the size can be 1-6 inches.
A pre-treatment cleaning of the first substrate 101a is also required before ion implantation is performed on the upper surface of the first substrate 101 a.
First, the organic cleaning of the first substrate 101a may include the steps of:
in the first step, methanol is used for soaking for 3 min.
And secondly, soaking for 3min by using acetone.
And thirdly, soaking for 3min by using methanol.
And fourthly, washing for 3min by using deionized water.
And fifthly, washing for 5min by using flowing deionized water.
Next, the acid cleaning of the first substrate 101a may include the steps of:
in the first step, deionized water is used for soaking, and the temperature is heated to 90 ℃.
And secondly, preparing an SPM solution, and soaking the SPM solution in the SPM solution for 5min, wherein the SPM solution is prepared from deionized water, a 30% hydrogen peroxide solution and a 96% concentrated sulfuric acid solution in a ratio of 1:1: 4. Or preparing a Piranha solution and soaking the Piranha solution in the Piranha solution for 1min, wherein the Piranha solution is prepared by using a 30% hydrogen peroxide solution and a 98% concentrated sulfuric acid solution in a ratio of 1: 3.
And thirdly, soaking the fabric by using deionized water, heating the fabric to 90 ℃, and then cooling the fabric to room temperature.
Step two, referring to fig. 2 to 4, forming a bonding interlayer 101c on the upper surface of the second substrate 101 b; and reacting beta-Ga2O3Transferred to the upper surface of the bonding intermediate layer 101c for beta-Ga2O3The layer 101d is thinned to form the heterojunction substrate 101.
Here, with continued reference to fig. 2, the first substrate 101a, the second substrate 101b, and the bonding intermediate layer 101c collectively constitute a foreign substrate.
In the embodiment of the invention, the intelligent stripping technology is utilized to strip beta-Ga2O3Transferred to the upper surface of the bonding intermediate layer 101 c. The specific process steps of the smart cut technology are referred to in the prior art and are not described in detail herein.
In the embodiment of the invention, the etching process can be utilized to carry out the etching on the beta-Ga2O3The layer 101d is thinned, and the specific process will be described in detail later.
After the heterojunction substrate 101 is formed, the method further includes: and (3) carrying out ion bombardment for 5-20 min by adopting a plasma gluing machine under the action of oxygen plasma to achieve the purpose of cleaning impurities on the surface of the heterojunction substrate 101. Wherein, the power range of the plasma bombardment can be 200W-400W.
In another embodiment, the cleaning process in step one can be combined with an acid-base solution for cleaning.
Step three, referring to fig. 5, a layer of beta-Ga is grown on the upper surface of the heterojunction substrate 1012O3As a buffer layer 102.
Optionally, the buffer layer 102 is unintentionally doped β -Ga2O3And (3) a layer.
Step four, referring to fig. 6, the sub-barrier layer 103, the first doping layer 104, the first heterojunction layer 105, the quantum well layer 106, the second heterojunction layer 107, the second doping layer 108, and the main barrier layer 109 are sequentially grown on the upper surface of the buffer layer 102.
Specifically, the growth sequence may comprise the following steps:
step 1, growing 4 nm-5 nm beta- (Al) on the upper surface of the buffer layer 102 by adopting an oxygen plasma assisted Molecular Beam Epitaxy (MBE) processxGa1-x)2O3Layer, forming the sub-barrier layer 103.
And 2, growing a Si doped layer for 1.8-2 s on the upper surface of the secondary barrier layer 103 by using a Si delta-doping process to form a first doped layer 104 with the thickness of 2-3 nm.
Step 3, growing 4 nm-5 nm beta- (Al) on the upper surface of the first doping layer 104xGa1-x)2O3A layer of a material selected from the group consisting of,the first heterojunction layer 105 is formed.
Step 4, growing 3nm of beta-Ga on the upper surface of the first heterojunction layer 1052O3And a quantum well layer forming the quantum well layer 106.
Step 5 of growing 3nm to 5nm of beta- (Al) on the upper surface of the quantum well layer 106xGa1-x)2O3Layer, forming a second heterojunction layer 107.
And 6, growing a Si doped layer for 3s on the upper surface of the second heterojunction layer 107 by using a Si delta-doting doping process to form a second doped layer 108.
Step 7, growing a certain thickness of beta- (Al) on the upper surface of the second doped layer 108xGa1-x)2O3Barrier layers, forming a main barrier layer 109.
Wherein, beta- (Al)xGa1-x)2O3Layer and beta-Ga2O3The growth temperature of the layer is 700-750 ℃, and the growth temperature of the Si doped layer is 870-900 ℃.
The MBE process can control the Al component x of the film by adjusting the flux of the Al source, the range of the Al component x is 0.1-0.5, and the Al component effect and beta- (Al) arexGa1-x)2O3The thickness of the barrier layer is relevant. Specifically, the component x is preferably 0.17 when the thickness is 15nm to 30nm, the component x is preferably 0.25 when the thickness is 40nm to 60nm, and the component x is preferably 0.1 to 0.15 when the thickness is 5nm to 10 nm. The thickness of the barrier layer is chosen to significantly affect the device threshold voltage, and a thin barrier layer is beneficial for implementation of an enhancement mode device. Under the conditions, the device can realize larger two-dimensional electron gas concentration and channel mobility, and further improve the performance of the device.
Step five, referring to fig. 7 and fig. 15, performing ion implantation on both sides of the upper surface of the main barrier layer 109 to form a source ohmic contact region 111 and a drain ohmic contact region 112; the source ohmic contact region 111 and the drain ohmic contact region 112 extend to the buffer layer 102.
Ion implantation is performed in the hollow area by using a photolithography plate as shown in fig. 15, so as to form a source ohmic contact region 111 and a drain ohmic contact region 112.
Step six, referring to fig. 8 and 16, a source electrode 121 is formed on the source ohmic contact region 111, and a drain electrode 122 is formed on the drain ohmic contact region 112.
The material of the source electrode 121, the drain electrode 122, or the gate electrode 123 includes any two materials of gold, aluminum, titanium, tin, germanium, and indium.
The source electrode 121 and the drain electrode 122 are grown by a magnetron sputtering process using a photolithography plate as shown in fig. 16, and rapid thermal annealing is performed to form an ohmic contact. Wherein, the magnetron sputtering comprises a physical vapor deposition or molecular beam evaporation process.
The sputtering target material selects gold and titanium with the mass ratio purity of more than 99.99 percent, and argon with the mass percentage purity of 99.999 percent is used as sputtering gas and is introduced into the sputtering cavity. Before sputtering, the cavity of the magnetron sputtering equipment is cleaned for 5min by pure argon gas, and then vacuumized. Under vacuum degree of 6X 10-4Pa～1.3×10-3Pa, argon flow 20cm3/s～30cm3And/s, preparing a source electrode 121 and a drain electrode 122 under the conditions that the target base distance is 10cm and the working power is 20W-100W, wherein the thickness of the gold electrode is 100 nm-300 nm. And (3) performing rapid thermal annealing after sputtering is finished, and annealing for 30 s-2 min at the temperature of 450-500 ℃ in a nitrogen or argon environment to form ohmic contact.
In an alternative embodiment, the metal of the source electrode 121 or the drain electrode 122 may be a 2-layer structure composed of different elements, such as Au, Al, Ti, etc.
In another alternative embodiment, a transparent oxide film (TCO) with a thickness of 5nm to 20nm, such as ITO, FTO, AZO, etc., is inserted between the semiconductor layer and the metal layer, and the source electrode 121 or the drain electrode 122 may be replaced by Al, Ti, Ni, Ag, Pt, etc. Wherein, the chemical properties of Au, Ag and Pt are stable; the cost of Al, Ti and Ni is low.
Preferably, the Ti/Au structure or the inserted TCO insertion layer can reduce the contact resistance and improve the working current.
Step seven, referring to fig. 9 to 10, an oxide layer 131 is grown on the upper surface of the main barrier layer 109, and a dielectric layer 132 is grown on the upper surface of the oxide layer 131.
Wherein, the oxide layer 131 comprises alumina with a thickness of 10 nm-20 nm.
Referring to FIG. 9, Al of 10nm to 20nm is grown by using an Atomic Layer Deposition (ALD) process2O3Growth temperature is 175-250 ℃, and trimethyl aluminum and O are used2To reflect the precursor, N2Or Ar is inert carrier gas, and the oxide layer 131 is grown.
It should be noted that in the process of growing the oxide layer 131, the oxide layer 131 is also grown on the source electrode 121 and the drain electrode 122, and the oxide layer 131 on the source electrode 121 and the drain electrode 122 needs to be etched by using a photolithography plate as shown in fig. 16 before the dielectric layer 132 is grown.
Step eight, referring to fig. 11 and fig. 17, a gate electrode 123 is formed on the dielectric layer 132, and the gate electrode 123 is covered with a material identical to that of the dielectric layer 132.
A Ti/Pt metal gate 123 was grown by a magnetron sputtering process using a photolithography plate as shown in fig. 17.
The thickness of the gate 123 can be 200 nm-300 nm, the gate 123 can be in a 2-4-layer structure formed by elements such as Au, Al, Ti, Ni, Pt and Cr, the first layer can improve the metal adhesion by adopting 2 nm-4 nm Ti or Cr, and the rest layers can improve the threshold voltage of the device by adopting elements such as Au, Pt and Ni with high metal work functions.
In another embodiment, polysilicon heavily doped with P, As, Sb, etc. may be used As the gate 123.
Step nine, referring to fig. 12 to 13 and 18, a passivation layer 133 is grown on the upper surface of the dielectric layer 132, and both sides of the dielectric layer 132 and the passivation layer 133 are etched to expose at least a portion of the upper surfaces of the source electrode 121 and the drain electrode 122.
Growing the surface passivation layer 133 by using a plasma enhanced CVD process, wherein the material of the passivation layer 133 comprises SiO2The thickness is 200 nm-500 nm.
After the passivation layer 133 is grown, the photolithography plate shown in fig. 18 is used to remove a portion of the dielectric layer and the passivation layer 133 on the source electrode 121 and the drain electrode 122 through an Inductively coupled Plasma Etching (ICP) process or a Reactive Ion Etching (RIE) process, so as to obtain the device structure shown in fig. 13.
After the source electrode 121, the drain electrode 122 and the gate electrode 123 are prepared, the method further includes: on the structure formed in the ninth step, a photolithography plate shown in fig. 19 is used to grow a metal interconnection layer with a thickness of 0.5 μm to 2 μm by using a molecular beam evaporation process, wherein the material of the metal interconnection layer includes Au or Al, and a top view of the structure after the metal interconnection layer is formed is shown in fig. 14.
In the method for manufacturing an HEMT device based on a double heterojunction and a composite passivation layer according to the first embodiment of the present invention, a heterojunction substrate adopts β -Ga2O3The double heterojunction structure improves the electron transmission rate and the channel mobility of the device, thereby improving the working current of the device. The scheme of the invention can realize beta-Ga2O3The heterogeneous integration of the substrate improves the heat dissipation, the working temperature and the preparation cost of the device, inhibits the self-heating effect and improves the high-temperature reliability of the device. In addition, the composite passivation layer structure formed by the oxide layer and the dielectric layer can improve the electric field distribution in the device, further relieve the electric field concentration effect and greatly improve the breakdown voltage.
Preferably, the material of the oxide layer 131 includes HfO2、HfxAl1-xO、HfxSi1-xO、HfxZr1-xO、La2O3Or ZrO2The thickness of the oxide layer 131 is 20nm to 30 nm.
Wherein, HfO2、HfxAl1-xO (x ranges from 0.2 to 0.3) and HfxSi1-xO (x ranges from 0.3 to 0.4) and HfxZr1-xThe value range of O (x) is 0.5-0.7), and La2O3Or ZrO2The materials are all high dielectric constant materials>20。
The ALD process is utilized to grow the oxide layer 131, and the growth temperature is 650-750 ℃.
It can be understood that the oxide layer is made of a material with a high dielectric constant, which can improve the gate control capability of the device and reduce the gate leakage.
In the embodiment of the present invention, the material of the first substrate 101a includes: beta-Ga2O3Si, SiC or sapphire.
Preferably, the material of the first substrate 101a is beta-Ga2O3. Due to beta-Ga2O3The forbidden band width of the double-gate device is 4.7-4.9 eV, the theoretical breakdown electric field is 8MV/cm, and the forbidden band width and the theoretical breakdown electric field of the double-gate device are far beyond those of SiC and GaN, so that the device performance of the double-gate device can be effectively improved, and compared with SiC and GaN substrates, beta-Ga is used as the substrate2O3The price of (2) is low.
In the embodiment of the present invention, the ion implantation process is performed on the upper surface of the first substrate 101a, and the implanted ions include helium, iron, or magnesium, and the implantation angle is 7 °.
The implantation angle of the ion implantation is 7 degrees, which is beneficial to the bonding of subsequent foreign substrates.
In an embodiment of the present invention, the process of forming the bonding interlayer 101c may include: the bonding interlayer 101c is formed by an ALD process and annealed to migrate and accumulate implanted ions for subsequent lift-off.
In an alternative embodiment, the process of forming the bonding interlayer 101c may further include: and forming the bonding intermediate layer 101c by Ar ion bombardment, and annealing to enable implanted ions to migrate and accumulate so as to be beneficial to subsequent stripping.
Wherein the material of the bonding interlayer 101c comprises aluminum oxide, and the thickness of the bonding interlayer 101c is 5nm to 30 nm.
In an embodiment of the present invention, forming the heterojunction substrate 101 may include the following steps:
step 1, adding beta-Ga with the thickness of 300 nm-800 nm2O3Transferred to the upper surface of the bonding intermediate layer 101 c.
Wherein, the following SOI structure wafers are formed: beta-Ga2O3/Al2O3/Si、β-Ga2O3/Al2O3/4H-SiC、β-Ga2O3/Al2O3/6H-SiC、β-Ga2O3/Al2O3/3C-SiC、β-Ga2O3/Al2O3/Diamond、β-Ga2O3/4H-SiC、β-Ga2O3/6H-SiC、β-Ga2O3/3C-SiC、β-Ga2O3/Al2O3c-Sapphire and beta-Ga2O3c-Sapphire et al.
It can be understood that the preparation cost of the device can be reduced by selecting the Si substrate or the c-sapphire substrate; the sapphire substrate can also reduce the film damage caused by stripping, thereby improving the stability of the device; the SiC substrate and the Diamond substrate can improve the heat dissipation capacity of the device, inhibit the self-heating effect and improve the working temperature and high-temperature reliability of the device.
Step 2, etching process is utilized to etch beta-Ga2O3The layer 101d is thinned to less than 100nm to form the heterojunction substrate 101.
Wherein, beta-Ga2O3The thickness of layer 101d may be tested by optical ellipsometry.
Alternatively, the β -Ga may be treated using an ICP process, an RIE process, or a Chemical Mechanical Polishing (CMP) process2O3Layer 101d is etched.
Specifically, the etching conditions of ICP etching or RIE etching are: 99.999% Cl2、BCl3、Ar、Cl2/BCl3、Cl2/Ar/BCl3And (3) waiting for different mixed gas atmospheres, wherein the mixing ratio is 35:5, 25:15, 20:20 and 15:20, the ICP power is 300-900W, the RF power is 15-100W, and the etching temperature can be selected to be room temperature-80 ℃. The etching conditions of the wet etching process are as follows: 10 to 50 percent of HF (room temperature) at room temperature; or 40 to 70 percent of HNO at the temperature of 60 DEG C3(ii) a Or 80-85% of H at 80 DEG C3PO4(ii) a Or different solutions such as UV irradiation KOH and the like under the condition of 95 ℃ by a 254nmHg lamp.
Under the etching conditions, the beta-Ga can be stably and uniformly etched2O3。
In an embodiment of the present invention, the process of forming the buffer layer 102 may include:
in the atmosphere of oxygen plasma, the beta-Ga with the grain size of 100 nm-500 nm is grown by using the MBE process2O3As a buffer layer 102.
Alternatively, the growth process may be replaced by Low Pressure Chemical Vapor Deposition (LPCVD), Metal-oxide Chemical Vapor Deposition (MOCVD), or Pulsed Laser Deposition (PLD).
The above-mentioned processes all adopt the mixed gas atmosphere of oxygen and argon, the growth temperature of MBE process is 650-800 deg.C, the growth temperature of CVD process is 700-800 deg.C, and the growth temperature of PLD process is 500-800 deg.C.
In the embodiment of the invention, the materials of the secondary barrier layer and the primary barrier layer comprise beta- (Al)xGa1-x)2O3The value range of x is 0.1-0.5, and the growth temperature range is 700-750 ℃.
The materials of the first and second heterojunction layers include: beta-Ga2O3And beta- (Al)xGa1-x)2O3The growth temperature range is 700-750 ℃.
The doping materials of the first doping layer and the second doping layer comprise silicon doping, and the growth temperature range is 870-900 ℃.
In an embodiment of the present invention, the process of forming the source ohmic contact region 111 or the drain ohmic contact region 112 may include the following steps:
step 1, performing ion implantation on both sides of the upper surface of the main barrier layer 109, the implanted ions including silicon, tin, or germanium, the implantation angle ranging from 0 ° to 90 °, the implantation energy ranging from 20keV to 300keV, and the implantation dose of 1 × 1014cm-3～1×1015cm-3。
Step 2, annealing for 30-60 min under the atmosphere of neon or argon, wherein the annealing temperature range is 900-1050 ℃, and the doping concentration of the formed source electrode ohmic contact region 111 or drain electrode ohmic contact region 112 is more than 1 multiplied by 1019cm-3。
In the embodiment of the present invention, the thickness of the dielectric layer 132 is 80nm to 120nm, and the material of the dielectric layer 132 includes: BaTiO 23、SrTiO3、LaMnO3、KTaO3Or BiFeO3。
The dielectric constant of the material of the dielectric layer 132 is greater than 40.
Specifically, a dielectric layer 132 with the thickness of 80nm to 120nm is grown by adopting radio frequency magnetron sputtering, and the growth temperature is 650 ℃ to 750 ℃.
BaTiO with the mass ratio purity of more than 99.9 percent is selected as the sputtering target material3Argon with the purity of 99.999 percent by mass is used as sputtering gas and is introduced into the sputtering cavity. Before sputtering, the cavity of the magnetron sputtering equipment is cleaned for 5min by pure argon gas, and then vacuumized. Under a vacuum of 1X 10-4Pa～2×10-3Pa, argon flow 20cm3/s～30cm3And preparing the dielectric layer 132 under the conditions that the target base distance is 20cm and the working radio frequency power is 50W-100W.
In the embodiment of the present invention, the material of the passivation layer 133 may further include Si3N4Or a low dielectric constant dielectric layer/polymer layer bilayer structure. Wherein the low dielectric constant medium may comprise SiO2Or Si3N4The polymer layer is prepared by combining a surface spin coating process with a 150-200 ℃ solidification forming or PVD process, and can be selected from High Impact Polystyrene (HIPS), Polychlorotrifluoroethylene (PCTFE), polymethyl methacrylate (PMMA), fluorinated ethylene propylene copolymer (FEP), soluble Polytetrafluoroethylene (PFA), Polytetrafluoroethylene (PTFE), poly-4-methyl-1-pentene (PMP), High Density Polyethylene (HDPE), Low Density Polyethylene (LDPE), Linear Low Density Polyethylene (LLDPE), ethylene-vinyl acetate copolymer (EVA), Styrene Acrylonitrile (SAN), ethylene chlorotrifluoroethylene copolymer (ECTFE), ethylene-tetrafluoroethylene copolymer (ETFE) and the like.
The passivation layer 133 has a double-layer structure, so that air breakdown on the surface of the device can be effectively relieved.
A second embodiment of the present invention provides a HEMT device based on a double heterojunction and a composite passivation layer, which may be formed by the preparation method provided in any of the above embodiments, with reference to fig. 13 and 14, and includes:
a heterojunction substrate 101, a buffer layer 102, a sub-barrier layer 103, a first doping layer 104, a first heterojunction layer 105, a quantum well layer 106, a second heterojunction layer 107, a second doping layer 108, and a main barrier layer 109 formed in this order from bottom to top; the heterojunction substrate 101 and the buffer layer 102 have the same length, the secondary barrier layer 103, the first doping layer 104, the first heterojunction layer 105, the quantum well layer 106, the second heterojunction layer 107, the second doping layer 108, and the primary barrier layer 109 have the same length, and the heterojunction substrate 101 has a length greater than that of the secondary barrier layer 103;
a source ohmic contact region 111 and a drain ohmic contact region 112 located on both sides of the main barrier layer 109 and extending to the buffer layer 102;
a source electrode 121 on an upper surface of the source ohmic contact region 111;
a drain electrode 122 on an upper surface of the drain ohmic contact region 112;
an oxide layer 131 on the primary barrier layer 109;
a dielectric layer 132 and a passivation layer 133 sequentially disposed on the oxide layer 131, wherein the dielectric layer 132 covers at least a portion of the upper surfaces of the source 121 and the drain 122;
and the gate 123 is positioned in the dielectric layer 132 and close to the source 121.
Wherein the heterojunction substrate 101 comprises: a first substrate 101a, a second substrate 101b, a bonding interlayer 101c, and β -Ga formed in this order from bottom to top2O3Layer 101 d.
Alternatively, the material of the first substrate 101a may include β -Ga2O3Si, SiC or sapphire.
Preferably, the material of the first substrate 101a comprises beta-Ga2O3The thickness is 200-600 μm, and the size can be 1-6 inches.
Alternatively, the material of the bonding interlayer 101c may include alumina and have a thickness of 5nm to 30 nm.
Optionally, beta-Ga2O3The thickness of layer 101d is less than 100 nm.
OptionallyThe material of the buffer layer 102 may include beta-Ga2O3The thickness is 4nm to 5 nm.
Alternatively, the material of the sub-barrier layer 103 may include β - (Al)xGa1-x)2O3The thickness is 4 nm-5 nm, and the growth temperature is 700-750 ℃. Wherein the value range of x is 0.1-0.5.
Optionally, the material of the first doped layer 104 may include silicon doping, the thickness is 2nm to 3nm, and the growth temperature is 870 ℃ to 900 ℃.
Alternatively, the material of the first heterojunction layer 105 may include β -Ga2O3And beta- (Al)xGa1-x)2O3The thickness is 4 nm-5 nm, and the growth temperature is 700-750 ℃.
Alternatively, the material of the quantum well layer 106 may comprise beta-Ga2O3The thickness is 3nm, and the growth temperature is 700-750 ℃.
Alternatively, the material of the second heterojunction layer 107 may comprise beta-Ga2O3And beta- (Al)xGa1-x)2O3The thickness is 3 nm-5 nm, and the growth temperature is 700-750 ℃.
Optionally, the material of the second doped layer 108 may include silicon doping and the growth temperature is 870 ℃ to 900 ℃.
Optionally, the material of the main barrier layer 109 may include β - (Al)xGa1-x)2O3The growth temperature is 700-750 ℃.
Optionally, the doping concentration of the source ohmic contact region 111 or the drain ohmic contact region 112 is greater than 1 × 1019cm-3。
Optionally, the oxide layer 131 may include alumina, and has a thickness of 10nm to 20nm and a growth temperature of 175 ℃ to 250 ℃.
Optionally, the material of the dielectric layer 132 includes: BaTiO 23、SrTiO3、LaMnO3、KTaO3Or BiFeO3The thickness is 80 nm-120 nm, and the growth temperature is 650-750 ℃.
OptionalThe material of the passivation layer 133 may include SiO2The thickness is 200 nm-500 nm.
Alternatively, the material of the source electrode 121, the drain electrode 122, or the gate electrode 123 may include any two of gold, aluminum, titanium, tin, germanium, and indium.
Specifically, the metal of the source electrode 121 or the drain electrode 122 may be a 2-layer structure composed of different elements such as Au, Al, Ti, and the like.
In another alternative embodiment, a transparent oxide film (TCO) with a thickness of 5nm to 20nm, such as ITO, FTO, AZO, etc., is inserted between the semiconductor layer and the metal layer, and the source electrode 121 or the drain electrode 122 may be replaced by Al, Ti, Ni, Ag, Pt, etc. Wherein, the chemical properties of Au, Ag and Pt are stable; the cost of Al, Ti and Ni is low.
Preferably, the Ti/Au structure or the inserted TCO insertion layer can reduce the contact resistance and improve the working current.
The thickness of the gate 123 can be 200 nm-300 nm, the material of the gate 123 can be a 2-4-layer structure composed of elements such as Au, Al, Ti, Ni, Pt, Cr and the like, wherein the first layer adopts 2 nm-4 nm of Ti or Cr to improve the adhesion of metal, and the rest layers adopt elements such as Au, Pt, Ni and the like with high metal work function to improve the threshold voltage of the device.
In another embodiment, polysilicon heavily doped with P, As, Sb, etc. may be used As the gate 123.
Optionally, with continued reference to fig. 14, the method further includes: and a metal interconnection layer.
The metal interconnection layer is connected to the source electrode 121, the drain electrode 122 and the gate electrode 123, and the material of the metal interconnection layer may include Au or Al and has a thickness of 0.5 μm to 2 μm.
In a HEMT device according to a second embodiment of the present invention, a double-heterojunction and composite passivation layer is used as a heterojunction substrate, and β -Ga is used as a heterojunction substrate2O3The double heterojunction structure improves the electron transmission rate and the channel mobility of the device, thereby improving the working current of the device. The scheme of the invention can realize beta-Ga2O3Heterogeneous integration of substrate improves heat dissipation, working temperature and preparation cost of device, inhibits self-heating effect, and increases high temperature of deviceAnd (6) reliability.
In addition, the composite passivation layer structure formed by the oxide layer and the dielectric layer can improve the electric field distribution in the device, further relieve the electric field concentration effect and greatly improve the breakdown voltage.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A preparation method of an HEMT device based on a double heterojunction and a composite passivation layer is characterized by comprising the following steps:
providing a first substrate, and performing ion implantation on the upper surface of the first substrate to form a second substrate;
at the secondForming a bonding interlayer on the upper surface of the substrate, and mixing beta-Ga2O3Transferred to the upper surface of the bonding interlayer, for beta-Ga2O3Thinning the layer to form a heterojunction substrate;
growing a layer of beta-Ga on the upper surface of the heterojunction substrate2O3As a buffer layer;
sequentially growing a secondary barrier layer, a first doping layer, a first heterojunction layer, a quantum well layer, a second heterojunction layer, a second doping layer and a primary barrier layer on the upper surface of the buffer layer;
performing ion implantation on two sides of the upper surface of the main barrier layer to form a source electrode ohmic contact region and a drain electrode ohmic contact region; the source electrode ohmic contact region and the drain electrode ohmic contact region extend to the buffer layer;
forming a source electrode on the source electrode ohmic contact region, and forming a drain electrode on the drain electrode ohmic contact region;
growing an oxide layer on the upper surface of the main barrier layer, and growing a dielectric layer on the upper surface of the oxide layer;
forming a grid electrode on the dielectric layer, and covering the grid electrode with a material which is the same as that of the dielectric layer;
and growing a passivation layer on the upper surface of the dielectric layer, and etching the dielectric layer and two sides of the passivation layer to expose at least one part of the upper surfaces of the source electrode and the drain electrode.
2. The method for preparing a HEMT device based on double heterojunction and composite passivation layer according to claim 1, wherein the material of said oxide layer comprises HfO2、HfxAl1-xO、HfxSi1-xO、HfxZr1-xO、La2O3Or ZrO2The thickness of the oxide layer is 20 nm-30 nm.
3. The method for preparing a HEMT device based on double heterojunction and composite passivation layer according to claim 1, wherein the material of the first substrateThe material comprises the following steps: beta-Ga2O3Si, SiC or sapphire.
4. The method for preparing HEMT device based on double heterojunction and composite passivation layer according to claim 1, wherein the beta-Ga is2O3Transferred to the upper surface of the bonding interlayer, for beta-Ga2O3The layer is thinned to form a heterojunction substrate, comprising:
beta-Ga with the thickness of 300 nm-800 nm2O3Transferring to an upper surface of the bonding interlayer;
etching process is utilized to etch beta-Ga2O3The layer is thinned to less than 100nm to form a heterojunction substrate.
5. The method for preparing a HEMT device based on double heterojunction and composite passivation layer according to claim 1, wherein the process for forming the buffer layer comprises:
growing 100 nm-500 nm beta-Ga by molecular beam epitaxial growth process in oxygen plasma atmosphere2O3As a buffer layer.
6. The method for preparing a HEMT device based on double heterojunction and composite passivation layer as claimed in claim 1, wherein the ion implantation process is performed on the upper surface of the first substrate, the implanted ion type comprises helium, iron or magnesium, and the implantation angle is 7 °.
7. The method for preparing HEMT device based on double heterojunction and composite passivation layer according to claim 1,
the materials of the secondary barrier layer and the primary barrier layer comprise beta- (Al)xGa1-x)2O3The value range of x is 0.1-0.5, and the growth temperature range is 700-750 ℃;
the materials of the first and second heterojunction layers include: beta-Ga2O3And beta- (Al)xGa1-x)2O3The growth temperature range is 700-750 ℃;
the doping materials of the first doping layer and the second doping layer comprise silicon doping, and the growth temperature range is 870-900 ℃.
8. The method for preparing a HEMT device based on double heterojunction and composite passivation layer according to claim 1, wherein the process for forming the source ohmic contact region or the drain ohmic contact region comprises:
performing ion implantation on two sides of the upper surface of the main barrier layer, wherein the implanted ions comprise silicon, tin or germanium, the range of the implantation angle is 0-90 degrees, the implantation energy is 20-300 keV, and the implantation dosage is 1 multiplied by 1014cm-3～1×1015cm-3；
Annealing for 30-60 min under the atmosphere of neon or argon, wherein the annealing temperature range is 900-1050 ℃, and the doping concentration of the formed source electrode ohmic contact region or the drain electrode ohmic contact region is more than 1 multiplied by 1019cm-3。
9. The method for preparing an HEMT device based on double heterojunction and composite passivation layer according to claim 1, wherein the thickness of the dielectric layer is 80 nm-120 nm, and the material of the dielectric layer comprises: BaTiO 23、SrTiO3、LaMnO3、KTaO3Or BiFeO3。
10. A HEMT device based on a double heterojunction and a composite passivation layer, comprising:
the heterojunction substrate, the buffer layer, the secondary barrier layer, the first doping layer, the first heterojunction layer, the quantum well layer, the second heterojunction layer, the second doping layer and the main barrier layer are sequentially formed from bottom to top; the heterojunction substrate and the buffer layer have the same length, and the sub-barrier layer, the first doping layer, the first heterojunction layer, the quantum well layer, the second heterojunction layer, and the second doping layerThe layers and the primary barrier layer are the same in length, and the length of the heterojunction substrate is greater than that of the secondary barrier layer; wherein the heterojunction substrate comprises a first substrate, a second substrate, a bonding intermediate layer and beta-Ga sequentially formed from bottom to top2O3A layer;
the source electrode ohmic contact region and the drain electrode ohmic contact region are positioned on two sides of the main barrier layer and extend to the buffer layer;
the source electrode is positioned on the upper surface of the source electrode ohmic contact region;
the drain electrode is positioned on the upper surface of the drain electrode ohmic contact region;
an oxide layer on the primary barrier layer;
the dielectric layer and the passivation layer are sequentially positioned on the oxide layer, and the dielectric layer covers at least one part of the upper surfaces of the source electrode and the drain electrode;
and the grid electrode is positioned in the dielectric layer and is close to the source electrode.
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