CN113823615A - Capacitive isolation chip - Google Patents
Capacitive isolation chip Download PDFInfo
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- CN113823615A CN113823615A CN202010543785.2A CN202010543785A CN113823615A CN 113823615 A CN113823615 A CN 113823615A CN 202010543785 A CN202010543785 A CN 202010543785A CN 113823615 A CN113823615 A CN 113823615A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
Abstract
The invention discloses a capacitive isolation chip and a manufacturing method thereof, and the capacitive isolation chip comprises a substrate, a lower polar plate and an upper polar plate which are positioned on the upper side of the substrate and are arranged oppositely, and at least two interlayer dielectric layers positioned between the upper polar plate and the lower polar plate; a metal wiring layer is also arranged between the adjacent two interlayer dielectric layers, and a plurality of first contact holes which are connected with the corresponding metal wiring layer at the lower side of the metal wiring layer and are filled with metal objects are formed in the upper interlayer dielectric layer in the adjacent two interlayer dielectric layers; the metal wiring layer comprises a metal main body film and a first metal barrier film arranged on the upper surface of the metal main body film, and the capacitive isolation chip further comprises a medium buffer layer arranged on the upper surface of the first metal barrier film; based on the arrangement structure of the capacitive isolation chip, when the first contact hole is formed by etching the corresponding interlayer dielectric layer on the upper side of the metal wiring layer by using plasma, the etching uniformity of the first contact hole can be ensured even if the first metal barrier film has relatively thin thickness.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a capacitive isolation chip.
Background
Referring to fig. 1, a conventional structure of a capacitive isolation chip in the prior art is schematically shown, the capacitive isolation chip includes a substrate 100 ', a lower plate 200 ' and an upper plate 300 ' disposed on an upper side of the substrate 100 ' and opposite to each other, and a first interlayer dielectric layer 41 ' and a second interlayer dielectric layer 42 ' disposed between the upper plate 300 ' and the lower plate 200 ', and a metal wiring layer 500 ' disposed between the first interlayer dielectric layer 41 ' and the second interlayer dielectric layer 42 '. A metal wiring layer 500 ' according to the related art generally has a three-layer sandwich structure as shown in fig. 2, and specifically includes a metal main body film 50 ', a first metal barrier film 51 ' and a second metal barrier film 52 ' respectively provided on upper and lower surfaces of the metal main body film 50 '.
In the specific implementation process, in order to connect the metal wiring layer 500 'to the circuit structure on the upper side thereof, the second interlayer dielectric layer 42' must be provided with a plurality of contact holes 40 'filled with metal objects 40 a'. When the contact holes 40 ' are formed by plasma etching, the etching progress of each contact hole 40 ' in the second interlayer dielectric layer 42 ' inevitably has a certain difference, and since the thickness of the second interlayer dielectric layer 42 ' is usually much larger than that of the metal wiring layer 500 ', a plurality of contact holes 40 ' usually accumulate a larger progress difference in the second interlayer dielectric layer 42 '. In order to make all the contact holes 40 ' have better uniformity in the whole process of plasma etching and avoid the problem that some contact holes 40 ' are not etched to the metal wiring layer 500 ' and other contact holes 40 ' are etched in the metal wiring layer 500 ' to a deeper depth or even completely cut through the metal wiring layer 500 ', the first metal barrier film 51 ' involved in the prior art must be provided with a phaseFor thicker thicknesses, the thickness D 'of the metal body film 50' is typically
The thickness d1 'of the first metal barrier film 51' is
Left and right. Through process control, the speed of etching the first metal barrier film 51 ' by plasma can be far lower than the speed of etching the second interlayer dielectric layer 42 ', so that the contact hole 40 ' etched to the first metal barrier film 51 ' first can be etched downwards at a slower first speed, and the contact hole 40 ' not etched to the first metal barrier film 51 ' can be etched downwards at a much faster second speed relative to the first speed until all the contact holes 40 ' are abutted to the first metal barrier film 51 ', and then the formation of the contact hole 40 ' is completed.
In addition, in order to make the metal wiring layer 500 ' have better stress performance, the second metal barrier film 52 ' and the first metal barrier film 51 ' generally have more uniform thickness, i.e., the thickness d2 ' of the second metal barrier film 52 ' also has a relatively large value. As shown in fig. 2 and fig. 3, the specific process of forming the metal wiring layer 500' includes: a metal film corresponding to the metal wiring layer 500 ' is deposited on the upper surface of the first interlayer dielectric layer 41 ', and then a region 50a ' to be etched except for the circuit of the metal wiring layer 500 ' is etched by plasma to form the metal wiring layer 500 '. In the etching process, the region 50a 'to be etched of the metal film needs to be over-etched to a certain extent, however, since the etching rate of the plasma on the second metal barrier film 52' is slow, the required over-etching time is also long for the second metal barrier film 52 'with a thicker thickness, in this way, in the etching process, the plasma can bring great damage to the region of the upper surface of the first interlayer dielectric layer 41' corresponding to the region 50a 'to be etched, and the damage can greatly affect the isolation performance of the isolation gate between the upper and lower electrode plates of the capacitive isolation chip, and when the area of the region 50 a' to be etched is large, the effect is more obvious.
In view of the above, there is a need to provide an improved solution to the above problems.
Disclosure of Invention
The invention aims to solve at least one technical problem in the prior art, and in order to achieve the purpose of the invention, the invention provides a capacitive isolation chip which is specifically designed as follows.
A capacitive isolation chip comprises a substrate, a lower polar plate and an upper polar plate which are positioned on the upper side of the substrate and are arranged oppositely, and at least two interlayer dielectric layers positioned between the upper polar plate and the lower polar plate; a metal wiring layer is also arranged between two adjacent interlayer dielectric layers, and a plurality of first contact holes which are connected with the corresponding metal wiring layer on the lower side of the metal wiring layer and are filled with metal objects are formed in the upper interlayer dielectric layer of the two adjacent interlayer dielectric layers; the metal wiring layer comprises a metal main body film and a first metal barrier film arranged on the upper surface of the metal main body film, and the capacitive isolation chip further comprises a medium buffer layer arranged on the upper surface of the first metal barrier film.
Further, the metal wiring layer further comprises a second metal barrier film arranged on the lower surface of the metal main body film, and the second metal barrier film is consistent with the first metal barrier film in thickness.
Further, the thickness of the metal main body film is
The thickness of the first metal barrier film and the second metal barrier film is
Further, the interlayer dielectric layer is a silicon oxide film, and the dielectric buffer layer is a silicon nitride film, a silicon oxynitride film or a composite film formed by laminating the silicon nitride film and the silicon oxynitride film.
Further, the thickness of the medium buffer layer is 0.2-1.2 μm.
Furthermore, the capacitive isolation chip further comprises an interface dielectric layer arranged on the lower surface of the upper polar plate and/or the upper surface of the lower polar plate.
Further, the interface dielectric layer comprises a silicon nitride film and a silicon oxynitride film which are stacked.
Furthermore, the thicknesses of the silicon nitride film and the silicon oxynitride film which form the interface dielectric layer are both 0.5-1.5 μm.
Furthermore, the capacitive isolation chip also comprises a metal wiring area arranged on the same layer as the lower polar plate and a terminal arranged on the same layer as the upper polar plate, and a plurality of second contact holes which are connected with the metal wiring area and filled with metal objects are formed in the interlayer dielectric layer adjacent to the metal wiring area.
Furthermore, the capacitive isolation chip further comprises a passivation layer arranged on the upper side of the upper electrode plate.
The invention also provides a manufacturing method of the capacitive isolation chip, which comprises the following steps:
providing a substrate; sequentially forming a lower polar plate, at least two interlayer dielectric layers and an upper polar plate on the substrate;
before an upper interlayer dielectric layer of two adjacent interlayer dielectric layers is formed, a metal wiring layer and a dielectric buffer layer are sequentially formed on the corresponding lower interlayer dielectric layer, wherein the metal wiring layer comprises a metal main body film and a first metal barrier film arranged on the upper surface of the metal main body film; after the upper interlayer dielectric layer of two adjacent interlayer dielectric layers is formed, a plurality of first contact holes connected with the corresponding metal wiring layers on the lower side of the upper interlayer dielectric layer are formed in the upper interlayer dielectric layer, and metal materials are filled in the first contact holes.
The invention has the beneficial effects that: in the structure of the capacitive isolation chip provided by the invention, the dielectric buffer layer is arranged on the upper surface of the first metal barrier film of the metal wiring layer, when the first contact hole is formed by etching the corresponding interlayer dielectric layer on the upper side of the metal wiring layer by adopting plasma, the etching rate of the plasma to the dielectric buffer layer can be smaller than that to the interlayer dielectric layer by controlling because the etching rates of the plasma to different materials are different, so that the etching uniformity of the first contact hole can be ensured when the first metal barrier film has relatively thinner thickness, and the first metal barrier film is formed to have a larger process window.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a schematic diagram of a prior art capacitive isolator chip;
FIG. 2 is an enlarged view of portion A of FIG. 1 with metal in the contact hole removed;
FIG. 3 is a schematic diagram illustrating the formation of a metal wiring layer in FIG. 1;
FIG. 4 is a schematic diagram of a first embodiment of a capacitive isolation chip according to the present invention;
FIG. 5 is an enlarged view of portion B of FIG. 4 with metal in the first contact hole removed;
FIG. 6 is a schematic diagram illustrating the formation of the metal wiring layer of FIG. 4;
FIG. 7 is a flow chart illustrating a process for fabricating the capacitive isolation chip of FIG. 4;
FIG. 8 is a schematic diagram of a second embodiment of a capacitive isolation chip according to the present invention;
FIG. 9 is a schematic diagram of a third exemplary capacitive isolating chip according to the present invention;
fig. 10 is a schematic diagram of a fourth embodiment of the capacitive isolation chip according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 4, the capacitive isolation chip according to the present invention includes a substrate 100, a lower plate 200 and an upper plate 300 disposed on an upper side of the substrate 100 and opposite to each other, and at least two interlayer dielectric layers 400 disposed between the upper plate 300 and the lower plate 200. In this embodiment, two interlayer dielectric layers 400 are disposed between the upper plate 300 and the lower plate 200, that is, the two interlayer dielectric layers include a first interlayer dielectric layer 41 and a second interlayer dielectric layer 42 from bottom to top.
It is understood that in other embodiments of the present invention, three interlayer dielectric layers 400 or even more interlayer dielectric layers 400 may be disposed between the upper plate 300 and the lower plate 200, which may be adjusted according to the process requirements. Referring to fig. 8, three interlayer dielectric layers 400 are disposed between the upper plate 300 and the lower plate 200 in this embodiment, that is, a first interlayer dielectric layer 41, a second interlayer dielectric layer 42, and a third interlayer dielectric layer 43 are sequentially included from bottom to top.
In the invention, a metal wiring layer 500 is further arranged between two adjacent interlayer dielectric layers 400, and a plurality of first contact holes 401 which are connected with the corresponding metal wiring layer 500 at the lower side and are filled with metal objects are formed in the upper interlayer dielectric layer 500 in the two adjacent interlayer dielectric layers 500.
In the embodiment shown in fig. 4, the first interlayer dielectric layer 41 is adjacent to the second interlayer dielectric layer 42, a plurality of first contact holes 401 connected to the metal wiring layer 500 on the lower side of the first contact holes 401 are formed in the second interlayer dielectric layer 42 on the upper side, the first metal objects 401a are filled in the first contact holes 401, and the metal wiring layer 500 is electrically connected to the first metal objects 401a of the first contact holes 401. In the embodiment shown in fig. 8, the first interlayer dielectric layer 41 is adjacent to the second interlayer dielectric layer 42, the second interlayer dielectric layer 42 is adjacent to the third interlayer dielectric layer 43, a plurality of first contact holes 401 filled with the first metal objects 401a are formed in the second interlayer dielectric layer 42 and the third interlayer dielectric layer 43, and the first metal objects 401a in the first contact holes 401 are electrically connected to the metal wiring layer 500 on the lower side thereof.
As shown in fig. 5, the metal wiring layer 500 according to the present invention includes a metal body film 50 and a first metal barrier film 51 provided on an upper surface of the metal body film 500, and the capacitive isolation chip further includes a dielectric buffer layer 600 provided on an upper surface of the first metal barrier film 51.
In the structure of the capacitive isolation chip provided by the invention, the dielectric buffer layer 600 is arranged on the upper surface of the first metal barrier film 51 of the metal wiring layer 500, when the first contact hole 401 is formed by etching the corresponding interlayer dielectric layer 400 on the upper side of the metal wiring layer 500 by using plasma, because the etching rates of the plasma to different materials are different, the etching rate of the plasma to the dielectric buffer layer 600 can be controlled to be smaller than the etching rate to the interlayer dielectric layer 400, so that the etching uniformity of the first contact hole 104 can be ensured when the first metal barrier film 51 has a relatively thin thickness, and the first metal barrier film 51 can be formed to have a larger process window.
In the specific implementation process of the invention, through process selection, the rate of plasma etching the interlayer dielectric layer 400 is greater than the rate of plasma etching the dielectric buffer layer 600, and the rate of plasma etching the dielectric buffer layer 600 is greater than the rate of plasma etching the first metal barrier film 51.
As a preferred embodiment of the present invention, referring to fig. 5, the metal wiring layer 500 according to the present embodiment further includes a second metal barrier film 52 provided on the lower surface of the metal main body film 50, and the second metal barrier film 52 has a thickness equal to that of the first metal barrier film 51. Since the second barrier metal film 52 has the same thickness as the first barrier metal film 51, the entire metal wiring layer 500 has a better stress performance, and the phenomenon of separation between adjacent layers due to the stress problem can be avoided. It is to be understood that, in the present invention, the thickness of the second metal barrier film 52 is the same as that of the first metal barrier film 51, which means that the thicknesses of the two films are completely the same, or they may not be completely the same but in the same order of magnitude.
In addition, as shown in fig. 6, the specific forming process of the metal wiring layer 500 and the dielectric buffer layer 600 on the upper surface thereof includes: a metal film corresponding to the metal wiring layer 500 and a dielectric film corresponding to the dielectric buffer layer 600 are sequentially deposited on the upper surface of an interlayer dielectric layer 400, and then the first region to be etched 50a and the second region to be etched 60a except for the circuit of the metal wiring layer 500 are etched by plasma, so that the corresponding metal wiring layer 500 and the dielectric buffer layer 600 are formed. In the process, the region 50a to be etched of the metal film needs to be over-etched to a certain extent, although the etching rate of the plasma on the second metal barrier film 52 is slow, since the second metal barrier film 52 can be set to be very thin, the required over-etching time is correspondingly short, so that in the etching process, the damage of the plasma on the region of the interlayer dielectric layer 400 corresponding to the region 50a to be etched can be effectively reduced, and the isolation performance of the isolation gate between the upper plate 300 and the lower plate 200 of the capacitive isolation chip is further prevented from being affected. In the present invention, the isolation gate refers to the multi-layered interlayer dielectric layer 400 between the upper plate 300 and the lower plate 200.
In the practice of the invention, the thickness of the metal host film 50 is
The first metal barrier film 51 and the second metal barrier film 52 have a thickness of
The metal body film 50 of the present invention may be made of aluminum-copper alloy or copper. When the metal main body film 50 is made of an aluminum-copper alloy, the first metal barrier film 51 and the second metal barrier film 52 are both made of a composite layer of titanium and titanium nitride; when the metal body film 50 is made of a copper alloy, the first metal barrier film 51 and the second metal barrier film 52 are each made of a composite layer of tantalum and tantalum nitride. In the present invention, the first metal barrier film 51 and the second metal barrier film 52 mainly function to block the diffusion of the metal host film 50 into the interlayer dielectric layer, and also to some extent, to improve the bonding force with the adjacent layer. In particular, when the metal host film 50 is formed, it is necessary to perform processes such as coating, exposure, and development, and the first metal barrier film 51 can also be used as an anti-reflection layer during exposure.
In addition, in the specific implementation process, when the metal body film 50 is made of the aluminum-copper alloy, the first metal object 401a filled in the first contact hole 401 is made of metal tungsten; when the metal body film 50 is made of copper, the first metal object 401a filled in the first contact hole 401 is made of copper.
In some embodiments of the present invention, the interlayer dielectric layer 400 is a silicon oxide film, and the dielectric buffer layer 600 is a silicon nitride film, a silicon oxynitride film, or a composite film formed by laminating the two.
In the present invention, the total thickness of the isolation gate is generally in the range of 12-16 μm, and the thickness of the single interlayer dielectric layer 400 is in the range of 0.5-7 μm.
Preferably, the dielectric buffer layer 600 according to the present invention has a thickness of 0.2 to 1.2 μm. When the interlayer dielectric layer 400 is a composite film, the thickness ranges of the silicon nitride film and the silicon oxynitride film which form the composite film are both 0.1-0.6 μm.
As a preferred embodiment of the present invention, referring to fig. 9, the capacitive isolation chip according to this embodiment further includes an interface dielectric layer 700 disposed on the lower surface of the upper plate 300. In this embodiment, the isolation gate of the capacitive isolation chip further includes the interface dielectric layer 700, the interface dielectric layer 700 is made of a material different from that of the interlayer dielectric layer 400, and in the specific implementation process, the isolation performance of the isolation gate can be effectively improved by using a film stack structure made of a different material.
The interfacial dielectric layer 700 in the embodiment shown in fig. 9 includes a silicon nitride film 71 and a silicon oxynitride film 72 stacked from bottom to top; in other embodiments, the order of disposing the silicon nitride film 71 and the silicon oxynitride film 72 may be the reverse of the order illustrated in fig. 9, that is, the silicon nitride film 71 is disposed on the upper side of the silicon oxynitride film 72.
In other embodiments of the present invention, the interface dielectric layer 700 may be only disposed on the upper surface of the lower plate 200, and the interface dielectric layer 700 may be disposed on the lower surface of the upper plate 300 and the upper surface of the lower plate 200. The interfacial dielectric layer 700 is also not limited to a bilayer film morphology.
Referring to fig. 10, in this embodiment, the interface dielectric layer 700 is disposed on both the lower surface of the upper plate 300 and the upper surface of the lower plate 200. The interfacial dielectric layer 700 on the lower surface of the upper plate 300 has the same structure as the interfacial dielectric layer 700 in the embodiment shown in fig. 9, and the interfacial dielectric layer 700 on the upper surface of the lower plate is a single-layer film.
The thickness of the interface dielectric layer 700 is usually 1-3 μm, and when the interface dielectric layer 700 is formed by a double-layer film of the silicon nitride film 71 and the silicon oxynitride film 72, the thickness of the two layers is 0.5-1.5 μm.
Referring to fig. 4, 8, 9 and 10, the capacitive isolation chip according to the present invention further includes a metal wiring region 201 disposed on the same layer as the lower plate 200 and a first terminal 301 disposed on the same layer as the upper plate 300, wherein a plurality of second contact holes 402 connected to the metal wiring region 201 are formed in the interlayer dielectric layer 400 (i.e., the first interlayer dielectric layer 41) adjacent to the metal wiring region 201, and the second contact holes 402 are filled with a second metal object 402 a. Generally, the second metal object 402a and the first metal object 401a are made of the same material.
The capacitive isolation chip further includes a passivation layer 800 disposed on the upper side of the upper plate 300. In specific implementation, the passivation layer 800 includes a first passivation film 81 directly attached to the upper surface of the upper plate 300 and a second passivation film 82 attached to the upper surface of the first passivation film 81.
Preferably, the first passivation film 81 is a silicon oxide film, and the second passivation film 82 is a silicon nitride film. Typically, the thickness of the first passivation film 81 is 1 to 4 μm, and the thickness of the second passivation film 82 is 0.5 to 1.5 μm.
In the present invention, the passivation layer 800 is respectively provided with openings for partially exposing the first terminal and the upper plate 300, the partially exposed portion of the upper plate 300 forms the second terminal 302, and the first terminal 301 and the second terminal 302 are used as connectors for electrically connecting with the outside.
It is understood that in the present invention, the substrate 100 generally includes a wafer substrate and a circuit formed on the wafer substrate, and the specific structure can refer to the prior art. Referring to fig. 4, the circuits on the wafer are electrically connected to the metal wiring region 201, the second metal object 402a in the second contact hole 402, the wiring layer 500, the second metal object 401a in the first contact hole 401, and the first terminal 301 in sequence. In addition, although not shown, it is understood that other metal layers and dielectric layers may be disposed between the lower plate 200 and the substrate 100 in other embodiments of the present invention, and in particular, it is also possible to refer to the prior art, and no further development is made.
In the present invention, the upper plate 200 and the lower plate 300 may be configured to have a structure similar to that of the metal wiring layer 500, that is, include a metal main body film and metal barrier films attached to both surfaces thereof, and the material may refer to the material of the metal wiring layer 500. In the specific implementation process, the thickness of the metal main body film of the upper polar plate 300 is
The thickness of the metal main body film of the lower electrode plate 200 is
The thickness of the metal barrier film is set to be
In order to better understand the invention, the invention also provides a manufacturing method of the capacitive isolation chip, which comprises the following steps:
providing a substrate 100; sequentially forming a lower polar plate 200, at least two interlayer dielectric layers 400 and an upper polar plate 300 on a substrate 100;
before the formation of the upper interlayer dielectric layer in two adjacent interlayer dielectric layers 400, a metal wiring layer 500 and a dielectric buffer layer 600 are sequentially formed on the corresponding lower interlayer dielectric layer.
As shown in fig. 4 and 7, in this embodiment, before the second interlayer dielectric layer 42 is formed, a metal wiring layer 500 and a dielectric buffer layer 600 need to be sequentially formed on the first interlayer dielectric layer 41. For the embodiment shown in fig. 8, before the second interlayer dielectric layer 42 is formed, a metal wiring layer 500 and a dielectric buffer layer 600 are required to be sequentially formed on the first interlayer dielectric layer 41; before the third interlayer dielectric layer 43 is formed, it is also necessary to sequentially form the metal wiring layer 500 and the dielectric buffer layer 600 on the second interlayer dielectric layer 42.
After the upper interlayer dielectric layer in the two adjacent interlayer dielectric layers 400 is formed, a first contact hole 401 connected to the corresponding metal wiring layer 500 on the lower side thereof is formed in the upper interlayer dielectric layer, and the first contact hole 401 is filled with a first metal object 401 a.
As shown in fig. 4 and 7, in this embodiment, after the second interlayer dielectric layer 42 is formed, it is necessary to form a first contact hole 401 connected to a corresponding metal wiring layer 500 on the lower side of the second interlayer dielectric layer 42. For the embodiment shown in fig. 8, after the second interlayer dielectric layer 42 is formed, it is necessary to form a first contact hole 401 connected to a corresponding metal wiring layer 500 on the lower side thereof in the second interlayer dielectric layer 42; after the third interlayer dielectric layer 43 is formed, it is necessary to form first contact holes 401 connected to the respective metal wiring layers 500 on the lower side thereof in the third interlayer dielectric layer 43.
A specific method for fabricating the capacitive isolation chip shown in fig. 4 is described in more detail below with reference to fig. 7:
a lower polar plate 200 and a metal wiring area 201 which is arranged on the same layer with the lower polar plate 200 are manufactured on the substrate 100 by adopting a vapor deposition process and a plasma etching process;
manufacturing a first interlayer dielectric layer 41 on the upper side of the lower electrode plate 200 and the metal wiring area 201 by adopting a vapor deposition process, and forming a second contact hole 402 on the first interlayer dielectric layer 41 by adopting a plasma etching process;
depositing a second metal object 402a in the second contact hole 402 of the first interlayer dielectric layer 41 to electrically connect with the metal wiring region 201;
a metal wiring layer 500 and a dielectric buffer layer 600 are manufactured on the first interlayer dielectric layer 41 by adopting a vapor deposition process and a plasma etching process, wherein the metal wiring layer 500 is electrically connected with the second metal object 402a on the lower side of the metal wiring layer;
manufacturing a second interlayer dielectric layer 42 on the upper side of the dielectric buffer layer 600 by adopting a vapor deposition process, and forming a first contact hole 401 on the second interlayer dielectric layer 42 by adopting a plasma etching process, wherein the first contact hole 401 penetrates through the dielectric buffer layer 600;
depositing a first metal object 401a in the first contact hole 401 of the second interlayer dielectric layer 42 to form an electrical connection with the metal wiring layer 500;
manufacturing an upper polar plate 300 and a first terminal 301 which is arranged on the same layer as the upper polar plate 300 on the second interlayer dielectric layer 42 by adopting a vapor deposition process and a plasma etching process, wherein the first terminal 301 is electrically connected with a first metal object 401a on the lower side of the first terminal;
the first passivation layer 81 and the second passivation layer 82 are formed on the upper plate 300 by a vapor deposition process, and an opening is formed by a plasma etching process to expose a portion of the upper plate 300 and the first terminal 301, and the portion of the upper plate 300 exposed through the opening forms the second terminal 302.
In the present invention, when the fabricated object is a conductive metal layer, such as the metal wiring layer 500, the lower plate 200, the upper plate 300, the first metal object 401a, the second metal object 402a, etc., the involved vapor deposition process is PVD; when the manufactured object is a non-conductive layer, such as the first interlayer dielectric layer 41, the second interlayer dielectric layer 42, the dielectric buffer layer 600, the first passivation layer 81, the second passivation layer 82, and the like, the involved vapor deposition process is PVD.
It should be understood that although the present description refers to embodiments, not every embodiment contains only a single technical solution, and such description is for clarity only, and those skilled in the art should make the description as a whole, and the technical solutions in the embodiments can also be combined appropriately to form other embodiments understood by those skilled in the art.
The above-listed detailed description is only a specific description of a possible embodiment of the present invention, and they are not intended to limit the scope of the present invention, and equivalent embodiments or modifications made without departing from the technical spirit of the present invention should be included in the scope of the present invention.
Claims (11)
1. A capacitive isolation chip is characterized by comprising a substrate, a lower polar plate and an upper polar plate which are positioned on the upper side of the substrate and are arranged oppositely, and at least two interlayer dielectric layers positioned between the upper polar plate and the lower polar plate; a metal wiring layer is also arranged between two adjacent interlayer dielectric layers, and a plurality of first contact holes which are connected with the corresponding metal wiring layer on the lower side of the metal wiring layer and are filled with metal objects are formed in the upper interlayer dielectric layer of the two adjacent interlayer dielectric layers; the metal wiring layer comprises a metal main body film and a first metal barrier film arranged on the upper surface of the metal main body film, and the capacitive isolation chip further comprises a medium buffer layer arranged on the upper surface of the first metal barrier film.
2. The capacitive isolation chip of claim 1, wherein the metal wiring layer further comprises a second metal barrier film disposed on the lower surface of the metal body film, the second metal barrier film having a thickness corresponding to the thickness of the first metal barrier film.
3. The capacitive isolation chip of claim 2, wherein the metal body film has a thickness of
The thickness of the first metal barrier film and the second metal barrier film is
4. The capacitive isolation chip according to any one of claims 1 to 3, wherein the interlayer dielectric layer is a silicon oxide film, and the dielectric buffer layer is a silicon nitride film, a silicon oxynitride film or a composite film formed by laminating the silicon nitride film and the silicon oxynitride film.
5. The capacitive isolator chip of claim 4, wherein the dielectric buffer layer has a thickness of 0.2-1.2 μm.
6. The capacitive isolation chip according to any one of claims 1 to 3, further comprising an interface dielectric layer disposed on the lower surface of the upper plate and/or the upper surface of the lower plate.
7. The capacitive isolation chip of claim 6, wherein the interface dielectric layer comprises a silicon nitride film and a silicon oxynitride film stacked together.
8. The capacitive isolation chip of claim 7, wherein the thickness of the silicon nitride film and the silicon oxynitride film forming the interface dielectric layer are both 0.5-1.5 μm.
9. The capacitive isolation chip according to any one of claims 1 to 3, further comprising a metal wiring region disposed on the same layer as the lower electrode plate and a terminal disposed on the same layer as the upper electrode plate, wherein a plurality of second contact holes connected to the metal wiring region and filled with metal are formed in the interlayer dielectric layer adjacent to the metal wiring region.
10. The capacitive isolation chip of any one of claims 1 to 3, further comprising a passivation layer disposed on the upper side of the upper plate.
11. A manufacturing method of a capacitive isolation chip comprises the following steps: it is characterized in that the preparation method is characterized in that,
providing a substrate;
sequentially forming a lower polar plate, at least two interlayer dielectric layers and an upper polar plate on the substrate; wherein the content of the first and second substances,
before an upper interlayer dielectric layer of two adjacent interlayer dielectric layers is formed, a metal wiring layer and a dielectric buffer layer are sequentially formed on the corresponding lower interlayer dielectric layer, wherein the metal wiring layer comprises a metal main body film and a first metal barrier film arranged on the upper surface of the metal main body film;
after the upper interlayer dielectric layer of two adjacent interlayer dielectric layers is formed, a plurality of first contact holes connected with the corresponding metal wiring layers on the lower side of the upper interlayer dielectric layer are formed in the upper interlayer dielectric layer, and metal materials are filled in the first contact holes.
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| JP2001068640A (en) * | 1999-08-25 | 2001-03-16 | Sanyo Electric Co Ltd | Semiconductor device and its manufacture |
| CN102790032A (en) * | 2011-05-16 | 2012-11-21 | 中芯国际集成电路制造(上海)有限公司 | Interconnection structure and forming method thereof |
| CN103346067A (en) * | 2013-06-26 | 2013-10-09 | 上海宏力半导体制造有限公司 | Method for forming semiconductor device and method for forming MIM capacitor |
| CN103811310A (en) * | 2014-03-07 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Resistor structure and forming method thereof |
| CN111199953A (en) * | 2018-11-16 | 2020-05-26 | 无锡华润上华科技有限公司 | MIM capacitor and manufacturing method thereof |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001068640A (en) * | 1999-08-25 | 2001-03-16 | Sanyo Electric Co Ltd | Semiconductor device and its manufacture |
| CN102790032A (en) * | 2011-05-16 | 2012-11-21 | 中芯国际集成电路制造(上海)有限公司 | Interconnection structure and forming method thereof |
| CN103346067A (en) * | 2013-06-26 | 2013-10-09 | 上海宏力半导体制造有限公司 | Method for forming semiconductor device and method for forming MIM capacitor |
| CN103811310A (en) * | 2014-03-07 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Resistor structure and forming method thereof |
| CN111199953A (en) * | 2018-11-16 | 2020-05-26 | 无锡华润上华科技有限公司 | MIM capacitor and manufacturing method thereof |
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