CN115692372A - Anti-fuse unit structure, preparation method and preparation method of electrode structure - Google Patents
Anti-fuse unit structure, preparation method and preparation method of electrode structure Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 84
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 58
- 230000004888 barrier function Effects 0.000 claims abstract description 48
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 43
- 239000010937 tungsten Substances 0.000 claims abstract description 43
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 29
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 29
- 230000007547 defect Effects 0.000 claims abstract description 9
- 230000007797 corrosion Effects 0.000 claims abstract description 8
- 238000005260 corrosion Methods 0.000 claims abstract description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 28
- 238000000151 deposition Methods 0.000 claims description 28
- 238000005530 etching Methods 0.000 claims description 23
- 229910052681 coesite Inorganic materials 0.000 claims description 22
- 229910052906 cristobalite Inorganic materials 0.000 claims description 22
- 229910052682 stishovite Inorganic materials 0.000 claims description 22
- 229910052905 tridymite Inorganic materials 0.000 claims description 22
- 238000005240 physical vapour deposition Methods 0.000 claims description 17
- 238000001259 photo etching Methods 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 239000002131 composite material Substances 0.000 claims description 9
- 238000004140 cleaning Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 239000000463 material Substances 0.000 description 8
- 230000008021 deposition Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000003860 storage Methods 0.000 description 3
- 238000000605 extraction Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Abstract
The invention relates to an anti-fuse structure, in particular to an anti-fuse unit structure, a preparation method and a preparation method of an electrode structure. An anti-fuse unit structure comprises an upper barrier layer and an anti-fuse film layer, wherein the upper barrier layer is arranged on the anti-fuse film layer, and the anti-fuse film layer is arranged on a silicon dioxide dielectric layer and is positioned above a tungsten plug. The anti-fuse unit structure provided by the invention optimizes the bottom structure of the anti-fuse unit, removes the lower polar plate barrier layer of the anti-fuse unit structure, obviously enlarges the tolerance of the anti-fuse laminated corrosion process, enhances the defect tolerance in the process and improves the yield of the anti-fuse unit structure.
Description
Technical Field
The invention relates to an anti-fuse structure, in particular to an anti-fuse unit structure, a preparation method and a preparation method of an electrode structure.
Background
The MTM antifuse structure is used for data information storage or logic switch realization, and the manufacturing process is compatible with a standard CMOS process. The typical structure of the MTM antifuse unit is a sandwich structure, is generally positioned between two layers of metal wiring and consists of an antifuse dielectric layer, upper and lower electrode barrier layers and upper and lower electrode metals, and the antifuse unit is disconnected before and after programming to realize the logic function or the storage function of a circuit. The anti-fuse unit has the characteristics of high reliability, radiation resistance, strong confidentiality, good flexibility and the like, and the anti-fuse unit is a storage unit or a switch unit widely used in the aerospace field due to the excellent characteristics.
Conventional anti-fuse cells include upper and lower barrier layers that are highly desirable for integrated circuit process control because the upper and lower barrier layers are simultaneously exposed to the process chamber environment during the etch of the anti-fuse film stack, as shown in fig. 10. Since the upper barrier layer 6 and the lower barrier layer 62 are both conductive layers and the antifuse film 7 is very thin, if there is a very small defect 63 in the process chamber, there is a risk that the upper and lower barrier layers of the antifuse unit are short-circuited, and the antifuse unit may fail or have a reliability risk.
Disclosure of Invention
In order to solve the problems of the traditional structure, the invention provides a structure which optimizes the bottom appearance of the anti-fuse unit and simultaneously removes the lower polar plate barrier layer, so that even if larger defect particles exist in the anti-fuse laminated corrosion process, the anti-fuse unit cannot be short-circuited and failed due to the absence of the lower polar plate barrier layer, and the process capacity of the structure preparation is greatly increased. The specific technical scheme is as follows:
the anti-fuse unit structure comprises an upper barrier layer and an anti-fuse film layer, wherein the upper barrier layer is arranged on the anti-fuse film layer, and the anti-fuse film layer is arranged on a silicon dioxide dielectric layer and is positioned above a tungsten plug.
Preferably, the antifuse film layer is one of a SiO2 dielectric layer, a SiN dielectric layer, an amorphous dielectric layer or a composite layer, wherein the composite layer is formed by overlapping one or more of the SiO2 dielectric layer, the SiN dielectric layer or the amorphous dielectric layer, the thicknesses of the SiO2 dielectric layer and the SiN dielectric layer are from 10A to 500A, and the thickness of the amorphous dielectric layer is from 100A to 1500A.
Preferably, the thickness uniformity of each film layer of the composite layer is less than 2%.
Further, the thickness of the antifuse mold layer is 100A to 2000A.
Preferably, the upper barrier layer is generally a TiN layer or a TiW layer, and the film thickness of the upper barrier layer is 500A to 3000A.
Furthermore, the angle of the cross section of the lamination formed by the anti-fuse film layer and the upper barrier layer is more than 85 DEG
Preferably, the anti-fuse film layer is located on the top of the via tungsten plug, and completely covers the via.
A method for preparing an anti-fuse structure comprises the following steps:
performing anti-fuse film deposition on the silicon dioxide dielectric layer by adopting a CVD or PVD method;
and depositing an upper barrier layer on the anti-fuse film layer by adopting a PVD (physical vapor deposition) or CVD (chemical vapor deposition) method.
The preparation method of the electrode structure comprises the following steps:
s1, completing the process manufacturing of a front-end CMOS device and a lower plate wiring layer of an anti-fuse structure based on a standard CMOS process;
s2, depositing a SiO2 medium by adopting a CVD (chemical vapor deposition) process; then forming a through hole by photoetching and etching processes; depositing tungsten by adopting a CVD (chemical vapor deposition) process, and removing tungsten outside the through hole by adopting a CMP (chemical mechanical polishing) process to only leave tungsten in the through hole;
s3, depositing an anti-fuse film layer by adopting a CVD or PVD method, and then depositing an upper barrier layer;
s4, etching the upper barrier layer and the anti-fuse film layer by adopting a photoetching and etching process, forming an anti-fuse unit structure on the through hole to be processed, then removing glue and cleaning, and removing defects in the process, wherein the section angle of the anti-fuse unit laminated film structure is larger than 85 degrees, the anti-fuse unit structure is arranged right above the through hole and completely covers the area of the through hole, and the size of the anti-fuse unit is larger than that of the through hole;
s5, sequentially depositing SiO2 media by adopting a CVD method;
s6, etching the anti-fuse hole by adopting a photoetching and anisotropic etching method, and then removing the photoresist and cleaning;
and S7, depositing metal through a PVD (physical vapor deposition) process, leading out an upper polar plate of the anti-fuse unit structure, and forming an upper polar plate wiring layer by adopting a photoetching and corrosion process.
Preferably, no hollow is filled with tungsten in the through hole in the S2, and a smooth, continuous and round structure is formed around the tungsten plug and the through hole after the tungsten CMP process.
Compared with the prior art, the invention has the following beneficial effects:
the anti-fuse unit structure provided by the invention optimizes the bottom structure of the anti-fuse unit, removes the lower polar plate barrier layer of the anti-fuse unit structure, obviously enlarges the tolerance of the anti-fuse laminated corrosion process, enhances the defect tolerance in the process and improves the yield of the anti-fuse unit structure.
Drawings
FIG. 1 is a schematic diagram of device layer, antifuse underlayer metal;
FIG. 2 is a schematic illustration of the completion of the intermetallic SiO2 dielectric deposition, via lithography, etching, tungsten plug and tungsten CMP process;
FIG. 3 is a schematic illustration of an anti-fuse film layer after completion of a barrier layer deposition process on the anti-fuse;
FIG. 4 is a schematic illustration of a stack of barrier and antifuse films over an antifuse after a photolithography and etching process is completed, with a cross-sectional angle of greater than 85 degrees on both sides;
FIG. 5 is a schematic diagram of an antifuse unit after a process of depositing SiO2 dielectric by plate extraction;
FIG. 6 is a schematic illustration of the completed antifuse hole photolithography and etching;
FIG. 7 is a schematic diagram of the anti-fuse unit after the metal deposition and the photo etching of the upper plate are completed, and the extraction of the upper and lower plates of the anti-fuse unit is realized;
FIG. 8 is a schematic view of the allowed shape of the tungsten plug;
FIG. 9 is a schematic view of an impermissible shape of a tungsten plug;
fig. 10 is a schematic diagram of an antifuse in the prior art.
Detailed Description
The invention will now be further described with reference to the accompanying drawings.
Aiming at the problems of small process capacity width, low yield and the like caused by the structural characteristics of the anti-fuse wire on the traditional through hole, the invention removes the lower polar plate barrier layer of the anti-fuse wire unit structure based on the anti-fuse wire unit structure on the traditional through hole, and obtains a novel anti-fuse wire unit structure on the through hole with high process capacity width by optimizing the appearance of the through hole under the anti-fuse wire unit; the method reduces the control requirement on the manufacturing process, improves the process yield of the anti-fuse unit, and can meet the preparation requirement of a high-density anti-fuse unit structure.
In the invention, the bottom appearance of the anti-fuse unit structure is optimized, and the lower polar plate barrier layer in the structure is removed, so that even if larger defect particles exist in the anti-fuse laminated etching process, the short circuit failure of the anti-fuse unit can not be caused. In actual process, the failure cause accounts for more than 70% of total failure, so that the structure greatly increases the process width.
As shown in fig. 3 and 4, an anti-fuse cell structure includes an upper barrier layer 7 and an anti-fuse film layer 6, where the upper barrier layer 7 is disposed on the anti-fuse film layer 6, and the anti-fuse film layer 6 is disposed on the silicon dioxide dielectric layer 4 and above the tungsten plug 5.
The antifuse film layer 6 is one of a SiO2 dielectric layer, a SiN dielectric layer, an amorphous dielectric layer or a composite layer, wherein the composite layer is formed by overlapping one or more of the SiO2 dielectric layer, the SiN dielectric layer or the amorphous dielectric layer, the thicknesses of the SiO2 dielectric layer and the SiN dielectric layer are respectively 10A to 500A, and the thickness of the amorphous dielectric layer is respectively 100A to 1500A.
The thickness uniformity of each film layer of the composite layer is less than 2 percent.
The thickness of the antifuse film layer 6 is 100A to 2000A.
The upper barrier layer 7 is generally a TiN layer or a TiW layer, and the film thickness of the upper barrier layer 7 is 500A to 3000A.
The angle of the laminated section formed by the anti-fuse film layer 6 and the upper barrier layer 7 is larger than 85 degrees.
The anti-fuse unit structure is arranged right above the tungsten plug 5, and the area at the top of the tungsten plug 5 is completely covered. The size of the anti-fuse unit is slightly larger than that of the through hole, the sizes of the through holes covered on the periphery of the anti-fuse unit are equal, and the sizes of the through holes covered on the periphery of the anti-fuse unit are 0.1um to 0.5um.
A preparation method of an anti-fuse structure comprises the following steps: depositing an anti-fuse film layer 6 on the silicon dioxide dielectric layer 4 by adopting a CVD or PVD method; an upper barrier layer 7 is deposited over the antifuse film layer 6 by PVD or CVD.
Compared with the traditional anti-fuse unit structure on the through hole, the structure has higher capability of tolerating process defects and better process yield.
After a through hole process is completed based on a mature silicon-based CMOS process technology, optimizing a tungsten plug and a tungsten CMP (chemical mechanical polishing) process, so that after the tungsten plug process, the tungsten in the through hole is filled without a cavity phenomenon, and after the tungsten CMP process, a tungsten plug column 5 and the periphery of the through hole form a smooth, continuous and round shape; depositing an anti-fuse film layer 6 and an upper polar plate barrier layer to cover the surface of the whole wafer, and then photoetching and corroding to ensure that the upper polar plate barrier layer and the anti-fuse film structure are only reserved in part of specific through hole areas, and other areas are corroded and removed; depositing a dielectric layer to form an antifuse hole through photoetching and corrosion, wherein the antifuse hole is overlapped with a through hole at the bottom of the antifuse hole in the longitudinal direction; and then the connection of the upper electrode and the lower electrode of the anti-fuse unit is realized through upper layer metal deposition, photoetching and corrosion.
A method of making an electrode structure comprising the steps of:
the first step is to complete the front-end CMOS device process manufacturing and the lower plate wiring layer process of the anti-fuse structure based on the standard CMOS process, as shown in FIG. 1. The substrate layer 1 is a CMOS process substrate material layer, generally a Si substrate or an SOI substrate material; the isolation medium layer 2 is an isolation medium layer in a CMOS process, and is generally an insulation medium such as SiO2, siN and the like; the metal wiring layer 3 is a metal wire for interconnecting devices in a CMOS process, the metal wiring layer 3 has completed photoetching and corrosion processes of the metal wiring layer, and in the invention, the metal wiring is used as a lower plate leading-out metal layer of an anti-fuse unit structure. The layers and the structure are realized by a standard CMOS process of a base line;
secondly, as shown in fig. 2, depositing a SiO2 medium by a CVD chemical vapor deposition process to obtain a first SiO2 medium layer 4, wherein the thickness of the first SiO2 medium layer 4 is consistent with the standard CMOS process reference condition; then forming a through hole by photoetching and etching processes; and then depositing tungsten by adopting a CVD (chemical vapor deposition) process, and removing tungsten outside the through hole by adopting a CMP (chemical mechanical polishing) process to only leave tungsten in the through hole to obtain the tungsten plunger 5. Because the lower plate barrier layer 62 is removed, the tungsten plug CVD process and the tungsten CMP process based on the base line are required to carry out process optimization in the process, so that after the tungsten plug process, the tungsten in the through hole is filled without a cavity phenomenon, after the tungsten CMP process, the tungsten plug column 5 and the periphery of the through hole form smooth, continuous and round shapes, and after the tungsten CMP process, several acceptable typical shapes are shown in FIG. 8, and unallowable shapes are shown in FIG. 9;
thirdly, as shown in fig. 3, depositing an antifuse film layer 6 by using a CVD or PVD method, where the antifuse film material may generally adopt a SiO2 medium, a SiN medium, an amorphous medium, or a stacked structure composed of these film layers, and the total film thickness is determined according to the breakdown voltage of the antifuse unit, and is generally 100a to 2000a in thickness, and the uniformity of each film thickness is less than 2%; then, a PVD or CVD method is adopted, a barrier layer is deposited again to obtain an upper barrier layer 7, the barrier layer is used for preventing the upper layer material and the lower layer material from being diffused, meanwhile, good contact is formed between the upper layer material and the lower layer material, tiN, tiW and other materials are generally adopted, and the thickness of the barrier layer film is 500-3000A; because tungsten has stronger electromigration resistance, different from the traditional structure, the deposition of the lower electrode plate barrier layer 62 is not carried out in the step, and the CVD or PVD method is adopted to directly carry out the deposition of the anti-fuse film layer 6;
fourthly, as shown in fig. 4, etching the anti-fuse structure laminated film by using a photoetching and etching process, wherein the etched film layer comprises two layers of mediums, namely an upper barrier layer 7 and an anti-fuse film layer 6, forming an anti-fuse unit structure on a specific through hole, and then removing glue and cleaning, so as to remove defects in the process, wherein the cross section angle of the anti-fuse unit laminated film structure is required to be more than 85 degrees, the structure is a laminated film, a trapezoid structure is required to be formed after etching, the angle is more than 85 degrees, the side surfaces of the two layers of films after etching are smooth, and the fault phenomenon caused by the different etching rates of the two films can not occur; the anti-fuse unit structure is arranged right above the through hole and covers the area of the through hole completely, the size of the anti-fuse unit structure is larger than that of the through hole, the size of the through hole covered by the anti-fuse unit structure meets the minimum size processing capacity of a process line, and the anti-fuse unit structure generally covers 0.1-0.5 um, namely the anti-fuse unit structure can cover the tungsten plug 5;
and fifthly, as shown in fig. 5, depositing a second SiO2 dielectric layer 8 by a CVD method, wherein the thickness of the second SiO2 dielectric layer 8 is 500-1000A.
Sixthly, as shown in fig. 6, etching the antifuse hole by photolithography and anisotropic etching, wherein the antifuse hole 9 is used for leading out an upper plate 10 of the antifuse unit structure, and then removing the photoresist and cleaning;
and seventhly, as shown in fig. 7, depositing metal through a PVD process, leading out the upper plate 10 of the antifuse unit structure, and then forming an upper plate wiring layer by using a photolithography and etching process, where the upper plate wiring layer includes an upper plate 10 and a lower plate 11.
The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive step, which shall fall within the scope of the appended claims.
Claims (10)
1. An anti-fuse unit structure, includes upper barrier layer (7) and anti-fuse film layer (6), upper barrier layer (7) set up on anti-fuse film layer (6), characterized in that, anti-fuse film layer (6) set up on silicon dioxide dielectric layer (4), and are located the top of tungsten stopper post (5).
2. The antifuse unit structure of claim 1, wherein the antifuse film layer (6) is one of a SiO2 dielectric layer, a SiN dielectric layer, an amorphous dielectric layer or a composite layer, wherein the composite layer is formed by stacking one or more of the SiO2 dielectric layer, the SiN dielectric layer or the amorphous dielectric layer, the thicknesses of the SiO2 dielectric layer and the SiN dielectric layer are from 10A to 500A, and the thickness of the amorphous dielectric layer is from 100A to 1500A.
3. The antifuse cell structure of claim 2, wherein the composite layer has a uniformity of thickness of less than 2%.
4. An antifuse cell structure according to any one of claims 1 to 3, wherein the thickness of the antifuse film layer (6) is 100A to 2000A.
5. An anti-fuse cell structure according to any of claims 1 to 3, characterized in that said upper barrier layer (7) is a TiN layer or TiW layer, and the thickness of said upper barrier layer (7) is 500A to 3000A.
6. An anti-fuse cell structure according to any of claims 1 to 3, characterized in that the angle of the cross-section of the stack of the anti-fuse film (6) and the upper barrier layer (7) is greater than 85 °.
7. An antifuse cell structure according to any one of claims 1 to 3, wherein the antifuse film layer (6) is located on top of the via tungsten plug (5) and covers the via completely.
8. A preparation method of an anti-fuse structure is characterized by comprising the following steps:
depositing an anti-fuse film layer (6) on the silicon dioxide dielectric layer (4) by adopting a CVD or PVD method;
and depositing an upper barrier layer (7) on the anti-fuse film layer (6) by adopting a PVD or CVD method.
9. The preparation method of the electrode structure is characterized by comprising the following steps of:
s1, completing the process manufacturing of a front-end CMOS device and a lower plate wiring layer of an anti-fuse structure based on a standard CMOS process;
s2, depositing a SiO2 medium by adopting a CVD (chemical vapor deposition) process; then forming a through hole by photoetching and etching processes; depositing tungsten by adopting a CVD (chemical vapor deposition) process, and removing tungsten outside the through hole by adopting a CMP (chemical mechanical polishing) process to only leave tungsten in the through hole;
s3, depositing an anti-fuse film layer (6) by adopting a CVD or PVD method, and then depositing an upper barrier layer (7);
s4, etching the upper barrier layer (7) and the anti-fuse film layer (6) by adopting a photoetching and etching process, forming an anti-fuse unit structure on the through hole to be processed, then degumming and cleaning, and removing defects in the process, wherein the laminated section angle formed by the anti-fuse film layer (6) and the upper barrier layer (7) is more than 85 degrees, the anti-fuse unit structure is arranged right above the through hole and completely covers the through hole area, and the size of the anti-fuse unit is more than that of the through hole;
s5, sequentially depositing SiO2 media by adopting a CVD method;
s6, etching the anti-fuse hole by adopting a photoetching and anisotropic etching method, and then removing the photoresist and cleaning;
and S7, depositing metal through a PVD (physical vapor deposition) process, leading out an upper polar plate of the anti-fuse unit structure, and forming an upper polar plate wiring layer by adopting a photoetching and corrosion process.
10. The method for preparing the electrode structure according to claim 9, wherein the through hole in S2 is filled with tungsten without voids, and the tungsten plug (5) and the through hole are formed into a smooth, continuous and round structure after the tungsten CMP process.
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