JP2001068640A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device having such a structure that can suppress the increase, etc., of the manufacturing man-hour regarding the formation of electrodes while the performance of the device as a capacitor is secured. SOLUTION: In the DRAM and logic circuit forming region of a semiconductor device on which a DRAM and logic circuit are mixedly mounted, contact holes 8 for diffusion layers 6 and metallic wiring M1 are formed at prescribed positions by depositing interlayer insulating films 7 on the diffusion layers 6. Then metallic barrier films 9 are formed on the insulating films 7 and in the contact holes 8 and a filling material 10 is buried in the holes 8. In addition, the storage electrodes 9a of a capacitor are formed by exposing the metallic barrier films 9 by removing the filling material 10 only from the contact holes 8 formed in the memory cell area of the DRAM. Thereafter, high dielectric films 11 are deposited on the storage electrodes 9a and the counter electrodes 12 of the capacitor are formed simultaneously with the metallic wiring M1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a device structure useful for efficiently forming a storage capacitor electrode in a storage (stack) type dynamic RAM (DRAM) or the like. , And a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device in which a functional circuit such as a DRAM and a logic circuit such as a microprocessor or an application specific integrated circuit (ASIC) are mounted on the same semiconductor substrate, a storage capacitor electrode of a memory cell of the DRAM is used. And the wiring of the logic circuit are formed separately. Hereinafter, a semiconductor device in which such a DRAM and a logic circuit are mounted together will be exemplified.

FIG. 20 shows a DRA comprising two layers of metal wiring.
1 shows an example of a conventional semiconductor device in which a logic circuit using M and five layers of metal wiring and using a DRAM is mounted on the same semiconductor substrate. Here, FIG. 20A shows a partial sectional structure of a DRAM region, and FIG. 20B shows a partial sectional structure of a logic circuit region. 21 to 23 show an outline of the manufacturing process. Also in FIGS. 21 to 23, each figure (a) shows a partial sectional structure of a DRAM region, and each figure (b) shows a partial sectional structure of a logic circuit region.

An outline of a method of manufacturing the semiconductor device will be described below with reference to FIGS. At the time of manufacturing, first, as shown in FIGS. 21A and 21B, after forming a field oxide film 2 for element isolation on a Si (silicon) substrate 1, a gate oxide film 3 and polycrystalline silicon are formed. A gate electrode 4, a word line (gate wiring) 4a, a silicon oxide film 5 covering the upper part thereof, and diffusion layers 6 and 6a are formed. After an interlayer insulating film 217 is formed thereon by a CVD method, the interlayer insulating film 21 is formed by a photoresist process and a dry etching process.
7 is opened for forming a capacitor.

Next, in the DRAM region, the thin film deposition, the photoresist process, and the dry etching process are repeated, so that the storage electrode 201, the capacitor insulating film 202, and the counter electrode 20 of the capacitor shown in FIG.
3 are sequentially formed. Then, an interlayer insulating film 204 including the logic circuit region is formed thereon.

Next, in the DRAM region, as shown in FIG. 23A, the wirings and the interlayer insulating films are alternately deposited and processed to form bit lines 206 made of a polycrystalline silicon film and a tungsten polycide film. Then, a contact hole 205 connecting the bit line 206 and the diffusion layer 6a is formed. After that, an interlayer insulating film 207 is formed so as to cover the upper portion including the logic circuit region.

[0007] Then, as shown in FIGS. 20A and 20B, the backing wiring 208 of the DRAM and the first metal wiring M1 in the logic circuit area are simultaneously formed, and an interlayer insulating film 209 is formed thereon. Form. Next, the power supply line 210 in the DRAM area and the second metal wiring M2 in the logic circuit area
Are also formed at the same time. As a result, the formation of all the wirings in the DRAM region is completed, and the passivation film (interlayer insulating film) 211 including the logic circuit region on the power supply line 210 is completed.
To form

Thereafter, in the logic circuit region, metal wires and interlayer insulating films 212 to 213 are alternately deposited and processed in the same manner to form third metal wires M3, fourth metal wires M4, and fifth metal wires M5. FIG.
The wiring formation in the logic circuit region as shown in FIG. 2B is completed, and the wiring of the semiconductor device is completed. FIG. 24 summarizes the structure of the semiconductor device manufactured as described above.

[0009]

By the way, as described above, the storage electrode 201 and the counter electrode 203 of the capacitor in the DRAM area are formed separately from the wiring in the logic area, and in recent years, the wiring in the logic area has been multi-layered. At present, as shown in FIG. 24, although three wirings are simultaneously formed as common wirings, a total of nine wiring steps are required. As described above, when the DRAM region having the stacked memory cell and the logic circuit region are mixedly mounted, the increase in the number of wiring steps due to the formation of the electrode of the capacitor increases the number of steps of manufacturing the same semiconductor device, and as a result, Manufacturing costs are to be increased.

[0010] Further, even in a single DRAM, the structure of the memory cell portion, particularly the capacitor of the cell portion, is complicated with the high integration, and the wiring of the peripheral circuit is multi-layered with the high performance of the circuit. DRAM, which tends to be mentioned above
The same problem as in the case where the area and the logic circuit area are mixed is not negligible.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a structure capable of suppressing an increase in the number of manufacturing steps required for forming electrodes while securing performance as a capacitor. And a method of manufacturing the same.

[0012]

To achieve the above object, according to the present invention, in a semiconductor device having a capacitor, a metal wiring in which a lower electrode of the capacitor is buried in a conductive hole in an interlayer. Its gist is that it is formed using a material.

According to the above configuration, the capacitor can be formed by efficiently using the wiring region on the semiconductor substrate. According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the metal wiring material serving as the lower electrode diffuses and reacts between the layer materials to be conductive in the inter-layer conductive holes. The gist of the invention is that it is a barrier metal that prevents

According to the above configuration, since the lower electrode of the capacitor, that is, the storage electrode, is formed including the inner wall and the bottom surface of the inter-layer conductive hole, the electrode area can be easily secured, and the capacitor as a capacitor can be easily obtained. It is easy to secure an effective area. In addition, since the lower electrode is formed of a barrier metal, a capacitor can be formed with a more stable structure in characteristics.

According to a third aspect of the present invention, in the semiconductor device having the capacitor, the first electrode in which the lower electrode of the capacitor is embedded in the inner wall and the bottom surface of the interlayer conductive hole.
And that the upper electrode of the capacitor is formed using a second metal wiring material embedded in the inter-layer conductive hole via an appropriate dielectric film. This is the gist.

According to the above configuration, the lower electrode of the capacitor, that is, the storage electrode is formed including the inner wall and the bottom surface of the inter-layer conductive hole, so that the electrode area can be easily secured, and the effective capacitor as a capacitor can be obtained. It is easy to secure the area.

According to the fourth aspect of the present invention, in the third aspect,
In the semiconductor device described above, the first metal wiring material is a metal material containing Ti (titanium) or Ta (tantalum), and the second metal wiring material is W (tungsten), Al (aluminum), or Cu. Its gist is that it is a metal material containing (copper).

A metal material containing Ti (titanium) or Ta (tantalum) is a material suitable as a barrier metal in the above-mentioned inter-layer conductive holes, and W (tungsten), Al
A metal material containing (aluminum) or Cu (copper) is a suitable material as a metal material to be buried in the inter-layer conductive holes. Therefore, according to the above configuration, a capacitor can be formed with a structure that is stable in characteristics.

According to the fifth aspect of the present invention, in the first aspect,
5. The semiconductor device according to any one of items 1 to 4, wherein the interlayer conductive hole is a contact hole electrically connected to an (impurity) diffusion layer formed in a semiconductor substrate of the semiconductor device. I do.

According to the above structure, since the lower electrode of the capacitor can be formed immediately above the semiconductor substrate, that is, at a stage before wiring or the like is formed, the lower electrode is formed on the surface for forming the capacitor. The dielectric film can be subjected to high heat treatment. That is, the choice of materials for the dielectric film increases, and a high-performance capacitor can be formed.

Further, according to the invention described in claim 6, according to claim 1,
In the semiconductor device according to any one of the above (1) to (4), the gist is that the inter-layer conductive hole is a via hole for establishing conduction between upper metal wirings of the semiconductor device.

According to the above configuration, a capacitor can be formed at an arbitrary position on the upper layer of the semiconductor device. Therefore, the degree of freedom regarding the shape of the capacitor is increased, such as securing the electrode area of the storage electrode, which is the lower electrode, and
Capacitor performance can be easily ensured.

According to a seventh aspect of the present invention, in the semiconductor device having the capacitor, a part of the metal wiring material in which the lower electrode of the capacitor is embedded in the interlayer conductive hole in a region other than the capacitor in the semiconductor device. The gist of the invention is that it is formed using A semiconductor device characterized by the above-mentioned.

According to the above structure, the capacitor can be formed by efficiently using the wiring region on the semiconductor substrate. According to the same configuration, for example, even in a semiconductor device in which the above-described functional circuit and a logic circuit using this functional circuit are mixedly mounted on the same semiconductor substrate, the formation of the lower electrode of the capacitor and the logic circuit, for example, , And the number of manufacturing steps (wiring steps) can be easily reduced.

According to the invention described in claim 8, according to claim 7,
The semiconductor device according to the aspect, wherein the metal wiring material serving as the lower electrode is a barrier metal that prevents diffusion and reaction between the layer materials to be conductive in the inter-layer conductive holes. .

According to the above configuration, the lower electrode of the capacitor, that is, the storage electrode, can be formed so as to include the inner wall and the bottom surface of the inter-layer conductive hole. Therefore, it is easy to secure the electrode area, and it is also easy to secure the effective area as a capacitor. In addition, since the wiring in the region other than the lower electrode and the capacitor is formed of the barrier metal, the capacitor and its peripheral circuits can be formed with a more stable structure in characteristics.

According to a ninth aspect of the present invention, in the semiconductor device having a capacitor, the lower electrode of the capacitor is embedded in the inner wall and the bottom surface of the interlayer conductive hole in a region other than the capacitor in the semiconductor device. The upper electrode of the capacitor is formed by using a part of the metal wiring material of the first metal wiring material, and the upper electrode of the second metal wiring material is embedded in the conductive hole of the interlayer in order to establish conduction between the target interlayers. The gist of the invention is that it is formed using a part.

According to the above structure, the lower electrode of the capacitor, that is, the storage electrode can be formed so as to include the inner wall and the bottom surface of the inter-layer conductive hole. Therefore, the electrode area can be easily ensured, and the effective area of the capacitor can be improved. Is also easy to secure. Further, in this case, the capacitor can be formed by using a technique for forming a normal inter-layer conductive hole in the wiring region, so that the manufacture thereof is also easy.

According to a tenth aspect of the present invention, in the semiconductor device according to the ninth aspect, the first metal wiring material is a metal material containing Ti (titanium) or Ta (tantalum), and The gist is that the metal wiring material is a metal material containing W (tungsten), Al (aluminum), or Cu (copper).

As described above, Ti (titanium) or Ta
A metal material containing (tantalum) is a suitable material as a barrier metal in the above-described inter-layer conductive holes, and a metal material containing W (tungsten), Al (aluminum), or Cu (copper) is used as a conductive material. It is a material suitable as a metal material to be embedded in a hole. Therefore, according to the above configuration, the capacitor and its peripheral circuits can be formed with a structure that is stable in characteristics.

According to the eleventh aspect of the present invention, in the method for manufacturing a semiconductor device having a capacitor, a step of forming two or more layers of metal including the inner wall of the hole, Removing at least a part of the upper metal film, and the remaining metal film layer is used as a lower electrode of the capacitor.

According to a twelfth aspect of the present invention, in the method for manufacturing a semiconductor device having a capacitor, a step of forming two or more layers of metal including the inner wall of the hole, Removing at least a part of the upper metal film, forming a dielectric film on the surface from which the uppermost metal film has been removed, and further forming a metal on the surface of the formed dielectric film And forming the capacitor including the steps of:

According to a thirteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the eleventh or twelfth aspect,
The hole is an inter-layer conductive hole, and as a metal used as a lower electrode of the capacitor, a barrier metal that prevents diffusion and reaction between layer materials to be conductive in the same inter-layer conductive hole is used. This is the gist.

According to the manufacturing method of the present invention, a high-capacitance capacitor having a large effective area can be obtained by diverting a normal technique for forming a conductive hole in a wiring region such as a contact hole or a via hole. It can be easily manufactured. In particular, when the barrier metal is used as the metal for the lower electrode, a semiconductor device having a capacitor with a more stable structure in characteristics can be manufactured.

According to a fourteenth aspect of the present invention, in the method for manufacturing a semiconductor device, a functional circuit having a capacitor and a logic circuit having two or more layers of metal wiring are formed on the same semiconductor substrate. And the barrier layer of the inter-layer conduction hole in the logic circuit is formed simultaneously with the same metal material, and the upper electrode of the capacitor and the metal wiring of the logic circuit are formed simultaneously.

As described above, the logic circuit is provided with a plurality of metal wirings, and the stacked functional circuit is provided with various metal wirings for driving the same, including capacitance elements (capacitors). However, according to the manufacturing method, the lower and upper electrodes of the capacitor are formed in common with the barrier metal and metal wiring formed in the logic circuit,
The number of wiring steps as the semiconductor device is reduced.

According to a fifteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourteenth aspect, the inter-layer conductive hole is formed in an (impurity) diffusion layer formed in a semiconductor substrate of the semiconductor device and an upper layer thereof. The gist of the invention is to form a connection with a metal wiring to be formed, and to form an upper electrode of the capacitor by embedding the metal wiring material in an interlayer conductive hole.

According to the above-described manufacturing method, when forming the lower and upper electrodes of the capacitor, the electrode area can be increased by using the inter-layer conductive holes, and the capacitance of the capacitor can be suitably increased. In addition, the number of wiring layers can be reduced, and the dielectric film of the capacitor can be subjected to high heat treatment. That is, the choice of materials for the dielectric film increases, and a high-performance capacitor can be formed.

According to a sixteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fourteenth aspect, the inter-layer conductive hole is formed so as to establish electrical continuity between upper metal wirings of the semiconductor device. The gist is that the upper electrode is formed by burying the metal wiring material in the interlayer conductive hole.

According to the above-described manufacturing method, when forming the lower and upper electrodes of the capacitor, the electrode area can be increased by using the inter-layer conductive holes, and the capacitor capacity can be suitably increased. In addition, a capacitor can be formed at an arbitrary position on the upper layer of the semiconductor device. Therefore, the degree of freedom regarding the shape of the capacitor is increased, such as securing the electrode area of the storage electrode serving as the lower electrode, and the performance of the capacitor is easily secured.

According to the seventeenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which a stacked dynamic RAM and a logic circuit having a plurality of layers of metal wiring and utilizing the dynamic RAM are formed on the same semiconductor substrate. An interlayer insulating film is deposited on a diffusion layer formed on a semiconductor substrate in a region where the dynamic RAM and the logic circuit are formed, and a diffusion layer and a metal wiring are electrically connected at a predetermined position in the interlayer insulating film. Forming a contact hole to be formed, forming a barrier metal film on the interlayer insulating film and in the contact hole, burying a filling material made of a conductive material in the contact hole, The dynamic RA
Removing the filling material only in the contact holes formed in the M memory cell region to expose the barrier metal film to form a storage electrode of a capacitor; and depositing a high dielectric material film on the storage electrode Simultaneously forming a counter electrode of a capacitor on the high-dielectric material film in the formation region of the dynamic RAM, and simultaneously forming a first metal wiring thereof as a common wiring layer in the formation region of the logic circuit. And a connection wiring of the counter electrode in the dynamic RAM forming region, and a second wiring of the second layer in the logic circuit forming region, on an upper layer of a wiring layer including a counter electrode of the capacitor and a first metal wiring. Simultaneously forming each of the metal wirings as a common wiring layer; and forming a wiring comprising a connection wiring of the counter electrode and a metal wiring of a second layer. Forming a gate backing wire in the dynamic RAM forming region and a third metal wiring in the logic circuit forming region as a common wiring layer simultaneously above the layer; The power supply line in the dynamic RAM forming region and the fourth metal wiring in the logic circuit forming region are provided on a common wiring layer above the wiring layer including the wiring and the third metal wiring. And a step of forming them simultaneously.

According to the above-described manufacturing method, the number of wiring layers can be significantly reduced in a semiconductor device in which the stacked dynamic RAM and the logic circuit are mounted together. Further, according to the manufacturing method, when forming the lower and upper electrodes of the capacitor, the electrode area can be increased by using the inter-layer conductive hole, and the capacitor capacity can be suitably increased.

According to the invention, a method of manufacturing a semiconductor device in which a stacked dynamic RAM and a logic circuit having a plurality of layers of metal wiring and utilizing the dynamic RAM are formed on the same semiconductor substrate. In the above, on a transistor formed on the semiconductor substrate,
Simultaneously forming the bit line in the formation area of the dynamic RAM and the first layer metal wiring as a common wiring layer in the formation area of the logic circuit; On the wiring layer made of wiring, the storage electrode connection wiring of the capacitor is formed simultaneously as the common wiring layer in the formation area of the dynamic RAM, and the second metal wiring is formed as the common wiring layer in the formation area of the logic circuit. Depositing an interlayer insulating film between metal wirings in a formation region of the dynamic RAM and the logic circuit, and forming a via hole between metal wirings at a predetermined position in the interlayer insulating film; Forming a barrier metal film in the via hole, and embedding a filling material made of a conductive material in the via hole Forming a storage electrode of a capacitor by exposing the barrier metal film by removing the burying material only in the via hole formed in the memory cell region of the dynamic RAM among the via holes; A step of depositing a dielectric material film and a common electrode of a capacitor on the high dielectric material film in the formation region of the dynamic RAM, and a third metal wiring in the formation region of the logic circuit. Simultaneously forming a wiring layer of the capacitor, and forming a gate-backed wiring in the formation area of the dynamic RAM on an upper layer of the wiring layer including the counter electrode of the capacitor and the third metal wiring. Then, the step of simultaneously forming the fourth metal wiring as a common wiring layer and the step of forming the gate backing A power supply line is formed in the dynamic RAM forming region, and a fifth metal wiring is formed in the logic circuit forming region in a layer above the wiring layer including the wiring and the fourth metal wiring. And a step of forming them simultaneously.

According to the above manufacturing method, it is possible to reduce the maximum number of wiring layers in a semiconductor device in which the above-mentioned stacked dynamic RAM and its logic circuit are mixedly mounted. According to this manufacturing method, the degree of freedom in designing the capacitor is increased, and the storage electrode and the counter electrode are formed in the dynamic RA.
Since M can be formed flat in the upper layer of the circuit, the film thickness can be made uniform and the reliability of the device can be improved.

[0045]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail with reference to FIGS.

FIG. 1 shows a DRAM which is a functional circuit having a capacitor as a semiconductor device according to the present embodiment.
2 shows a partial cross-sectional structure of a semiconductor device in which a logic circuit having five layers of metal wiring and using the same DRAM is formed on the same semiconductor substrate. Here, FIG.
M memory cell area (hereinafter simply referred to as DRAM area)
1B shows a partial cross-sectional structure, and FIG. 1B shows a partial cross-sectional structure of a logic circuit region.

First, the wiring structure of each wiring layer in the semiconductor device of the present embodiment will be described with reference to FIG. The wiring of the first layer is formed as the gate electrode 4 and the like in each of the DRAM region and the logic circuit region as in the related art. In the first layer,
The lower electrode (storage electrode) 9a of the capacitor in the DRAM region is formed by the barrier metal film (first metal wiring material) 9 of the second-layer wiring (the first metal wiring M1 and the like).

The next wiring of the second layer is common as the counter electrode 12 and the bit line 12a of the capacitor in the DRAM region, and as the first metal wiring (second metal wiring material) M1 in the logic circuit region. It is formed on the wiring layer.

The next wiring of the third layer serves as a connecting wiring 17 for connecting the respective counter electrodes 12 in the DRAM region.
In the logic circuit area, the second metal wiring M2 is also formed on a common wiring layer.

The next fourth layer wiring is formed in a common wiring layer as a gate backing wiring 22 in the DRAM area and as a third metal wiring M3 in the logic circuit area.

The wiring of the fifth layer is formed as a power supply line 27 in the DRAM area and as a fourth metal wiring M4 in the logic circuit area, also in the common wiring layer.

Finally, the sixth layer wiring is formed as a fifth metal wiring M5 only in the logic circuit region. FIG. 2 summarizes such a wiring structure of the semiconductor device of the present embodiment for each common wiring layer.

Next, a method of manufacturing a semiconductor device according to the present embodiment will be described with reference to FIG. 1 and FIGS. 3 to 9, each figure (a) shows a partial sectional structure of a DRAM region, and each figure (b) shows a partial sectional structure of a logic circuit region.

First, as shown in FIGS. 3A and 3B,
After a field oxide film 2 for element isolation is formed on a Si (silicon) substrate 1, a gate oxide film 3, a gate electrode 4 of a transistor made of polycrystalline silicon, a silicon oxide film 5 covering an upper portion thereof, and a diffusion layer 6 , 6a are formed in the DRAM area and the logic circuit area. In the DRAM area, a word line (gate wiring) 4a is formed together with the gate electrode 4. The gate electrode 4 and the word line (gate wiring) 4a are simultaneously formed in the DRAM region and the logic circuit region, respectively, as a first layer wiring. After that, the first metal wiring interlayer insulating film 7 is formed thereon by, for example, the CVD method in both the above regions.

Subsequently, as shown in FIGS. 4A and 4B, contact holes (interlayer conductive holes) 8 are formed at predetermined positions in the DRAM region and the logic circuit region.
Thereafter, the underlying barrier metal film 9 of the first metal wiring M1 made of, for example, TiN (titanium nitride) and Ti (titanium)
Is formed on the inner surface of the contact hole 8 and the interlayer insulating film 7 under the first metal wiring by a sputtering method or the like.
Thereafter, the contact hole 8 is buried with a burying material 10 such as W (molybdenum) by a CVD method or the like.

Subsequently, as shown in FIGS. 5A and 5B, an insulating film 51 such as a SiO2 (silicon oxide) film is deposited on both regions so that a portion of the DRAM region to be a capacitor is exposed. Insulating film 5 by photolithography
1 is removed by patterning.

Next, first, as shown in FIG. 6A, by immersing in a hydrogen peroxide solution, a filling material (tungsten) in the contact hole 8 where the insulating film 51 is removed in the DRAM region. 10 and the above Ti
The barrier metal film 9 such as N / Ti is exposed. In the present embodiment, as described above, lower electrode (storage electrode) 9a of the capacitor is formed by barrier metal film 9.

Subsequently, as shown in FIGS. 6A and 6B, a high dielectric material film 11 such as a Ta2O5 (ditanium pentoxide) film is deposited in each of the above regions by a CVD method or the like. .

Next, as shown in FIGS. 7A and 7B,
After covering only the portion to be a capacitor in the DRAM region with the photoresist 52, the base barrier metal film 9, which is deposited on the first metal wiring lower interlayer insulating film 7 except for the portion to be the capacitor by dry etching or the like, Insulating film 5
1 and the high dielectric material film 11 are removed. As a result, the storage electrode 9a of the capacitor is formed by the underlying barrier metal film 9, and the capacitance insulating film 11a of the capacitor is formed by the high dielectric material film 11, respectively.

That is, in this embodiment, the DRA
The capacitor constituting the memory cell in the M region is formed using the contact hole 8. At this time, since the storage electrode 9a is formed using the inner wall of the contact hole 8, a wider electrode area as a capacitor can be secured. As a result, a sufficient capacity as a capacitor can be secured, and the number of steps for forming the storage electrode 9a can be reduced.

Next, as shown in FIGS. 8A and 8B,
After the photoresist 52 is ashed and removed, the DRA
In the M region, the counter electrode 12 and the bit line 12a, which are the upper electrodes of the capacitors, are used. In the logic circuit region, the first metal wiring M1 is used as the second layer wiring, and is made of the same material, for example, aluminum. Form at the same time.

Thus, the counter electrode 12 of the capacitor
Are formed at the same time as the first metal wiring M1 in the logic circuit region, so that the number of steps required to form the counter electrode 12 is also reduced. Further, the barrier metal film 9 forming the storage electrode 9a of the capacitor serves as the barrier metal film 9 of the first metal wiring M1 in the logic circuit region.

Subsequently, as shown in FIGS. 9A and 9B, a first-second metal wiring interlayer insulating film 13 is deposited in each of the above regions, and the first-second metal A via hole (interlayer conductive hole) 14 between wirings is formed. Then, an underlying barrier metal film 15 of the second metal wiring M2 made of, for example, TiN / Ti is formed on the inner wall of the via hole 14 and on the interlayer insulating film 13 by a sputtering method or the like.
Thereafter, the via hole 14 is filled with a filling material 16 such as W by a CVD method or the like, and then the TiN / Ti thin film and the filling material 16 are filled with the via hole 14 by an etch-back method.
Remove all parts.

Further, as shown in FIGS. 9 (a) and 9 (b), a connection line 17 for connecting the counter electrodes 12 to each other is provided in the DRAM region, and a connection is provided in the logic circuit region. In this case, the second metal wirings M2 are simultaneously formed of the same material, for example, aluminum as the wirings of the third layer.

Subsequently, as shown in FIGS. 1 (a) and 1 (b), the gate backing wiring 22 is provided in the DRAM area, and the gate backing wiring 22 is provided in the logic circuit area. The three metal wirings M3 are simultaneously formed of the same material, for example, aluminum as the wiring of the fourth layer.
An interlayer insulating film 23 is formed thereon in each region, and a via hole 24 is similarly formed in the logic circuit region, a barrier metal film 25 is formed, and the hole 24 is buried with a burying material 26 such as W. I do.

Next, as shown in FIGS. 1A and 1B, the power supply line 27 is located in the DRAM area, and the fourth metal is located in the logic circuit area. The wiring M4 is simultaneously formed of the same material, for example, aluminum as the fifth layer wiring. As a result, all the wirings in the DRAM region are completed, and a passivation film (interlayer insulating film) 28 is formed on the power supply line 27 including the logic circuit region.

Thereafter, in the logic circuit region, as shown in FIG. 1B, a via hole 29 is similarly formed, a barrier metal film 30 is formed, and filling is performed with a filling material 31 such as W. . Then, the fifth metal wiring M5 is formed, for example, of aluminum as a sixth-layer wiring. Finally, passivation film 3 is formed in the logic circuit area.
2 is completed to complete the semiconductor device.

As described above, in addition to the bit line 12a in the DRAM area, the upper electrode (counter electrode) of the capacitor
12, the connection wiring 17, the gate backing wiring 22, and the power supply line 27 are formed simultaneously with each metal wiring in the logic circuit area, so that the number of layers and man-hours required for the wiring can be reduced as compared with the conventional semiconductor device. become.

As described above, according to the semiconductor device of this embodiment and the method of manufacturing the same, the following effects can be obtained. (1) Capacitor storage electrode 9a of DRAM memory cell
Is formed by the underlying barrier metal film 9. The storage electrode 9a is formed using the inner wall of the contact hole 8. Therefore, a large electrode area can be secured as a capacitor, a sufficient capacity can be secured as a capacitor, and the number of steps for forming the storage electrode 9a can be reduced.

(2) For the upper electrode (opposite electrode) 12 of the capacitor, the inner wall of the contact hole 8 is used and the first metal wiring M in the logic circuit region is used.
Since it is formed at the same time as 1, the formation is suitable and easy.

(3) Since the storage electrode 9a of the capacitor can be formed immediately above the semiconductor substrate 1, that is, at a stage before aluminum wiring or the like is formed, a film is formed on the surface for forming the capacitor. The high dielectric material film 11 can be subjected to high heat treatment.
That is, the choice of materials for the dielectric film increases, and a high-performance capacitor can be formed. (4) In the present embodiment, the bit line 12a, the upper electrode 12 of the capacitor, the connection wiring 17,
The gate backing wiring 22 and the power supply line 27 are formed simultaneously with each metal wiring in the logic circuit area. As a result, it is possible to reduce the number of steps required for wiring as compared with a conventional semiconductor device in which a functional circuit having a capacitor and a logic circuit are formed on the same semiconductor substrate.

The above embodiment can be modified and implemented as follows. The cross-sectional shape of the electrode of the capacitor is not limited to that shown in FIG. 8A, and may be, for example, a cross-sectional shape shown in FIG. With the shape shown in FIG. 10, the electrode area can be further increased, and the capacity of the memory cell as a capacitor can be further increased.

(Second Embodiment) Next, a second embodiment of a semiconductor device and a method of manufacturing the same according to the present invention will be described.
This will be described in detail with reference to FIGS. The same elements as those of the semiconductor device according to the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted. The differences will be mainly described below.

FIG. 11 shows a DRAM as a functional circuit having a capacitor as a semiconductor device according to the present embodiment.
2 shows a partial cross-sectional structure of a semiconductor device in which a logic circuit having five layers of metal wiring is formed on the same semiconductor substrate. Here, FIG. 11A shows a partial cross-sectional structure of the DRAM region, similarly to FIG. 1, and FIG. 11B shows a partial cross-sectional structure of the logic circuit region.

First, the outline of the wiring structure of each wiring layer in the semiconductor device of the present embodiment will be described with reference to FIG. The first-layer wiring is formed as the gate electrode 4 and the like in each of the DRAM region and the logic circuit region, as in the first embodiment.

The next second layer wiring is formed in a common wiring layer as the bit line 12a or the like in the DRAM area, and as the first metal wiring M1 in the logic circuit area.

The next third layer wiring is the second storage electrode connecting wiring 17b of the capacitor in the DRAM area, and the second metal wiring M in the logic circuit area.
2 is also formed on a common wiring layer. In addition,
In the third layer, a lower electrode (storage electrode) of the capacitor in the DRAM region is formed by a barrier metal film (first metal wiring material) 20 of a fourth layer wiring (third metal wiring M3 and the like) described below. ) 20a are formed.

The next wiring of the fourth layer is formed in the common wiring layer as the counter electrode 22a of the capacitor in the DRAM area and as the third metal wiring (second metal wiring material) M3 in the logic circuit area. Have been.

The next fifth layer wiring is also formed in the common wiring layer as a gate backing wiring 27a in the DRAM area and as a fourth metal wiring M4 in the logic circuit area.

The wiring of the next sixth layer is formed in the same wiring layer as the power supply line 33 in the DRAM area and as the fifth metal wiring M5 in the logic circuit area.

Finally, a passivation film 34 is formed in the DRAM region and the logic circuit region, and the semiconductor device is completed. Such a wiring structure of the semiconductor device of the present embodiment is summarized in FIG. 12 for each common wiring layer.

Next, a method of manufacturing the semiconductor device of the present embodiment will be described with reference to FIG. 11 and FIGS. 13 to FIG. 19, each figure (a) is a D
A partial cross-sectional structure of a RAM area is shown, and each figure (b) shows a partial cross-sectional structure of a logic circuit area.

First, as shown in FIGS. 13A and 13B, after a field oxide film 2 for element isolation is formed on a Si (silicon) substrate 1, a gate oxide film 3 and polycrystalline silicon are formed. The gate electrode 4 of the transistor, the silicon oxide film 5 covering the upper part thereof, and the diffusion layers 6 and 6a are formed by a DRAM.
Formed in the region and the logic circuit region. In addition, DRAM
In the region, a word line (gate wiring) 4 a is formed together with the gate electrode 4. The gate electrode 4 and the word line (gate wiring) 4a are simultaneously formed in the DRAM region and the logic circuit region, respectively, as a first layer wiring. After that, the first metal wiring interlayer insulating film 7 is formed thereon by, for example, the CVD method in both the above regions.

Subsequently, in each of the above regions, after a contact hole (interlayer conductive hole) 8 is formed at a predetermined position, the underlying barrier metal film 9 of the first metal wiring M1 made of, for example, TiN / Ti is formed by a sputtering method or the like. It is formed on the inner surface of the contact hole 8 and on the interlayer insulating film 7 under the first metal wiring. Thereafter, the contact hole 8 is buried with a burying material 10 such as W (tungsten) by a CVD method or the like. After that, the barrier metal film 9 and the burying material 10 are removed by an etch-back method except for the contact holes 8.

Thereafter, as shown in FIGS. 14A and 14B, the bit line 12a and the first storage electrode connecting wiring 12b are arranged in the DRAM area, and the logic circuit area is formed in the DRAM area. In this case, the first metal wiring M1 is simultaneously formed of the same material, for example, aluminum, as the wiring of the second layer.

Subsequently, as shown in FIGS. 14A and 14B, in each of the above regions, the first and second interlayer insulating films 13 between metal wirings are deposited, and the first and second interlayer insulating films 13 are formed at predetermined positions. A via hole (interlayer conductive hole) 14 between metal wirings is formed.
Then, for example, a second metal wiring M made of TiN / Ti
The barrier metal film 15 of the second base is formed on the inner surface of the via hole 14 and the interlayer insulating film 13 by sputtering or the like.
Form on top. After that, the via hole 14 is filled with a filling material 16 such as W (tungsten) by a CVD method or the like. After that, the barrier metal film 15 and the burying material 16 are removed by an etch-back method except for the via holes 14.

Further, as shown in FIGS. 14A and 14B, the second storage electrode connecting wiring 17b is provided in the DRAM area, and the second storage electrode connecting wiring 17b is provided in the logic circuit area. The metal wirings M2 are simultaneously formed of the same material, for example, aluminum, as the third-layer wirings.

Next, as shown in FIGS. 15A and 15B, in each of the above regions, a second-third metal interlayer insulating film 18 is deposited, and the second-third metal Via holes (interlayer conductive holes) 19 and 19a between wirings are formed. The via hole 19a formed in the DRAM region
Is larger than the diameter of the via hole 19 formed in the logic circuit area as shown in FIGS. 15 (a) and 15 (b).

Then, for example, a third layer of TiN / Ti
The barrier metal films 20 and 20a of the metal wiring M3 are formed on the inner surfaces of the via holes 19 and 19a and on the interlayer insulating film 18 by a sputtering method or the like. Thereafter, the via holes 19 and 19a are buried by a burying material 21 such as W (tungsten) by a CVD method or the like. After that, the barrier metal films 20, 20a and the filling material 21 are removed by an etch-back method except for the via holes 19, 19a. Subsequently, as shown in FIGS. 15A and 15B, the photoresist 53 is covered except for the memory cell region of the DRAM.

Next, as shown in FIG.
In the M region, the interlayer insulating film 18 between the second and third metal wirings is removed by, for example, a dry etch back method so that the second storage electrode connecting wiring 17b is not exposed. continue,
For example, by invading hydrogen peroxide solution, DRAM
The filling material 21 of the via hole 19a between the second and third metal wirings in the memory cell region is removed. Thereby, the D
In the RAM area, only the barrier metal film 20 of the third metal wiring M3, for example, TiN / Ti is exposed as a wiring material. In the present embodiment, the barrier metal film 20 of the third metal wiring M3 forms the storage electrode 20a of the capacitor.

Next, as shown in FIGS. 17A and 17B, after the photoresist 53 is ashed and removed, a high dielectric material film 11a such as the Ta2O5 film is formed by CVD or the like. accumulate.

Next, as shown in FIGS. 18A and 18B, only the photoresist 54 is provided only in the memory cell region of the DRAM.
After that, the DR
The high dielectric material film 11a deposited outside the memory cell region of the AM is removed.

Next, as shown in FIGS. 19A and 19B, after the photoresist 54 is ashed and removed,
In the RAM area, the counter electrode 22a, which is the upper electrode of the capacitor, and in the logic circuit area, the third metal wiring M3 is simultaneously formed as the fourth layer wiring using the same material, for example, aluminum.

As described above, also in the present embodiment, DR
The capacitor forming the memory cell in the AM area is the
It is formed using the third metal via hole 19a. That is, the storage electrode 2 which is the lower electrode of the capacitor
Numeral 0a is formed by the barrier metal film 20 of the third metal wiring M3, and the counter electrode 22a as the upper electrode is formed by the third metal wiring M3. At this time, as in the first embodiment, since the storage electrode 20a is formed using the inner wall of the via hole 19a, a wide electrode area can be secured as a capacitor. as a result,
A sufficient capacity as a capacitor can be secured, and the number of steps required for forming the storage electrode 20a can be reduced. Moreover, in the present embodiment, since this capacitor is formed in the upper layer of the wiring layer, the degree of freedom in designing the formation of the capacitor is also increased.

Subsequently, as shown in FIGS. 11 (a) and 11 (b), after the third to fourth inter-metal-wiring interlayer insulating films 23 are deposited in each of the above regions, the DRAM regions are not used. The gate backing wiring 27a and the fourth metal wiring M4 in the logic circuit region are formed simultaneously as the fifth layer wiring by using the same material, for example, aluminum. Thereafter, as shown in FIGS. 11A and 11B, the fourth to fifth metal wiring interlayer insulating films 28 are deposited in the respective regions. Then, at the predetermined position in the logic circuit area,
A via hole 29 between fifth metal wirings is formed, a barrier metal film 30 is formed in the via hole 29, and a filling material 31 such as W (tungsten) is buried.

Subsequently, as shown in FIGS. 11A and 11B, a power supply line 33 is provided in the DRAM region, and a fifth metal wiring M5 is provided in the logic circuit region. The wiring of the sixth layer is simultaneously formed of the same material, for example, aluminum. And finally, D
The passivation film 34 is formed in the RAM area and the logic circuit area, and the semiconductor device is completed.

As described above, also in the present embodiment, D
In addition to the bit line 12a in the RAM area, the upper electrode (opposite electrode) 22a of the capacitor, the gate line 2
By forming the power supply line 7a and the power supply line 33 at the same time as each metal wiring in the logic circuit area, the number of wiring layers and the number of steps can be reduced as compared with the conventional semiconductor device.

As described above, according to the semiconductor device of the second embodiment and the method of manufacturing the same, the following effects can be obtained. (1) In the present embodiment, the storage electrode 20a, which is the lower electrode of the capacitor, is formed of the barrier metal film 2 of the third metal wiring M3.
0, and the counter electrode 22a as the upper electrode is formed by the third metal wiring M3. At this time, as in the first embodiment, since the storage electrode 20a is formed using the inner wall of the via hole 19a, a wide electrode area can be secured as a capacitor.
As a result, a sufficient capacity can be secured as a capacitor, and the number of steps required for forming the storage electrode 20a can be reduced. In addition, since the capacitor is formed in the upper layer portion of the wiring layer on which the memory element is formed, the degree of freedom in designing the capacitor is increased. (2) In the present embodiment, the counter electrode 27a of the capacitor constituting the DRAM, the gate backing wiring 27a, and the power supply line 33 are each formed on the upper layer of the circuit forming the DRAM by a separate metal wiring of the logic circuit. The structure is shared. Therefore, the degree of freedom in designing the capacitor for the dynamic RAM is increased, and
Since the counter electrode 22a and the like can be formed flat in the upper layer of the circuit forming the same dynamic RAM, the reliability of the element performance can be improved, for example, the film thickness can be made uniform. .

The following modifications are common to the above embodiments. In each of the above embodiments, the example of the stacked dynamic RAM has been described as an example of the functional circuit included in the semiconductor device. However, the present invention is not limited to this. In short, it is only necessary that a logic circuit and a wiring layer to be mounted on the same semiconductor substrate be formed in a common layer, each having a capacitor as a functional circuit. For example, assuming that the semiconductor device itself is a stacked dynamic RAM, the memory cell portion constitutes a functional circuit, and its peripheral circuits constitute a multilayered logic circuit, and the present invention is applied to the stacked dynamic RAM. Can be.

In each of the above embodiments, the material of the lower electrode (storage electrode) of the capacitor of the memory cell is T
Although an example in which a metal containing Ti (titanium) such as i and TiN is used has been shown, other metals containing Ta (tantalum) such as TaN (tantalum nitride) can also be used as the electrode material.

In each of the above embodiments, an example is shown in which Ta2O5 (tantalum pentoxide) is used as the capacitor insulating film 11a, but the present invention is not limited to this. In addition, a film material such as an alumina insulating film, strontium titanate, barium strontium titanate, or lead zirconium titanate that can be formed at a low temperature can be used.

In each of the above embodiments, the example in which the metal wirings are entirely formed of aluminum is described. However, the present invention is not limited to this. For example, each metal wiring or one of the metal wirings may be formed of W (tungsten), Cu (Copper) or the like may be used.

In each of the above embodiments, the example in which the barrier metal film, the burying material, the interlayer insulating film, and the like are removed by the etch-back method has been described. However, the present invention is not limited to this.
For example, it may be removed by a CMP (Chemical Mechanical Polishing) method. The number of metal wirings (the number of wiring layers) in each region described in each of the above embodiments is arbitrary, and is not limited thereto.

[0104]

According to the semiconductor device of the present invention, for example, in a semiconductor device in which a stacked dynamic RAM and its logic circuit are mixed, the upper and lower electrodes of the capacitor of the memory cell are electrically connected to each other between contact holes and via holes. It can be formed including the inner wall and bottom surface of the hole.
Therefore, it is easy to secure the electrode area, and it is also easy to secure the effective area as a capacitor. In addition, the number of manufacturing steps (wiring steps) can be easily reduced, for example, the electrode formation and the wiring formation in the logic circuit can be performed simultaneously.

Further, according to the method of manufacturing a semiconductor device according to the present invention, for example, in the manufacture of a semiconductor device in which a stacked dynamic RAM and its logic circuit are mixedly mounted, it is possible to significantly reduce the number of wiring steps. become able to. Further, when forming the lower and upper electrodes of the capacitor of the memory cell, the electrode area can be increased by using a contact hole or a via hole, and the capacitance of the capacitor can be suitably increased.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a partial sectional structure of a first embodiment of a semiconductor device according to the present invention;

FIG. 2 is an explanatory view generally showing a wiring layer structure of the semiconductor device according to the embodiment;

FIG. 3 is an exemplary sectional view showing the method of manufacturing the semiconductor device of the embodiment;

FIG. 4 is an exemplary sectional view showing the method of manufacturing the semiconductor device of the embodiment;

FIG. 5 is a sectional view showing the method of manufacturing the semiconductor device of the embodiment.

FIG. 6 is a sectional view showing the method of manufacturing the semiconductor device of the embodiment.

FIG. 7 is a sectional view showing the method of manufacturing the semiconductor device of the embodiment.

FIG. 8 is a sectional view showing the method of manufacturing the semiconductor device of the embodiment.

FIG. 9 is a sectional view showing the method of manufacturing the semiconductor device of the embodiment.

FIG. 10 is a sectional view showing the method of manufacturing the semiconductor device of the embodiment.

FIG. 11 is a sectional view showing a partial sectional structure of a second embodiment of the semiconductor device according to the present invention;

FIG. 12 is an explanatory view generally showing a wiring layer structure of the semiconductor device according to the first embodiment;

FIG. 13 is a sectional view showing the method for manufacturing the semiconductor device of the embodiment.

FIG. 14 is a sectional view showing the method of manufacturing the semiconductor device of the embodiment.

FIG. 15 is a sectional view showing the method of manufacturing the semiconductor device of the embodiment.

FIG. 16 is a sectional view showing the method for manufacturing the semiconductor device of the embodiment.

FIG. 17 is a sectional view showing the method of manufacturing the semiconductor device of the embodiment.

FIG. 18 is a sectional view showing the method of manufacturing the semiconductor device of the embodiment.

FIG. 19 is a sectional view showing the method of manufacturing the semiconductor device of the embodiment.

FIG. 20 is a cross-sectional view showing a partial cross-sectional structure of a conventional semiconductor device.

FIG. 21 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 22 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 23 is a cross-sectional view illustrating a method for manufacturing a conventional semiconductor device.

FIG. 24 is an explanatory diagram generally showing a wiring layer structure of a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Field oxide film, 3 ... Gate oxide film, 4 ... Gate electrode (polycrystalline silicon), 4a ... Word line (gate wiring), 5 ... Silicon oxide film, 6, 6a
... Diffusion layer, 7 ... Interlayer insulating film under first metal wiring, 8 ... Contact hole, 9 ... Barrier metal film, 9a, 20a ... Lower electrode (storage electrode) of capacitor, 9b ... Gate connecting wiring, 10 ... Filling material, 11, 11a: High dielectric material film (capacitive insulating film), 12, 22a: Upper electrode (counter electrode) of capacitor, 12a: Bit line, 12b: First storage electrode connecting wiring, 13: First-second An interlayer insulating film between metal wirings, 14 ... a via hole between the first and second metal wirings, 15 ...
Barrier metal film, 16 buried material, 17 connection wiring of capacitor counter electrode, 17b connection wiring for second storage electrode,
18 ... third-fourth metal wiring capacitance insulating film, 19, 19
a: third to fourth via holes between metal wirings, 20: barrier metal film, 21: filling material, 22, 27a: gate backing wiring, 23: fourth to fifth metal wiring interlayer insulating film, 2
4: Via hole between fourth and fifth metal wirings, 25: barrier metal film, 26: filling material, 27, 33 ... power supply line, 28
... Interlayer insulating film between fifth and sixth metal wirings, 29 ... Via hole between fifth to sixth metal wirings, 30 ... Barrier metal film, 31
... embedding material, 32, 34 ... passivation film, 51
... insulating film, 52, 52, 54 ... photoresist, M1 ...
First metal wiring, M2: second metal wiring, M3: third metal wiring, M4: fourth metal wiring, M5: fifth metal wiring.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/8234 H01L 27/10 681F 27/088 (72) Inventor Makoto Akizuki 2 Keihanhondori, Moriguchi-shi, Osaka 5-5-5 SANYO Electric Co., Ltd. F term (reference) 4M104 AA01 BB14 BB30 BB32 CC01 DD37 DD43 FF16 FF17 FF18 GG08 GG09 GG16 5F038 AC02 AC14 DF05 5F048 AA09 AB01 AC01 BA01 BF02 BF07 BF12 5F083 JA28 JA28 KA01 KA05 PR21 PR39 PR40 ZA12

Claims (18)

[Claims] 1. A semiconductor device having a capacitor,
A semiconductor device, wherein a lower electrode of the capacitor is formed by using a metal wiring material embedded in an inter-layer conductive hole. 2. The semiconductor device according to claim 1, wherein the metal wiring material serving as the lower electrode is a barrier metal which is present in the inter-layer conductive hole and prevents diffusion and reaction between layer materials to be conductive. . 3. A semiconductor device having a capacitor,
The lower electrode of the capacitor is formed using a first metal wiring material embedded in the inner wall and the bottom surface of the interlayer conductive hole, and the upper electrode of the capacitor has an appropriate dielectric film in the interlayer conductive hole. A semiconductor device formed using a second metal wiring material embedded through the semiconductor device. 4. The first metal wiring material is Ti (titanium).
4. The semiconductor device according to claim 3, wherein the second metal wiring material is a metal material containing Ta (tantalum), W (tungsten), Al (aluminum), or Cu (copper). 5. The semiconductor according to claim 1, wherein said inter-layer conductive hole is a contact hole electrically connected to an (impurity) diffusion layer formed in a semiconductor substrate of said semiconductor device. apparatus. 6. The semiconductor device according to claim 1, wherein said interlayer conductive hole is a via hole for providing electrical connection between upper metal wirings of said semiconductor device.
5. The semiconductor device according to any one of 4. 7. A semiconductor device having a capacitor,
A semiconductor device, wherein a lower electrode of the capacitor is formed by using a part of a metal wiring material embedded in an interlayer conductive hole in a region other than the capacitor in the semiconductor device. 8. The semiconductor device according to claim 7, wherein said metal wiring material serving as said lower electrode is a barrier metal which is present in said inter-layer conductive hole and prevents diffusion and reaction between layer materials to be conductive. . 9. A semiconductor device having a capacitor,
A lower electrode of the capacitor is formed by using a part of a first metal wiring material embedded in an inner wall and a bottom surface of the interlayer conductive hole in a region other than the capacitor in the semiconductor device, and a lower electrode of the capacitor is formed. An electrode is embedded in the inter-layer conduction hole to establish conduction between the target inter-layers.
A semiconductor device formed by using a part of the metal wiring material. 10. The first metal wiring material is a metal material containing Ti (titanium) or Ta (tantalum).
The second metal wiring material is W (tungsten), Al
The semiconductor device according to claim 9, wherein the semiconductor device is a metal material containing (aluminum) or Cu (copper). 11. A method of manufacturing a semiconductor device having a capacitor, wherein two or more layers of metal including an inner wall of a hole are formed, and at least a part of a topmost metal film of the formed metal film layer. And removing the remaining metal film layer as a lower electrode of the capacitor. 12. A method of manufacturing a semiconductor device having a capacitor, wherein two or more layers of metal are formed including inner walls of holes, and at least a part of the uppermost metal film of the formed metal film layer. Removing, a step of forming a dielectric film on the surface from which the uppermost metal film has been removed, and a step of further forming a metal on the surface of the formed dielectric film, A method for manufacturing a semiconductor device, comprising forming a capacitor. 13. A barrier for preventing diffusion and reaction between layer materials to be conducted in the same interlayer conductive hole as a metal serving as a lower electrode of the capacitor. The method for manufacturing a semiconductor device according to claim 11, wherein a metal is used. 14. A method of manufacturing a semiconductor device, wherein a functional circuit having a capacitor and a logic circuit having two or more layers of metal wiring are formed on the same semiconductor substrate, wherein a lower electrode of the capacitor and an interlayer in the logic circuit are provided. Simultaneously forming the barrier layer of the conduction hole with the same metal material,
A method of manufacturing a semiconductor device, comprising simultaneously forming an upper electrode of the capacitor and a metal wiring of the logic circuit. 15. The method for manufacturing a semiconductor device according to claim 14, wherein said inter-layer conductive hole is connected to an (impurity) diffusion layer formed on a semiconductor substrate of said semiconductor device and a metal wiring formed thereon. And forming an upper electrode of the capacitor by embedding the metal wiring material in the interlayer conductive hole. 16. The method of manufacturing a semiconductor device according to claim 14, wherein said inter-layer conductive holes are formed so as to establish conduction between upper metal wirings of said semiconductor device, and upper electrodes of said capacitors are electrically connected to the same inter-layer conductive layers. A method for manufacturing a semiconductor device, wherein the method is formed by embedding the metal wiring material in a hole. 17. A method of manufacturing a semiconductor device in which a stacked dynamic RAM and a logic circuit having a plurality of layers of metal wiring and utilizing the dynamic RAM are formed on the same semiconductor substrate. A step of depositing an interlayer insulating film on the diffusion layer formed in the semiconductor substrate in the formation region, and forming a contact hole at a predetermined position in the interlayer insulating film for electrically connecting the diffusion layer and the metal wiring; Forming a barrier metal film on the interlayer insulating film and in the contact hole; burying a filling material made of a conductive material in the contact hole; forming the contact hole in a memory cell region of the dynamic RAM The buried material is removed only in the contact holes that have been exposed to expose the barrier metal film. Forming a high-dielectric material film on the storage electrode; and forming a counter electrode of the capacitor on the high-dielectric material film in the formation region of the dynamic RAM. In the logic circuit formation region, a step of simultaneously forming the first metal wiring as a common wiring layer, and the step of forming the dynamic layer on the wiring layer comprising the counter electrode of the capacitor and the first metal wiring. A step of simultaneously forming a connection wiring of the counter electrode in a RAM formation region and a second metal wiring thereof as a common wiring layer in a formation region of the logic circuit; In a region where the dynamic RAM is to be formed, the gate backing wiring is further provided above the wiring layer made of the metal wiring of the layer. Simultaneously forming the third-layer metal wiring as a common wiring layer in the formation region, and forming the dynamic RAM above the wiring layer composed of the gate backing wiring and the third-layer metal wiring. Forming a power supply line in a region, and forming a fourth metal wiring of the logic circuit as a common wiring layer in a region where the logic circuit is formed, at the same time. 18. A method of manufacturing a semiconductor device in which a stacked dynamic RAM and a logic circuit having a plurality of layers of metal wiring and utilizing the dynamic RAM are formed on the same semiconductor substrate. Simultaneously forming a bit line in the formation region of the dynamic RAM and a metal wiring of the first layer as a common wiring layer in the formation region of the logic circuit on the transistor; On the wiring layer made of the first metal wiring, the storage electrode connecting wiring of the capacitor is formed in the formation area of the dynamic RAM, and the second metal wiring is formed in the formation area of the logic circuit. Forming simultaneously as a layer, and forming a memory area in the formation area of the dynamic RAM and the logic circuit. Depositing an interlayer insulating film between interconnects and forming via holes between metal interconnects at predetermined positions in the interlayer insulating film; forming a barrier metal film on the interlayer insulating film and in the via holes; Burying a burying material made of a conductive material therein, and removing the burying material only in the via hole formed in the memory cell region of the dynamic RAM to expose the barrier metal film and form a storage electrode of a capacitor. Depositing a high dielectric material film on the storage electrode; forming a counter electrode of a capacitor on the high dielectric material film in the formation region of the dynamic RAM; Simultaneously forming a third layer of metal wiring as a common wiring layer; On the upper layer of the wiring layer composed of the third metal wiring, the gate backing wiring is formed as a common wiring layer in the formation region of the dynamic RAM, and the fourth metal wiring is formed as the common wiring layer in the formation region of the logic circuit. Forming a power supply line in a region where the dynamic RAM is formed, and a fifth line in a region where the logic circuit is formed in a layer further above a wiring layer including the gate backing wiring and the fourth layer metal wiring. Forming a metal wiring simultaneously as a common wiring layer.