CN113812124A - Predistortion parameter updating device and method and predistortion processing system - Google Patents
Predistortion parameter updating device and method and predistortion processing system Download PDFInfo
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Abstract
A predistortion parameter updating device (10) comprises at least two storage units (12), a control unit (13) and a processing unit (14), wherein each storage unit (12) is used for storing a sub lookup table, each sub lookup table stores a plurality of rows of predistortion parameters, all the sub lookup tables are used for forming a mother lookup table together, and each row of predistortion parameters in each sub lookup table corresponds to one row of predistortion parameters in the mother lookup table. The control unit (13) is used for controlling the processing unit (14) to read the predistortion parameters from the corresponding sub lookup tables in the storage unit (12) according to the line numbers of the predistortion parameters needing to be updated in the mother lookup tables. The processing unit (14) is used for calculating the read predistortion parameters to obtain updated predistortion parameters and write the original address. The processing unit (14) asynchronously performs read operation and write operation on the same sub lookup table, and effectively avoids read-write conflict in the update process of the predistortion parameters.
Description
The present application relates to the field of communications technologies, and in particular, to a predistortion parameter updating apparatus and method, and a predistortion processing system.
In a wireless communication system, a Power Amplifier (PA) is a key component of a transmitter system, and mainly functions to amplify a modulated frequency band signal to a transmission Power required by an antenna for transmission, so as to ensure that a receiver can obtain a strong signal. However, the power amplifier is the most important non-linear source in the transmitter, and on one hand, the non-linearity will distort the transmitted signal, resulting in the increase of the system error rate; on the other hand, the nonlinearity reduces the operating efficiency of the power amplifier, which tends to increase power consumption.
Digital Pre-Distortion (DPD) is one of the main methods to solve the nonlinearity of power amplifier. The digital predistortion technology achieves the purpose of counteracting nonlinearity brought by the power amplifier by compensating the input signal. When DPD is used for compensation, a Look-Up Table (Look-Up Table, abbreviated as LUT) in a memory needs to be read for predistortion parameters LUT to be updatedm(n-1) and then obtaining the updated predistortion parameter LUTm(n) and updating the LUTm(n) writing to the original address in the lookup table. Thus, according to the above steps, the predistortion parameters corresponding to the (m +1) th row in the lookup table are obtained, and the nth iteration of all LUTs is completed. However, in the process of updating the predistortion parameters, if the predistortion parameters being updated are read, read-write collision is caused, and an error occurs, so that the digital predistortion processing state is unstable.
Disclosure of Invention
The technical problem to be solved in the embodiments of the present application is to provide a predistortion parameter updating apparatus and method, and a predistortion processing system, which improve the stability of predistortion processing.
In order to achieve the above purpose, the embodiment of the present application adopts the following technical solutions:
in a first aspect, an embodiment of the present application provides a predistortion parameter updating apparatus, which includes at least two storage units, a control unit, and a processing unit. Each storage unit is used for storing a sub lookup table, each sub lookup table stores a plurality of rows of predistortion parameters, all the sub lookup tables are used for forming a mother lookup table together, and each row of predistortion parameters in each sub lookup table corresponds to one row of predistortion parameters and one row number in the mother lookup table. The control unit is used for outputting a read enabling signal and a read address signal according to the row number of the predistortion parameter needing to be updated in the mother lookup table, and the processing unit is used for reading the predistortion parameter from the sub lookup table where the predistortion parameter needing to be updated is located according to the read enabling signal and the read address signal. The processing unit is used for calculating the read predistortion parameters to obtain updated predistortion parameters, the control unit is used for outputting write enable signals and write address signals according to the row numbers of the read predistortion parameters in the parent lookup table, the processing unit writes the updated predistortion parameters into the original addresses of the read predistortion parameters in the corresponding child lookup tables according to the write enable signals and the write address signals, and the processing unit asynchronously carries out reading operation and writing operation on the same child lookup table.
In this embodiment, an existing lookup table is divided into a plurality of sub lookup tables, that is, the sub lookup tables stored in all the storage units are used to jointly form a master lookup table, each line of predistortion parameters in each sub lookup table corresponds to one line of predistortion parameters and one line number in the master lookup table, and the processing unit asynchronously reads and writes the same sub lookup table, so that read-write conflicts can be avoided when the sub lookup tables are read and written in the predistortion parameter updating process, and the stability and the processing speed of predistortion processing can be improved.
In an embodiment, the at least two storage units include a first storage unit and a second storage unit, the first storage unit is configured to store the first sub lookup table, the second storage unit is configured to store the second sub lookup table, the first sub lookup table stores a first predistortion parameter, the second sub lookup table stores a second predistortion parameter, and the first predistortion parameter is an LUT2j(n), the second predistortion parameter is LUT2j+1(n) the LUT2j(n) corresponding predistortion parameter LUTm(n) even line number predistortion parameters, the LUT2j+1(n) corresponding predistortion parameter LUTm(n) odd line number predistortion parameters, where M is the line number, and M is 0 … M-1; n is an iteration number, and N is 1 … N; 2j is an even row number, (2j +1) is an odd row number, j is 0,1,2 …, the processing unit is configured to read a first predistortion parameter from the first sub lookup table, and perform calculation according to the read first predistortion parameter to obtain a first updated predistortion parameter, and write the first updated predistortion parameter into an original address of the first sub lookup table where the read first predistortion parameter is located; the processing unit is used for reading a second predistortion parameter from a second sub lookup table where the predistortion parameter needing to be updated is located, calculating according to the read second predistortion parameter to obtain a second updated predistortion parameter, and writing the second updated predistortion parameter into an original address of the second sub lookup table where the read second predistortion parameter is located.
In this embodiment, the processing unit LUT is based on the predistortion parametersmAnd (n) the line numbers in the sub lookup tables alternately use the first sub lookup table and the second sub lookup table, so that the calculation resources are saved, and the calculation cost is reduced.
In an embodiment, the processing unit avoids a conflict between read and write operations in the same sub lookup table for an odd number of clock cycles between read and write operations of the predistortion parameters in the same row in the same sub lookup table.
In an embodiment, when the processing unit reads a row of first predistortion parameters from the first sub lookup table, the processing unit writes a row of second updated predistortion parameters into a second sub lookup table; and when the processing unit reads a row of second predistortion parameters from the second sub lookup table, writing the acquired row of first updated predistortion parameters into the first sub lookup table.
In this embodiment, the processing unit performs a write operation on the second sub lookup table while performing a read operation on the first sub lookup table, and the processing unit performs a read operation on the second sub lookup table while performing a write operation on the first sub lookup table, which is beneficial to improving the processing speed of updating the predistortion parameters.
In an embodiment, when the processing unit reads a row of first predistortion parameters from the first sub lookup table, it reads a row of second predistortion parameters from the first sub lookup table, and when the processing unit writes the acquired row of first updated predistortion parameters into the first sub lookup table, it writes the acquired row of second updated predistortion parameters into the second sub lookup table.
In this embodiment, the processing unit performs a read operation on the first sub lookup table and a read operation on the second sub lookup table at the same time, and the processing unit performs a write operation on the first sub lookup table and a write operation on the second sub lookup table at the same time, which is beneficial to improving the processing speed of updating the predistortion parameters.
In one embodiment, the memory unit is a single-port random access memory. The occupied space of the single-port random access memory is small, so that the occupied space of the predistortion parameter updating device is favorably reduced, the area of a special integrated circuit (namely a chip) is reduced, and the power consumption and the use cost of the predistortion parameter updating device are reduced.
In an embodiment, the memory cells are dual port random access memories, which can further improve the efficiency of reading and updating the predistortion parameters.
In an embodiment, one of the first storage unit and the second storage unit is a single-port random access memory, and the other of the first storage unit and the second storage unit is a dual-port random access memory, and since the single-port random access memory occupies a small space, the dual-port random access memory can improve the efficiency of reading and updating the predistortion parameters.
In a second aspect, an embodiment of the present application provides a predistortion system, which includes the predistortion parameter updating apparatus, the predistortion compensation apparatus and the power amplifier as described above, where the processing unit is configured to calculate the predistortion parameters to be updated to obtain updated predistortion parameters, and includes: the processing unit is used for processing the data according to LUTm(n)＝LUT m(n-1) + alpha.e (n) x (n-m) to obtain the updated predistortion parameter LUTm(n), where x (n) is the input signal, e (n) is the error between the input signal x (n) and the feedback signal y (n), the feedback signal y (n) is the sampling signal coupled back through the power amplifier, LUTm(n-1) the predistortion parameter that needs to be updated, said predistortion compensation means being for updating the predistortion parameter LUT using the updated predistortion parameter supplied from said predistortion parameter updating meansm(n) pre-distorting the input signal x (n) to obtain a compensated output signal, wherein the power amplifier is further configured to power-amplify the compensated output signal to achieve a required transmit power.
In a third aspect, an embodiment of the present application provides a predistortion parameter updating method, configured to update predistortion parameters stored in at least two sub lookup tables, where all the sub lookup tables are used to jointly form a mother lookup table, and each row of predistortion parameters in each sub lookup table corresponds to a row of predistortion parameters and a row number in the mother lookup table, where the method includes the following steps: outputting a read enabling signal and a read address signal according to the row number of the predistortion parameter to be updated in the mother lookup table; reading predistortion parameters from corresponding sub lookup tables according to the read enable signal and the read address signal; calculating according to the read predistortion parameters to obtain updated predistortion parameters; outputting a write enable signal and a write address signal according to the row number of the read predistortion parameter in the mother lookup table; and writing the updated predistortion parameters into the original addresses of the read predistortion parameters in the corresponding sub lookup tables according to the write enable signal and the write address signal, wherein the reading operation and the writing operation of the same sub lookup table are asynchronously carried out.
In an embodiment, the at least two sub lookup tables include a first sub lookup table and a second sub lookup table, the first sub lookup table stores a first predistortion parameter, the second sub lookup table stores a second predistortion parameter, and the first predistortion parameter is an LUT2j(n), the second predistortion parameter is LUT2j+1(n) the LUT2j(n) corresponding predistortion parameter LUTm(n) even line number predistortion parameters, the LUT2j+1(n) corresponding predistortion parameter LUTm(n) odd line number predistortion parameters, where M is the line number, and M is 0 … M-1; n is an iteration number, and N is 1 … N; 2j is an even row number, (2j +1) is an odd row number, j is 0,1,2 …, and reading the predistortion parameters from the sub lookup table where the predistortion parameters to be updated are located according to the read enable signal and the read address signal includes: reading a first predistortion parameter from a first sub lookup table where the predistortion parameter to be updated is located according to the read enable signal and the read address signal, reading a second predistortion parameter from a second sub lookup table where the predistortion parameter to be updated is located according to the read enable signal and the read address signal, and calculating according to the read predistortion parameter to obtain the updated predistortion parameter comprises: and calculating according to the read first predistortion parameter to obtain a first updated predistortion parameter, and calculating according to the read second predistortion parameter to obtain a second updated predistortion parameter. The controlling writing the updated predistortion parameters into the original addresses in the corresponding sub lookup tables comprises: writing the first updated predistortion parameter into the original address of the first sub lookup table where the first predistortion parameter is located, and writing the second updated predistortion parameter into the original address of the second sub lookup table where the second updated predistortion parameter is locatedAnd writing the original address of the second sub lookup table where the second predistortion parameter is located.
In an embodiment, the method further comprises: the read and write operations for the predistortion parameters of the same row in the same sub-lookup table are separated by an odd number of clock cycles.
In an embodiment, the method further comprises: when a row of first predistortion parameters is read from the first sub lookup table, writing the acquired row of second updated predistortion parameters into a second sub lookup table; and when a row of second predistortion parameters is read from the second sub lookup table, writing the acquired row of first updated predistortion parameters into the first sub lookup table.
In an embodiment, the method further includes reading a row of second predistortion parameters from the second sub lookup table when reading a row of first predistortion parameters from the first sub lookup table, and writing the obtained row of second updated predistortion parameters into the second sub lookup table when writing the obtained row of first updated predistortion parameters into the first sub lookup table.
In a fourth aspect, an apparatus is provided. The apparatus provided by the present application has means (means) for carrying out the above-described method, which means comprise corresponding means for performing the steps or functions described in the above-described method aspects. The steps or functions may be implemented by software, or by hardware (e.g., a circuit), or by a combination of hardware and software.
In one possible design, the apparatus includes one or more processors.
Optionally, the apparatus may also include one or more memories for coupling with the processor that hold the necessary program instructions and/or data for the apparatus. The one or more memories may be integral with the processor or separate from the processor. The present application is not limited.
The device can be a smart terminal or a wearable device and the like.
The device may also be a chip.
In another possible design, the apparatus includes a processor and a memory, where the memory is configured to store a set of program codes, and the processor is configured to call the program codes stored in the memory, so that the apparatus executes the method performed in the possible implementation manner of the third aspect.
In a fifth aspect, a computer-readable storage medium is provided for storing a computer program comprising instructions for performing the method of the possible implementation of the third aspect.
In a sixth aspect, there is provided a computer program product comprising: computer program code for causing a computer to perform the method of the third aspect described above and any possible embodiment of the third aspect when the computer program code runs on a computer.
Fig. 1 is a schematic diagram of an operating state of a predistortion processing system provided in the present application.
Fig. 2 is a schematic diagram of a parent lookup table formed by a first sub lookup table and a second sub lookup table according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of partial predistortion parameter updates of the first sub lookup table and the second sub lookup table according to an embodiment of the present disclosure.
FIG. 4a is a schematic diagram showing the comparison of the area of a conventional dual-port RAM with two single-port RAMs.
FIG. 4b is a schematic diagram of power consumption comparison between a conventional one-port RAM and a conventional one-port RAM.
Fig. 5 is a schematic diagram of partial predistortion parameter updates of the first sub lookup table and the second sub lookup table according to an embodiment of the present application.
Fig. 6 is a flowchart of a predistortion processing method according to an embodiment of the present application.
Fig. 7 is a schematic composition diagram of another predistortion parameter updating apparatus according to an embodiment of the present application.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating an operating state of a predistortion processing system 100 according to the present application. The predistortion processing system 100 comprises a predistortion parameter updating device 10, a predistortion compensation device 20 and a power amplifier 40. The predistortion parameter updating device 10 obtains predistortion parameters according to the input signal (x (n)) and the feedback signal (z (n)), and the predistortion compensation device 20 performs predistortion processing (i.e. compensation) on the input signal by using the predistortion parameters provided by the predistortion parameter updating device 10 to obtain a compensation output signal (y (n)), so as to achieve the purpose of counteracting the nonlinearity of the power amplifier. The power amplifier 40 is also used to power amplify the compensated output signal to achieve the desired transmit power.
The predistortion processing system 100 is applied to the field of communications, where the input signal refers to a signal input to the predistortion processing system 100 for predistortion processing, and the feedback signal is a sampling signal coupled back through the power amplifier 40. The predistortion processing is digital predistortion processing (DPD processing for short). It is understood that the predistortion processing system 100 may also be applied to other fields requiring predistortion processing of signals, such as artificial intelligence, financial prediction, natural weather modeling, etc. Such as the field of neural networks, and the like.
The predistortion processing system 100 further comprises a digital-to-analog converter 30 and an analog-to-digital converter 50, wherein the digital-to-analog converter 30 performs digital-to-analog conversion on the compensation output signal, and the analog-to-digital converter 50 performs digital-to-analog conversion on the feedback signal.
The predistortion parameter updating apparatus 10 includes at least two storage units 12, a control unit 13 and a processing unit 14.
Each storage unit 12 is configured to store a sub-lookup table, and each sub-lookup table stores a plurality of rows of predistortion parameters. Each sub lookup table stores a plurality of rows of predistortion parameters, all the sub lookup tables are used for jointly forming a mother lookup table, and each row of predistortion parameters in each sub lookup table corresponds to one row of predistortion parameters and one row number in the mother lookup table.
The control unit 13 is configured to output a read enable signal and a read address signal according to a row number of a predistortion parameter to be updated in the mother lookup table, and the processing unit 14 is configured to read the predistortion parameter from a corresponding child lookup table in the storage unit 12 according to the read enable signal and the read address signal.
The processing unit 14 is configured to calculate the read predistortion parameters to obtain updated predistortion parameters. The control unit is configured to output a write enable signal and a write address signal according to the row number of the read predistortion parameter in the master lookup table, and the processing unit 14 writes the updated predistortion parameter into the original address of the read predistortion parameter in the corresponding sub lookup table according to the write enable signal and the write address signal. The processing unit 14 asynchronously performs read and write operations to the same sub-lookup table.
Each storage unit 12 stores one sub lookup table, all the sub lookup tables are used for jointly forming one mother lookup table, and each row of predistortion parameters in each sub lookup table corresponds to one row of predistortion parameters in the mother lookup table, so that the method is beneficial to improving the update speed of the predistortion parameters and improving the stability of predistortion processing. The processing unit 14 performs the reading operation and the writing operation on the same sub lookup table asynchronously, so as to avoid the read-write collision when the sub lookup table is read and written in the predistortion parameter updating process, and improve the stability of the predistortion processing.
In this embodiment, the processing unit 14 performs the read operation and the write operation on the same sub lookup table in different clock cycles. In one clock cycle, the processing unit 14 reads a row of predistortion parameters in one sub lookup table, or the processing unit 14 writes corresponding updated predistortion parameters obtained by the read row of predistortion parameters in the sub lookup table into the same sub lookup table. I.e. for one sub-lookup table, processing unit 14 only performs read operations or processing unit 14 only performs write operations in one clock cycle.
The compensated output signal y (n) is expressed by the following mathematical formula:
wherein, wm,qFor predistortion coefficients, LUTsm(| x (n-m) |) is a predistortion parameter, and m is a LUTm(| x (n-m) |) is the line number in, and n is the iteration number.
According to LMSE algorithm, order
LUT m(|x(n-m)|)＝LUT m(n) (3)
LUTm(n)＝LUT m(n-1)+α·e(n)·x(n-m),m＝0…M-1 (4)
Wherein e (n) represents the error between the input signal x (n) and the feedback signal z (n), and α is an adjustable parameter.
According to LUTmThe row number m of (n) decomposes formula (3) into:
LUT 2j(n)＝LUT 2j(n-1)+α·e(n)·x(n-m)，j＝0,1,2… (5)
LUT 2j+1(n)＝LUT 2j+1(n-1)+α·e(n)·x(n-m)，j＝0,1,2… (6)
in other words, m may be 2j or (2j +1), i.e. the line number m is divided into an even line number 2j and an odd line number (2j +1), and the predistortion parameter LUT is calculatedm(n) decomposition into first predistortion parameters LUT2j(n), and a second predistortion parameter LUT2j+1(n) of (a). In other words, LUT2j(n) corresponding predistortion parameter LUTmEven line number predistortion parameters in (n), LUT2j+1(n) corresponding predistortion parameter LUTmAnd (n) the odd-numbered line number predistortion parameters.
The storage unit 12 includes a first storage unit 122 and a second storage unit 124, the first storage unit 122 is used for storing a first sub lookup table, the second storage unit 124 is used for storing a second sub lookup table, and the first sub lookup table stores a first predistortion parameter LUT with even row numbers2j(n) the second sub-lookup table stores the odd-numbered line predistortion parameters LUT2j+1(n) of (a). j is the row number of the first sub lookup table and the second sub lookup table. The first sub lookup table and the second sub lookup table together form a mother lookup table (as shown in fig. 2), m is the row number of the mother lookup table, and the predistortion parameters in the mother lookup table are expressed as LUTm(n) of (a). Each row of predistortion parameters in each sub-lookup table corresponds to a row of predistortion parameters in the mother lookup table, for example, when j is 1, i.e. the first predistortion parameter LUT of the 2 nd row in the first sub-lookup table2(n) corresponding to the predistortion parameter LUT with line number 3 in the mother lookup table2(n)。
The processing unit 14 is configured to obtain a first predistortion parameter as the LUT2j(n) calculating to obtain the first updated predistortion parameter as LUT2j(n +1), and the first updated predistortion parameter LUT2j(n +1) write first predistortion parameter LUT2j(n) the original address of the first sub-lookup table.
The processing unit 14 is configured to obtain the second predistortion parameter as the LUT2j+1(n) calculating to obtain a second updated predistortion parameter LUT2j+1(n +1), and second updating predistortion parameter LUT2j+1(n +1) writing the first predistortion parameter LUT2j+1(n) the original address of the second sub-lookup table. And in one iteration, writing the first updated predistortion parameter of the first sub lookup table as the first predistortion parameter to be replaced in the next iteration, and circulating. And writing a second updated predistortion parameter of the second sub lookup table in one iteration as a second predistortion parameter to be replaced in the next iteration.
Wherein, for the same sub lookup table, the read operation and the write operation of the processing unit 14 are performed at different clock cycles respectively.
And the reading and the writing of the first sub lookup table are asynchronously carried out, and the reading and the writing of the second sub lookup table are asynchronously carried out, so that the reading and writing conflict between the first sub lookup table and the second sub lookup table is avoided, and the stability of the predistortion processing is improved.
When the first storage unit 122 in which the first sub lookup table is located provides the predistortion parameter to the processing unit 14, the processing unit 14 updates the second predistortion parameter in the second sub lookup table. After the update of the predistortion parameters stored in the second sub lookup table of the second storage unit 124 is completed, the second storage unit 124 provides the second predistortion parameters stored in the second sub lookup table to the processing unit 14. While the processing unit 14 reads the second predistortion parameter stored in the second sub lookup table, the processing unit 14 updates the first predistortion parameter stored in the first sub lookup table. After the update of the first predistortion parameters stored in the first sub-lookup table of the first storage unit 122 is completed, the first storage unit 122 provides the first predistortion parameters stored in the first sub-lookup table to the processing unit 14, and so on.
Further, the processing unit 14 includes a first sub-processing unit 141, a second sub-processing unit 142, a third sub-processing unit 143, a fourth sub-processing unit 144, a fifth sub-processing unit 145, and a sixth sub-processing unit 146.
The first sub-processing unit 141 is configured to obtain an error e (n) between the input signal x (n) and the feedback signal z (n).
The second sub-processing unit 142 is configured to obtain the current iteration number output by the control unit 13, the line number of the predistortion parameter to be updated, and select x (n-M) from x (n), x (n-1) … x (n-M-1).
The third sub-processing unit 143 is configured to obtain the product of e (n) and x (n-m) according to the selected x (n-m).
The fourth sub-processing unit 144 is configured to obtain the product α · e (n) · x (n-m).
The fifth sub-processing unit 145 is used for reading the LUT according to the read enable signal and the read address signalm(n-1) and obtaining and updating predistortion parameter LUT according to equation (4)m(n) of (a). The fifth sub-processing unit 145 is used for updating the predistortion parameter LUT according to the write enable signal and the write address signalmAnd (n) writing the original address in the corresponding sub lookup table. Wherein, when m is 2j, the fifth sub-processing unit 145 is configured to read the first predistortion parameter LUT2j(n-1) and obtaining a first update prediction according to equation (5)Distortion parameter LUT2j(n), and updating the first updated predistortion parameter LUT2j(n) writing the first predistortion parameter LUT2jThe original address of (n-1). When m is (2j +1), the fifth sub-processing unit 145 is configured to read the second predistortion parameter LUT2j+1(n-1) and obtaining a second updated predistortion parameter LUT according to equation (6)2j+1(n), and updating the second updated predistortion parameter LUT2j+1(n) write LUT2j+1The original address of (n-1).
The sixth sub-processing unit 146 is configured to delay the processing of the predistortion parameters in the sub-lookup table by the fifth sub-processing unit 145. For example, at the 0 th clock cycle, the fifth sub-processing unit 145 reads the LUT in the first sub-lookup table0(n); in the 1 st clock cycle, the fifth sub-processing unit 145 does not operate, and in the 2 nd clock cycle, the fifth sub-processing unit 145 reads the LUT in the first sub-lookup table2(n), i.e. the sixth sub-processing unit 146 delays the fifth sub-processing unit 145 reading the LUT2(n)。
The processing unit 14 further comprises a seventh processing unit, for example a delay unit. The processing unit 14 may comprise an eighth processing unit for performing down-conversion, filtering, image removal, amplitude and phase adjustment, and the like on the feedback signal.
The predistortion parameter updating apparatus 10 further comprises a delay alignment unit 16. The delay alignment unit 16 is configured to perform delay processing on the input signal (x (n)), so as to ensure that the input signal (x (n)) and the feedback signal (z (n)) are aligned in time, so that the error signal (e (n)) is calculated correctly.
To read out the predistortion parameter LUT from the first sub lookup table2j(n-1) is a brief explanation. The control unit 30 updates the predistortion parameter LUT according to the need2j(n-1) the row number 2j in the mother lookup table outputs a read enable signal and a read address signal, and the processing unit 14 reads the first predistortion parameter LUT to be updated stored in the first storage unit 122 according to the read enable signal and the read address signal2j(n-1), the processing unit 14 is adapted to apply a first pre-distortion parameter based on the read first pre-distortion parameterNumber LUT2j(n-1), the input signal (x (n)) and the feedback signal z (n) are processed to obtain the corresponding first updated predistortion parameter LUT2j(n) of (a). The control unit 30 reads the predistortion parameter LUT2j(n-1) outputting the write enable signal and the write address signal at the row number 2j in the mother lookup table. The processing unit 14 updates the acquired first updated predistortion parameter LUT according to the write enable signal and the write address signal2j(n) writing the first predistortion parameter LUT2j(n-1) updating the predistortion parameters corresponding to the line number 2j in the mother lookup table at the original address in the first child lookup table. Predistortion compensation device 20 extracts predistortion parameter LUT in predistortion parameter updating device 102j(n) performing predistortion processing on the input signal x (n) to obtain a compensated input signal y (n). The digital-to-analog converter 30 performs digital-to-analog conversion on the compensation output signal y (n), and the power amplifier 40 amplifies the digital-to-analog converted compensation output signal y (n) to achieve the required transmission power.
For example, please refer to fig. 3, fig. 3 is a schematic diagram illustrating an alternative operation of the first sub lookup table and the second sub lookup table according to an embodiment of the present application. The first storage unit 122 is a single-port random access memory, and is denoted as SP-RAM 0; the second storage unit 124 is also a single-port random access memory denoted as SP-RAM 1; clock is a clock cycle. The single-port random access memory generally has only one set of data lines and address lines, and cannot read and write at the same time.
In the 0 th clock cycle, the processing unit 14 reads the first predistortion parameter LUT stored in the first sub-lookup table0(n), the processing unit 14 does not perform read and write operations on the second sub-lookup table.
In the 1 st clock cycle, the processing unit 14 reads the second predistortion parameter LUT stored in the second sub lookup table1(n), the processing unit 14 does not perform read and write operations on the first sub-lookup table.
In the 2 nd clock cycle, the processing unit 14 reads the first predistortion parameter LUT stored in the first sub-lookup table2(n) processing unit 14 for the aboveThe second sub-lookup table does not perform read and write operations.
In the 3 rd clock cycle, the processing unit 14 will read the first predistortion parameter LUT0(n) the first updated predistortion parameter LUT0(n +1), writing the first predistortion parameter LUT0(n) realizing the LUT (look-up table) of the first predistortion parameters stored in the first sub lookup table at the original address in the first sub lookup table0(n) updating to LUT0(n +1), reading the second predistortion parameter LUT stored in the second sub lookup table3(n)。
In the 4 th clock cycle, the processing unit 14 reads the first predistortion parameter LUT stored in the first sub-lookup table4(n), the processing unit 14 updates the acquired second updated predistortion parameter LUT1(n +1) write second predistortion parameter LUT1(n) at the original address … … in the second sub-lookup table, in the ith clock cycle, the processing unit 14 reads the first predistortion parameter LUT stored in the first sub-lookup table2j(n), the processing unit 14 updates the acquired second updated predistortion parameter LUT2j-3(n +1) write second predistortion parameter LUT2j-3(n) an original address in the second sub-lookup table.
In this way, the processing unit 14 obtains the corresponding updated predistortion parameter according to the predistortion parameter read from each sub lookup table, and writes the obtained updated predistortion parameter into the original address in the corresponding sub lookup table.
In some embodiments, the read operation alternates with the write operation in the same sub-lookup table in a clock cycle order.
In this embodiment, the interval between the reading and writing operations of the predistortion parameters in the same row in the same sub lookup table is 3 clock cycles, so as to avoid read-write collision. It will be appreciated that the same sub-lookup table corresponds to an odd number of clock cycles between read and write operations of the predistortion parameters, e.g., 1,5,7 …, etc.
In this embodiment, since the first storage unit 122 and the second storage unit 124 are both single-port random access memories, the chip area is reduced without increasing the size of the memories, the power consumption is reduced accordingly, and the chip cost and the use cost are both reduced.
It is understood that the memory unit 12 is not limited to a random access memory, and the memory unit 12 may be other types of memories, such as a nonvolatile memory type, e.g., a ferroelectric memory, a phase change memory, a magnetic memory, a resistive memory, and the like.
Referring to fig. 4a and 4b, fig. 4a is a schematic diagram illustrating an area comparison between two single-port ram and a conventional dual-port ram, and fig. 4b is a schematic diagram illustrating a power consumption comparison between two single-port ram and a conventional dual-port ram. Compared with the existing dual-port access memory capable of reading and writing simultaneously, the memory occupation area can be effectively reduced by 40% by adopting two single-port random access memories; under the 491MHz clock, the total power consumption of the memory used by the predistortion parameter updating device 10 is reduced by 14%, so that the chip cost and the use cost in the Application of an Application Specific Integrated Circuit (ASIC) are favorably reduced.
In one embodiment, the first storage unit 122 is a dual port random access memory, and the second storage unit 124 is a dual port random access memory. For example, referring to fig. 5, fig. 5 is a schematic diagram of partial predistortion parameter update of the first sub lookup table and the second sub lookup table according to another embodiment of the present application. The processing unit 14 reads and writes the first sub-lookup table stored in the first storage unit 122, and reads and writes the second sub-lookup table stored in the second storage unit 124, similar to fig. 3, and will not be described herein again.
In one embodiment, one of the first storage unit 122 and the second storage unit 124 is a single-port random access memory, and the other is a dual-port random access memory. The dual port random access memory generally has two sets of data lines and address lines, which can be read and written simultaneously.
It will be appreciated that the number of sub-lookup tables is not limitedThree or more sub lookup tables, i.e. LUTs, may also be providedm(n) dividing into a plurality of portions corresponding to the number of said sub-look-up tables, each sub-look-up table holding a LUTm(n) a predistortion parameter for a portion of the number of lines.
Referring to fig. 6, fig. 6 is a flowchart illustrating a predistortion parameter updating method according to an embodiment of the present disclosure.
A predistortion parameter updating method for updating predistortion parameters stored in at least two sub lookup tables, all of which are used to jointly form a parent lookup table, each row of predistortion parameters in each sub lookup table corresponding to a row of predistortion parameters in the parent lookup table, the method comprising the steps of:
In an embodiment, the at least two sub lookup tables include a first sub lookup table and a second sub lookup table, the first sub lookup table stores a first predistortion parameter, the second sub lookup table stores a second predistortion parameter, and the first predistortion parameter is an LUT2j(n), the second predistortion parameter is LUT2j+1(n) the LUT2j(n) corresponding predistortion parameter LUTm(n) even-numbered predistortion parameters, andthe LUT2j+1(n) corresponding predistortion parameter LUTm(n) odd line number predistortion parameters, where M is the line number, and M is 0 … M-1; n is an iteration number, and N is 1 … N; 2j is an even row number, (2j +1) is an odd row number, j is 0,1,2 ….
The reading of the predistortion parameters from the sub lookup table where the predistortion parameters to be updated are located according to the read enable signal and the read address signal includes: reading a first predistortion parameter from a first sub lookup table where the predistortion parameter needing to be updated is located according to the read enable signal and the read address signal, and reading a second predistortion parameter from a second sub lookup table where the predistortion parameter needing to be updated is located according to the read enable signal and the read address signal.
The obtaining updated predistortion parameters by calculating according to the read predistortion parameters comprises: and calculating according to the read first predistortion parameter to obtain a first updated predistortion parameter, and calculating according to the read second predistortion parameter to obtain a second updated predistortion parameter.
The controlling writing the updated predistortion parameters into the original addresses in the corresponding sub lookup tables comprises: and writing the first updated predistortion parameter into the original address of a first sub lookup table where the first predistortion parameter is located, and writing the second updated predistortion parameter into the original address of a second sub lookup table where the second predistortion parameter is located.
In an embodiment, the method further comprises: the read and write operations for the predistortion parameters of the same row in the same sub-lookup table are separated by an odd number of clock cycles.
In an embodiment, the method further comprises: when a row of first predistortion parameters is read from the first sub lookup table, writing the acquired row of second updated predistortion parameters into a second sub lookup table; and when a row of second predistortion parameters is read from the second sub lookup table, writing the acquired row of first updated predistortion parameters into the first sub lookup table.
In an embodiment, the method further comprises; and when the first predistortion parameters of one row are read from the first sub lookup table, the second predistortion parameters of one row are read from the second sub lookup table, and when the acquired first updated predistortion parameters of one row are written into the first sub lookup table, the acquired second updated predistortion parameters of one row are written into the second sub lookup table.
Fig. 7 is a schematic diagram illustrating another predistortion parameter updating apparatus according to an embodiment of the present application. As shown in fig. 7, the predistortion parameter updating apparatus 200 may include a processor 210 and a memory 220. The memory 220 is used for storing instructions, and the processor 210 is used for executing the instructions stored in the memory 220 to implement the steps performed by the predistortion parameter updating apparatus in the method corresponding to fig. 1.
The processor 210 is configured to execute the instructions stored in the memory 220 to perform the steps performed by the predistortion parameter updating apparatus in the above-described method. The memory 220 may be integrated in the processor 210 or may be provided separately from the processor 210.
As an implementation, the processor 210 may be considered to be implemented by a dedicated processing chip, a processing circuit, a processor, or a general-purpose chip.
As another implementation manner, a manner of using a general-purpose computer to implement the terminal provided in the embodiment of the present application may be considered.
For the concepts, explanations, details and other steps related to the technical solutions provided in the embodiments of the present application related to the predistortion parameter updating apparatus, reference is made to the foregoing methods or descriptions related to these contents in other embodiments, which are not described herein again.
Those skilled in the art will appreciate that only one memory and processor are shown in fig. 7 for ease of illustration. In an actual controller, there may be multiple processors and memories. The memory may also be referred to as a storage medium or a storage device, and the like, which is not limited in this application.
It should be understood that, in the embodiment of the present Application, the processor may be a Central Processing Unit (CPU), and the processor may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components, and the like.
The memory may include both read-only memory and random access memory, and provides instructions and data to the processor. The portion of memory may also include non-volatile random access memory.
In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The steps of a method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software modules in a processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor. To avoid repetition, it is not described in detail here.
In the embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.
Those of ordinary skill in the art will appreciate that the various Illustrative Logical Blocks (ILBs) and steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, digital subscriber line) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk), among others.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (13)
- A predistortion parameter updating device is characterized in that the device comprises at least two storage units, a control unit and a processing unit,each storage unit is used for storing a sub lookup table, each sub lookup table stores a plurality of rows of predistortion parameters, all the sub lookup tables are used for jointly forming a mother lookup table, each row of predistortion parameters in each sub lookup table corresponds to one row of predistortion parameters in the mother lookup table,the control unit is used for outputting a read enabling signal and a read address signal according to the row number of the predistortion parameter needing to be updated in the mother lookup table, the processing unit is used for reading the predistortion parameter from the corresponding sub lookup table in the storage unit according to the read enabling signal and the read address signal,the processing unit is used for calculating the read predistortion parameters to obtain updated predistortion parameters, the control unit is used for outputting write enable signals and write address signals according to the row numbers of the read predistortion parameters in the parent lookup table, the processing unit writes the updated predistortion parameters into the original addresses of the read predistortion parameters in the corresponding child lookup tables according to the write enable signals and the write address signals,the processing unit asynchronously performs read operations and write operations on the same sub lookup table.
- The predistortion parameter updating apparatus of claim 1,the at least two storage units comprise a first storage unit and a second storage unit, the first storage unit is used for storing the first sub lookup table, and the second storage unit is used for storing the second sub lookup tableThe table is found, the first sub lookup table stores a first predistortion parameter, the second sub lookup table stores a second predistortion parameter, and the first predistortion parameter is an LUT2j(n), the second predistortion parameter is LUT2j+1(n) the LUT2j(n) corresponding predistortion parameter LUTm(n) even line number predistortion parameters, the LUT2j+1(n) corresponding predistortion parameter LUTm(n) odd line number predistortion parameters, where M is the line number, and M is 0 … M-1; n is an iteration number, and N is 1 … N; 2j is an even row number, (2j +1) is an odd row number, j is 0,1,2 …,the processing unit is used for reading a first predistortion parameter from the first sub lookup table, calculating according to the read first predistortion parameter to obtain a first updated predistortion parameter, and writing the first updated predistortion parameter into an original address of the first sub lookup table where the read first predistortion parameter is located;the processing unit is used for reading a second predistortion parameter from a second sub lookup table where the predistortion parameter needing to be updated is located, calculating according to the read second predistortion parameter to obtain a second updated predistortion parameter, and writing the second updated predistortion parameter into an original address of the second sub lookup table where the read second predistortion parameter is located.
- The predistortion parameter updating apparatus as claimed in claim 2, wherein the interval between the read and write operations of the predistortion parameters of the same row in the same sub lookup table by the processing unit is odd number of clock cycles.
- The predistortion parameter updating apparatus of claim 2,when the processing unit reads a row of first predistortion parameters from the first sub lookup table, writing the acquired row of second updated predistortion parameters into the second sub lookup table;and when the processing unit reads a row of second predistortion parameters from the first sub lookup table, writing the acquired row of first updated predistortion parameters into the first sub lookup table.
- The predistortion parameter updating apparatus of claim 2,the processing unit reads a row of second predistortion parameters from the first sub-lookup table when reading a row of first predistortion parameters from the first sub-lookup table,and when the processing unit writes the acquired row of first updated predistortion parameters into the first sub lookup table, the processing unit writes the acquired row of second updated predistortion parameters into the second sub lookup table.
- The predistortion parameter updating apparatus as claimed in claim 1, wherein the storage unit is a single port random access memory.
- A predistortion system, characterized in that the predistortion system comprises a predistortion parameter updating apparatus, a predistortion compensation apparatus and a power amplifier according to any one of claims 1 to 6,the processing unit is used for calculating the predistortion parameters to be updated to obtain the updated predistortion parameters, and comprises: the processing unit is used for processing the data according to LUTm(n)＝LUT m(n-1) + alpha.e (n) x (n-m) to obtain the updated predistortion parameter LUTm(n), where x (n) is the input signal, e (n) is the error between the input signal x (n) and the feedback signal y (n), the feedback signal y (n) is the sampling signal coupled back through the power amplifier, LUTm(n-1) the predistortion parameters that need to be updated,the predistortion compensation device is used for using the updated predistortion parameter LUT provided by the predistortion parameter updating devicem(n) pre-distorting said input signal x (n) to obtain a compensated output signal,the power amplifier is also used for carrying out power amplification on the compensation output signal so as to achieve required transmission power.
- A predistortion parameter updating method for updating predistortion parameters stored in at least two sub lookup tables, wherein all the sub lookup tables are used to jointly form a mother lookup table, and each row of predistortion parameters in each sub lookup table corresponds to a row of predistortion parameters in the mother lookup table, the method comprising the steps of:outputting a read enabling signal and a read address signal according to the row number of the predistortion parameter to be updated in the mother lookup table;reading predistortion parameters from corresponding sub lookup tables according to the read enable signal and the read address signal;calculating according to the read predistortion parameters to obtain updated predistortion parameters;outputting a write enable signal and a write address signal according to the row number of the read predistortion parameter in the mother lookup table;writing the updated predistortion parameters into the original addresses of the read predistortion parameters in the corresponding sub lookup tables according to the write enable signal and the write address signal,wherein the read operation and the write operation for the same sub lookup table are performed asynchronously.
- The predistortion parameter updating method of claim 8, wherein the at least two sub lookup tables comprise a first sub lookup table and a second sub lookup table, the first sub lookup table stores a first predistortion parameter, the second sub lookup table stores a second predistortion parameter, the first predistortion parameter is a LUT2j(n), the second predistortion parameter is LUT2j+1(n) the LUT2j(n) corresponding predistortion parameter LUTm(n) even line number predistortion parameters, the LUT2j+1(n) corresponding predistortion parameter LUTm(n) odd line number predistortion parameters, where M is the line number, and M is 0 … M-1; n is iteration number, n is 1 …N; 2j is an even row number, (2j +1) is an odd row number, j is 0,1,2 …,the reading of the predistortion parameters from the sub lookup table where the predistortion parameters to be updated are located according to the read enable signal and the read address signal includes: reading a first predistortion parameter from a first sub lookup table where the predistortion parameter to be updated is located according to the read enable signal and the read address signal, reading a second predistortion parameter from a second sub lookup table where the predistortion parameter to be updated is located according to the read enable signal and the read address signal,the obtaining updated predistortion parameters by calculating according to the read predistortion parameters comprises: calculating according to the read first predistortion parameter to obtain a first updated predistortion parameter, and calculating according to the read second predistortion parameter to obtain a second updated predistortion parameter;the writing of the updated predistortion parameters into the original addresses in the corresponding sub lookup tables comprises: and writing the first updated predistortion parameter into the original address of a first sub lookup table where the first predistortion parameter is located, and writing the second updated predistortion parameter into the original address of a second sub lookup table where the second predistortion parameter is located.
- The predistortion parameter updating method as claimed in claim 9, wherein the method further comprises: the read and write operations for the predistortion parameters of the same row in the same sub-lookup table are separated by an odd number of clock cycles.
- The predistortion parameter updating method as claimed in claim 9, wherein the method further comprises:when a row of first predistortion parameters is read from the first sub lookup table, writing the acquired row of second updated predistortion parameters into a second sub lookup table;and when a row of second predistortion parameters is read from the second sub lookup table, writing the acquired row of first updated predistortion parameters into the first sub lookup table.
- The predistortion parameter updating method as claimed in claim 9, wherein the method further comprises;reading a row of second predistortion parameters from the second sub-lookup table while reading a row of first predistortion parameters from the first sub-lookup table,and writing the acquired first updated predistortion parameters of one row into the first sub lookup table, and writing the acquired second updated predistortion parameters of one row into the second sub lookup table.
- A predistortion parameter updating apparatus comprising a processor and a memory, wherein the memory is configured to store a set of program codes, and the processor is configured to call the program codes stored in the memory and execute the steps according to any of claims 8-12.
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