CN113793881B - Photoelectric synapse device array, preparation method thereof and image processing equipment - Google Patents

Photoelectric synapse device array, preparation method thereof and image processing equipment Download PDF

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CN113793881B
CN113793881B CN202111089808.8A CN202111089808A CN113793881B CN 113793881 B CN113793881 B CN 113793881B CN 202111089808 A CN202111089808 A CN 202111089808A CN 113793881 B CN113793881 B CN 113793881B
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程传同
张恒杰
黄北举
张欢
陈润
黄宇龙
陈弘达
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Abstract

The present disclosure provides a photoelectric synapse device array, a method for manufacturing the same, and an image processing apparatus, the photoelectric synapse device array including: a bottom electrode; the P-type semiconductor layer, the N-type semiconductor layer, the light absorption layer and the transparent top electrode are sequentially stacked on the bottom electrode; wherein the top electrode and the bottom electrode maintain a vertical crossing structure, and each crossing point forms a single photoelectric synapse device unit.

Description

Photoelectric synapse device array, preparation method thereof and image processing equipment
Technical Field
The disclosure relates to the field of photoelectric synapse devices, in particular to a photoelectric synapse device array, a preparation method thereof and image processing equipment.
Background
The existing imaging technology is based on a three-step task processing process of image imaging, data storage and information processing. However, the three steps of image formation, data storage and information processing are transmitted through the circuit bus for many times in the conventional apparatus, which causes many problems in terms of efficiency and power consumption in the image processing process.
With the research of artificial synapses, attempts have been made in the related art to combine memristors and optical synapses for image processing to improve the efficiency of the image processing process and to reduce power consumption.
At present, a related technology adopts memristors and photoelectric synapses at two ends to solve the problems of efficiency and power consumption in the process of graphic processing, but the most important problem of devices at two ends is the crosstalk problem of leakage current in a circuit. In order to solve the problem of crosstalk of leakage current in a circuit, another related technology adopts a cross array of memristors or photoelectric synapses, in which each synapse device is connected in series with a transistor or a diode or a gate tube, so that although the problem of crosstalk of leakage current in the array is solved, the complexity of the process is increased by connecting redundant devices in series.
Disclosure of Invention
In view of the above, the present disclosure provides an optoelectronic synapse device array, a method for fabricating the same, and an image processing apparatus, so as to at least partially solve the above-mentioned technical problems.
According to one aspect of the present disclosure, there is provided an array of optoelectronic synapse devices comprising:
a bottom electrode;
the P-type semiconductor layer, the N-type semiconductor layer, the light absorption layer and the transparent top electrode are sequentially stacked on the bottom electrode;
wherein the top electrode and the bottom electrode maintain a vertical crossing structure, and each crossing point forms an individual photoelectric synapse device unit.
According to an embodiment of the present disclosure, the bottom electrode employs an inert metal having a work function greater than 5 eV.
According to the embodiment of the disclosure, the P-type semiconductor layer adopts a P-type semiconductor thin film material with defects; and/or the N-type semiconductor layer adopts a defected N-type semiconductor thin film material.
According to the embodiment of the disclosure, the material of the P-type semiconductor layer comprises NiO y 、IrO 2 、Co 2 O 3 、Rh 2 O 3 Or MnO 2 (ii) a And/or the material of the N-type semiconductor layer includes WO 3-z 、VO 2 、MoO 3 、Nb 2 O 5 Or TiO 2 Wherein y is more than or equal to 1,3 and z is more than or equal to 0.
According to the embodiment of the present disclosure, the light absorbing layer employs a photosensitive material having semiconductor process compatibility.
According to an embodiment of the present disclosure, the material of the light absorbing layer includes Si, siC, gaN, or ITO x Wherein x > 1.
According to an embodiment of the present disclosure, the material of the top electrode comprises ITO or FTO.
According to an embodiment of the present disclosure, the array of optoelectronic synapse devices further comprises: the substrate, the bottom electrode is located the surface of substrate.
According to another aspect of the present disclosure, there is provided a method for manufacturing an array of optoelectronic synapse devices, comprising:
preparing a bottom electrode on a substrate;
the bottom electrode is placed in an oxygen-deficient state to deposit a P-type semiconductor layer;
forming an N-type semiconductor layer on the P-type semiconductor layer;
forming a light absorption layer on the N-type semiconductor layer;
forming a transparent top electrode on the surface of the light absorption layer to obtain a photoelectric synapse device array; wherein the top electrode and the bottom electrode maintain a vertical crossing structure, and each crossing point forms a single photoelectric synapse device unit.
According to yet another aspect of the present disclosure, there is provided an image processing apparatus comprising an array of optoelectronic synapse devices as described above.
The technical scheme of the disclosure has at least the following advantages:
(1) The photoelectric synapse device has self-rectification characteristic by stacking a plurality of barrier regions through a bottom electrode, an N-type semiconductor layer and a P-type semiconductor layer, and the unidirectional conducting device can prevent reverse current from flowing in an array, so that crosstalk caused by leakage current is inhibited.
(2) The present disclosure provides an optically tunable feature for the optoelectronic synapse device elements by adding a light absorbing layer. Based on the photosensitive characteristic of the light absorption layer, conductive ions in the photoelectric synapse device unit can be increased, and therefore the memory device with adjustable electric conduction states is achieved. In addition, the disclosure may enhance the conductance of the illuminated photosynaptic device cells by applying an optical signal to the array of photosynaptic devices, and may erase upon application of a reverse voltage, thereby enabling synaptically excitable and suppressible. The photoelectric synapse device unit can be accurately controlled through the optical signal and the electric signal, and the stability and the repeatability of the photoelectric synapse device unit are effectively improved.
(3) The photoelectric synapse device array based on the stacking structure is simple in manufacturing process, and the unit size of the photoelectric synapse device can be designed to be smaller, so that integration is facilitated.
(4) The photoelectric synapse device array can realize all functions of optical imaging, information storage, information processing and electrical erasing, and the array formed by the photoelectric synapse device units can realize sensing, storing and calculating integration, so that the efficiency and power consumption of image detection and processing are greatly improved, the operational capability of a chip is further enhanced, a feasible scheme is provided for the design of the photoelectric synapse chip, and a new thought is provided for the visual neural network device integrating sensing, storing and calculating.
Drawings
FIG. 1A is a front view of an optoelectronic synapse device array structure in accordance with a preferred embodiment of the disclosure;
FIG. 1B is a top view of an optoelectronic synapse device array structure in accordance with a preferred embodiment of the present disclosure;
FIG. 2 is a flow chart of a method for fabricating an array of optoelectronic synapse devices in accordance with a preferred embodiment of the present disclosure;
FIG. 3 is a graph of expected results of current-voltage characteristics of positive and negative voltage sweeps of a photosynaptic device cell in both illuminated and non-illuminated conditions, in accordance with a preferred embodiment of the present disclosure;
FIG. 4 is an expected result of the current-time variation process (memory characteristic) of the optoelectronic synapse device element after illumination by a single optical signal in a preferred embodiment of the disclosure;
FIG. 5 is an expected result of an optoelectronic synapse device cell being erased with a negative-going voltage after being written with a plurality of optical signals in a preferred embodiment of the disclosure;
FIG. 6A is a schematic diagram illustrating the operation of the optoelectronic synapse device elements in an optoelectronic synapse device array in accordance with a preferred embodiment of the present disclosure;
FIG. 6B is a schematic diagram illustrating the energy band mechanism of the optoelectronic synapse device unit in the optoelectronic synapse device array under illumination according to a preferred embodiment of the present disclosure;
FIG. 7A is a schematic diagram illustrating the operation of the synapse device elements in an array under reverse voltage;
FIG. 7B is a schematic diagram illustrating the band mechanism of the optoelectronic synapse device unit in the array under reverse voltage;
FIG. 8 is a schematic diagram of a cross-talk blocking process between the optoelectronic synapse device units in the optoelectronic synapse device array in accordance with a preferred embodiment of the present disclosure;
FIG. 9 is a schematic diagram of an array of optoelectronic synapse devices in optical imaging, information storage and information processing processes in accordance with a preferred embodiment of the present disclosure.
Description of reference numerals:
1: a substrate; 2: a bottom electrode; 3: a P-type semiconductor layer;
4: an N-type semiconductor layer; 5: a light absorbing layer; 6: a top electrode;
(a, a), (b, b), (a, b): a photoelectric synapse device unit representing the ith row and the jth (i, j = a or b) column;
100: an array of optoelectronic synapse devices; 200: a lens group; a: and (4) an image.
Detailed Description
For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the disclosure and are not intended to limit the disclosure. Further, the technical features described in the embodiments of the present disclosure described below may be combined with each other as long as they do not conflict with each other.
It should be noted that in the drawings or description, the same reference numerals are used for similar or identical parts. Implementations not shown or described in the drawings are of a form known to those of ordinary skill in the art. Additionally, while exemplifications of parameters including particular values may be provided herein, it is to be understood that the parameters need not be exactly equal to the respective values, but may be approximated to the respective values within acceptable error margins or design constraints. In addition, directional terms, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", and the like, referred to in the following embodiments are only directions referring to the drawings. Accordingly, the directional terminology used is intended to be in the nature of words of description rather than of limitation.
As described in the background, in the related art, in order to solve the problem of leakage current crosstalk of the circuit, each synapse device is connected in series with a transistor or a diode or a gate tube, so that although the problem of leakage current crosstalk in the array is solved, the complexity of the process is necessarily increased by connecting redundant devices in series. In view of this, the present disclosure provides an array of optoelectronic synapse devices, a method for fabricating the array of optoelectronic synapse devices, and an image processing apparatus applying the array of optoelectronic synapse devices.
FIG. 1A and FIG. 1B show a front view and a top view, respectively, of an optoelectronic synapse device array structure in accordance with a preferred embodiment of the disclosure. It should be understood that the optoelectronic synapse device array structures shown in fig. 1A and 1B are merely exemplary, so as to facilitate understanding of the aspects of the disclosure by those skilled in the art, and are not intended to limit the scope of the disclosure. In other embodiments, the materials, sizes, shapes, and the like of the layers in the optoelectronic synapse device array may be selected according to practical situations, and are not limited herein.
Referring to fig. 1A and 1B together, the optoelectronic synapse device array comprises a substrate 1, a horizontal rod-shaped bottom electrode 2 disposed on the substrate 1, and a P-type semiconductor layer 3, an N-type semiconductor layer 4, a light absorption layer 5 and a transparent top electrode 6 sequentially stacked on the horizontal rod-shaped bottom electrode 2. Wherein the top electrode 6 is in a cross-bar shape and is in a vertical crossing structure with the bottom electrode 2, each crossing point forms a single optoelectronic synapse device unit (e.g., the dashed line in FIG. 1B).
In the embodiment of the present disclosure, the substrate 1 has good insulating property, and the material of the substrate 1 can be quartz, si/SiO, for example 2 Flexible Polyimide (PI) or polyethylene terephthalate (PET), and the like.
In the embodiment of the present disclosure, the bottom electrode 2 in the shape of a transverse rod is an inert metal with a high work function (for example, a work function greater than 5 eV), for example, pt or Au may be used as the material of the bottom electrode 2, and the thickness thereof may be, for example, 30 to 50nm.
In the disclosed embodiments, the P-type semiconductorThe body layer 3 is made of a P-type semiconductor thin film material with defects, such as NiO y (y≥1)、IrO 2 、Co 2 O 3 、Rh 2 O 3 Or MnO 2 The thickness of the P-type semiconductor layer 3 may be, for example, 50 to 300nm.
In the embodiment of the present disclosure, the N-type semiconductor layer 4 is made of a defective N-type semiconductor thin film material, such as WO 3-z (wherein 3 > z.gtoreq.0), VO 2 、MoO 3 、Nb 2 O 5 Or TiO 2 The thickness of the N-type semiconductor layer 4 may be, for example, 50 to 200nm.
In the embodiment of the present disclosure, the light absorption layer 5 is made of a photosensitive material compatible with semiconductor processes, and the material of the light absorption layer 5 includes, for example, si, siC, gaN, ITO x (x > 1), the light absorbing layer 5 may have a thickness of, for example, 10 to 80nm.
In the embodiment of the present disclosure, the transparent electrode material with high transparency and high electrical conductivity is used as the top electrode 6, which facilitates the light absorption layer 5 to have high light absorption, and by adding the light absorption layer, the optoelectronic synapse device unit can have optically tunable characteristics.
In the embodiment of the present disclosure, based on the photosensitive property of the light absorption layer 5, the conductive ions inside the optoelectronic synapse device unit can be increased, thereby realizing a memory device with adjustable electrical conductivity. In addition, the present disclosure may enhance the conductance of the illuminated photosynaptic device cells by applying an optical signal to the array of photosynaptic devices, and may be erased under application of a reverse voltage.
In the embodiment of the present disclosure, the material of the top electrode 6 includes ITO or FTO, for example, wherein the thickness of the top electrode 6 is 100 to 200nm, for example.
It should be noted that the above descriptions of materials, dimensions, etc. of the layers in the optoelectronic synapse device array are merely exemplary for facilitating the understanding of the disclosure by those skilled in the art, and are not intended to limit the scope of the disclosure. In other embodiments, the materials, dimensions, and the like of the layers in the optoelectronic synapse device array may be selected according to practical situations, and are not limited herein.
In the embodiment of the disclosure, by stacking the multilayer barrier regions by using the bottom electrode, the N-type semiconductor layer and the P-type semiconductor layer, the unit of the optoelectronic synapse device has a self-rectifying property, such a unidirectional conducting device can prevent a reverse current from flowing in the array, thereby suppressing a crosstalk phenomenon caused by a leakage current.
In addition, the photoelectric synapse device array based on the stacking structure in the embodiment of the disclosure has a simple manufacturing process, and overcomes the defects of high device process complexity and large manufacturing difficulty caused by solving the crosstalk problem of leakage current in the array in the prior art. In addition, the size of the photoelectric synapse device unit based on the stacked structure in the disclosure can be designed to be smaller, which is more beneficial for integration.
The photoelectric synapse device array in the embodiment of the disclosure can realize all functions of optical imaging, information storage, information processing and electrical erasing, and the array formed by the photoelectric synapse device units can realize stable sensing, memory effect and matrix operation capability (sensing, storage and calculation integration), so that the efficiency and power consumption of image detection and processing are greatly improved, the operation capability of the chip is further enhanced, a feasible scheme is provided for the design of the photoelectric synapse chip, and a new idea is provided for the visual neural network device integrating sensing, storage and calculation.
FIG. 2 is a flow chart of a method for fabricating an array of optoelectronic synapse devices in accordance with a preferred embodiment of the present disclosure.
The following detailed description of the fabrication process of the optoelectronic synapse device array in FIG. 1A is provided in connection with specific embodiments, and it should be understood that the following description is only exemplary, so as to facilitate those skilled in the art to better understand the disclosure, and is not intended to limit the scope of the disclosure.
The present disclosure provides a method for manufacturing a photoelectric synapse device array, comprising the following steps:
s210, preparing a bottom electrode on the substrate.
In particular, a substrate is selected, for example Si/SiO polished on one side 2 Cleaning the substrate with mixed solution of concentrated sulfuric acid and hydrogen peroxide for 30min, and sequentially removing with acetone, ethanol and waterThe substrate surface was cleaned by ultrasonic oscillation at 75% power for 5min and then blow-dried with nitrogen.
And preparing a transverse rod-shaped bottom electrode on the cleaned substrate through photoetching, a direct-current sputtering process and a stripping process. Wherein:
the photolithography process specifically includes the following operations: a negative photoresist (e.g., 6000rpm, 20s) is spin-coated on the substrate, and then subjected to pre-baking (e.g., 110 ℃,2 min), ultraviolet exposure (e.g., 300w, 30s), post-baking (e.g., 100 ℃,2 min), and development (e.g., 2min, 30s) operations, and after the development, a beam-like pattern, i.e., a gate pattern, is exposed on the substrate.
The direct current sputtering process comprises the following operations: use of an inert metal such as Pt to form the bottom electrode (i.e., gate) of the beam shape, since the bottom electrode of the beam shape may be in contact with SiO 2 Or the quartz substrate has low adhesiveness, so that a layer of Ti with a thickness of, for example, 5-10 nm is sputtered as an adhesion layer before sputtering the metal Pt to ensure that the transverse rod-shaped bottom electrode can be normally adhered to the substrate. Subsequently, for example, 50nm metal Pt is evaporated to prepare a bottom electrode in the form of a horizontal rod on the substrate, wherein the deposition power is, for example, 300W and the degree of vacuum is, for example, 0.8mTorr.
The stripping process comprises the following operations: soaking the film sample prepared in the previous step in acetone for 30min, washing or ultrasonically processing to assist stripping, and finally drying by using a nitrogen gun.
S220, the bottom electrode is placed in an oxygen-deficient state to deposit a P-type semiconductor layer.
The steps are realized through a photoetching process and a magnetron sputtering process in sequence. Wherein:
the photolithography process specifically comprises the following operations: a negative photoresist (rotational speed of 6000rpm, 20s) is coated on a substrate in a spinning mode, and then the substrate is subjected to pre-baking (110 ℃ C., 2min for example), ultraviolet exposure (300W, 30s) and post-baking (100 ℃ C., 2min for example) and development (2min, 30s), and after the development, an exposed pattern is a pattern of a P-type semiconductor layer.
The magnetron sputtering P-type semiconductor layer specifically comprises: for example, a Ni target having a purity of 99.99% is subjected to magnetron sputtering under conditions of a ratio of argon gas to oxygen gas of, for example, 30: 4 and a degree of vacuum of 0.5mTorr using a power of 200W, and the thickness of the finally obtained P-type semiconductor layer is, for example, 50 to 300nm.
And S230, forming an N-type semiconductor layer on the P-type semiconductor layer.
This step is realized by a magnetron sputtering process, for example, a W target having a power of 300W and a radio frequency sputtering purity of 99.99% is used, magnetron sputtering is performed under the conditions that the ratio of argon gas to oxygen gas is, for example, 20: 6, and the degree of vacuum is 0.5mTorr, and the thickness of the finally produced N-type semiconductor layer is, for example, 50 to 200nm.
And S240, forming a light absorption layer on the N-type semiconductor layer.
Preparing a light absorption layer by a magnetron sputtering process, specifically, carrying out magnetron sputtering on an ITO target material with the radio frequency sputtering purity of 99.99 percent under the conditions that the ratio of argon to oxygen is 50: 20, the vacuum degree is 0.5mTorr and the temperature is 100 ℃ by using the power of 200W, and finally preparing the ITO with high oxidation degree x The material is used as a light absorbing layer and has a thickness of, for example, 10 to 80nm.
After the light absorption layer is formed, a peeling process is required to peel the three layers of materials, specifically, the film sample prepared in the previous step is soaked in acetone for 30min, washed or ultrasonically assisted for peeling, and finally dried by a nitrogen gun.
And S250, forming a transparent top electrode on the surface of the light absorption layer to obtain the photoelectric synapse device array, wherein the top electrode and the bottom electrode maintain a vertical crossing structure, and each crossing point forms an individual photoelectric synapse device unit.
The step can be realized by photoetching, magnetron sputtering and stripping processes in turn. Wherein:
the photoetching process specifically comprises the following steps: a negative photoresist (e.g., 6000rpm, 20s) is spin-coated on a substrate, and then a photoresist pattern is prepared on the substrate through pre-baking (e.g., 110 ℃,2 min), ultraviolet exposure (e.g., 300W, 30s), post-baking (e.g., 100 ℃,2 min) and development (2min, 30s), and the top electrode pattern in a horizontal rod shape is exposed after the development.
And then preparing the transparent horizontal rod-shaped top electrode by a magnetron sputtering process, specifically, performing magnetron sputtering on an ITO target with the purity of 99.99% by using 200W of power and direct current at the temperature of 100 ℃ and the vacuum degree of 0.5mTorr and the ratio of argon to oxygen of 50: 5, wherein the thickness of the finally prepared transparent horizontal rod-shaped top electrode is 100-200 nm.
And finally, carrying out a stripping process, specifically, soaking the thin film sample prepared in the previous step in acetone for 30min, washing or carrying out ultrasonic to assist stripping, then drying by using a nitrogen gun, and finally preparing the photoelectric synapse device array based on the stacking structure.
It should be noted that the process method, the process parameters, the size and the thickness of each layer, and the like shown in the above steps are only exemplary, and the solution of the embodiment of the present disclosure is not limited thereto. For example, in some other embodiments, in step S210, vacuum evaporation may be used in the process of preparing the bottom electrode in the shape of a horizontal rod instead of the magnetron sputtering bottom electrode, and the specific vacuum evaporation process may be controlled according to actual needs as long as the bottom electrode in the shape of a horizontal rod can be formed.
In order to make the technical solution of the present disclosure more clearly understood by those skilled in the art, the following will describe in detail the advantages of the optoelectronic synapse device array of the embodiments of the present disclosure with reference to specific embodiments and fig. 3-9. It should be understood that the following description is intended only by way of example, to assist those skilled in the art in understanding the aspects of the present disclosure, and is not intended to limit the scope of the present disclosure.
Example (b):
in the present embodiment, the optoelectronic synapse device array structure shown in fig. 1A and 1B is adopted, and specifically, the optoelectronic synapse device array comprises a substrate 1, a horizontal rod-shaped bottom electrode 2, a P-type semiconductor layer 3, an N-type semiconductor layer 4, a light absorption layer 5, and a transparent horizontal rod-shaped top electrode 6 sequentially stacked on the bottom electrode 2. The materials of each layer are respectively as follows: the substrate 1 is Si/SiO 2 The horizontal rod-shaped bottom electrode 2 is Ti/Pt, the P-type semiconductor layer 3 is NiO y The N-type semiconductor layer 4 is WO 3-z The light absorbing layer 5 is ITO having a high degree of oxidation x The material, the horizontal rod-like top electrode 6 is ITO. Based on the structure, the photoelectric projection is finally formedContact device array (Pt/NiO) y /WO 3-z /ITO x ITO) in which each crossing forms a separate optoelectronic synapse device element (Pt/NiO) y /WO 3-z /ITO x /ITO)。
In this embodiment, the photoelectric synapse device array (Pt/NiO) y /WO 3-z /ITO x ITO) were tested for different characteristics and applications, as will be described below in connection with fig. 3-9.
FIG. 3 shows a photoelectric synapse device cell (Pt/NiO) y /WO 3-z /ITO x ITO) expected results of current-voltage characteristic curves for positive and negative voltage sweeps with and without light.
As shown in fig. 3, in the non-illumination environment, the optoelectronic synapse device unit has an IV loop with a rectifying effect, and in the illumination environment, the positive current of the optoelectronic synapse device unit rapidly increases, but the negative current is still in the off state, so that it is known that the optoelectronic synapse device unit has an obvious rectifying characteristic in both the illumination environment and the non-illumination environment.
FIG. 4 shows a photoelectric synapse device cell (Pt/NiO) y /WO 3-z /ITO x ITO) expected results of the current-time course (memory characteristics) after a single light signal irradiation.
As shown in FIG. 4, by monitoring the current of the photo-synapse device unit in the photo-synapse device array, it can be determined whether the photo-synapse device unit is working normally. When a single pulse of light is used, the electrical conductance of the photosynaptic device cell increases to a higher electrical conductance state; after the light is removed, the current of the optoelectronic synapse device unit can still keep in the original high conducting state, thereby proving that the optoelectronic synapse device unit in this embodiment has good memory characteristics.
FIG. 5 shows a photoelectric synapse device cell (Pt/NiO) y /WO 3-z /ITO x ITO) the expected result of erasing with negative voltage after multiple optical signal writes.
As shown in FIG. 5, the present embodiment can achieve multi-pulse multi-cycle erase/write operations by performing multiple optical writes and electrical erases on the photo-synapse device cells in the array of photo-synapse devices. Therefore, the present embodiment can accurately control the optoelectronic synapse device unit through the optical signal and the electrical signal, and effectively improve the stability and the repeatability of the optoelectronic synapse device unit.
FIGS. 6A and 6B are the photoelectric synapse device elements (Pt/NiO), respectively y /WO 3-z /ITO x ITO) under the action of illumination and a band mechanism under the action of illumination.
As shown in FIG. 6A, a small forward reading voltage is applied to the bottom electrode of the photo-synapse device cell, and light is applied to the photo-absorption layer to generate photo-generated electrons, which migrate downward to generate an upward photocurrent.
As shown in FIG. 6B, corresponding to FIG. 6A, under the action of the forward reading voltage, the potential barrier of the heterojunction formed by the P-type semiconductor layer and the N-type semiconductor layer and the gold half-contact is lowered, so that the ion migration of photo-generated electrons and negative charges is facilitated, and the conductance performance of the photoelectric synapse device unit is changed.
FIGS. 7A and 7B are the photoelectric synapse device elements (Pt/NiO), respectively y /WO 3-z /ITO x ITO) under reverse voltage action and a band mechanism under the reverse voltage action.
As shown in FIG. 7A, when a large positive operating voltage is applied to the top electrode of the photosynaptic device cell, the current is suppressed and no downward current can be generated.
As shown in fig. 7B, according to fig. 7A, since the potential barrier is increased at a negative voltage, electrons cannot smoothly flow from the bottom electrode to the top electrode, and both negative charges are blocked by the potential barrier, so that no current flows.
FIG. 8 is a schematic diagram illustrating a process of blocking crosstalk between photosynaptic device units in an array of photosynaptic devices.
Referring to fig. 8, (a, a) shows the optoelectronic synapse device elements in row a and column a, and (b, a), (b, b) and (a, b) have similar definitions, and are not repeated herein.
Assuming that the optoelectronic synapse device units around the optoelectronic synapse device unit (a, a) are all high-conductivity devices, when the optoelectronic synapse device unit (a, a) is subjected to optical writing operation, a forward current flows to the top electrode, but the nearby optoelectronic synapse device units (b, a), (b, b) and (a, b) are also high-conductivity, but due to rectification characteristics, the current does not flow through the optoelectronic synapse device unit at the position (b, b), so that the formation of leakage current crosstalk is blocked, and misreading of the device conductivity state is avoided.
FIG. 9 is a schematic diagram of an array of optoelectronic synapse devices in optical imaging, information storage and information processing processes in accordance with an embodiment of the disclosure.
Referring to FIG. 9, an image A is processed by the lens assembly 200 and then transmitted to the optoelectronic synapse device array 100. By reading the voltage (V) read ) The conductance state of the photosynaptic device unit can be measured, and due to the conductance state memory property of the photosynaptic device unit, the photosurred photosynaptic device array can perform matrix operation through electric pulses.
The photoelectric synapse device array in the embodiment of the disclosure can realize all functions of optical imaging, information storage, information processing and electrical erasing, and the array formed by the device units can realize sensing, storing and computing integration, so that the efficiency and power consumption of image detection and processing are greatly improved, the operational capability of the chip is further enhanced, a feasible scheme is provided for the design of the photoelectric synapse chip, and a new thought is provided for the visual neural network device integrating sensing, storing and computing.
Another aspect of the present disclosure also provides an image processing apparatus, which includes all the technical features of the optoelectronic synapse device array described above, that is, has the technical effects brought by all the technical features described above, and thus, no further description is given here.
In summary, the present disclosure provides a photoelectric synapse device array, a method for fabricating the same, and an image processing apparatus. The photoelectric synapse device array enables the photoelectric synapse device units to have self-rectification characteristics by stacking a plurality of barrier regions through the bottom electrode, the N-type semiconductor layer and the P-type semiconductor layer, and the unidirectional conducting device can prevent reverse current from flowing in the array, so that a crosstalk phenomenon caused by leakage current is inhibited.
In addition, the photoelectric synapse device array can realize all functions of optical imaging, information storage, information processing and electrical erasing, and the sensing, storage and calculation integration can be realized through the array formed by the photoelectric synapse device units, so that the efficiency and the power consumption of image detection and processing are greatly improved, the operational capability of a chip is further enhanced, a feasible scheme is provided for the design of the photoelectric synapse chip, and a new thought is provided for the sensing, storage and calculation integrated visual neural network device.
The above-mentioned embodiments, objects, technical solutions and advantages of the present disclosure are further described in detail, it should be understood that the above-mentioned embodiments are only examples of the present disclosure, and should not be construed as limiting the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims (9)

1. An array of optoelectronic synapse devices, comprising:
a bottom electrode;
the P-type semiconductor layer, the N-type semiconductor layer, the light absorption layer and the transparent top electrode are sequentially stacked on the bottom electrode;
wherein the top electrode and the bottom electrode maintain a vertical crossing structure, and each crossing point forms a single photoelectric synapse device unit;
wherein the material of the light absorption layer comprises Si, siC, gaN or ITO x Wherein x > 1.
2. The array of optoelectronic synapse devices of claim 1, wherein the bottom electrode comprises an inert metal with a work function greater than 5 eV.
3. The optoelectronic synapse device array of claim 1, wherein the P-type semiconductor layer is a defective P-type semiconductor thin film material; and/or the N-type semiconductor layer adopts a defective N-type semiconductor thin film material.
4. The optoelectronic synapse device array of claim 3, wherein the material of the P-type semiconductor layer comprises NiO y 、IrO 2 、Co 2 O 3 、Rh 2 O 3 Or MnO 2 (ii) a And/or the material of the N-type semiconductor layer comprises WO 3-z 、VO 2 、MoO 3 、Nb 2 O 5 Or TiO 2 Wherein y is more than or equal to 1,3 and z is more than or equal to 0.
5. The array of optoelectronic synapse devices of claim 1, wherein the light absorbing layer comprises a photosensitive material compatible with semiconductor processes.
6. The array of optoelectronic synapse devices of claim 1, wherein the material of the top electrode comprises ITO or FTO.
7. The array of optoelectronic synapse devices of any one of claims 1-6, further comprising: the substrate, the bottom electrode is located the surface of substrate.
8. A method of fabricating an array of optoelectronic synapse devices as claimed in any of claims 1-7, comprising:
preparing a bottom electrode on a substrate;
placing the bottom electrode in an oxygen-deficient state to deposit a P-type semiconductor layer;
forming an N-type semiconductor layer on the P-type semiconductor layer;
forming a light absorption layer on the N-type semiconductor layer;
and forming a transparent top electrode on the surface of the light absorption layer to obtain the optoelectronic synapse device array, wherein the top electrode and the bottom electrode are in a vertical crossing structure, and each crossing point forms an individual optoelectronic synapse device unit.
9. An image processing apparatus comprising an array of optoelectronic synapse devices as claimed in any one of claims 1-7.
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