CN113793636A - Flash memory block abrasion degree evaluation method and solid state disk - Google Patents
Flash memory block abrasion degree evaluation method and solid state disk Download PDFInfo
- Publication number
- CN113793636A CN113793636A CN202111064333.7A CN202111064333A CN113793636A CN 113793636 A CN113793636 A CN 113793636A CN 202111064333 A CN202111064333 A CN 202111064333A CN 113793636 A CN113793636 A CN 113793636A
- Authority
- CN
- China
- Prior art keywords
- flash memory
- value
- memory block
- rber
- flash
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims abstract description 235
- 238000011156 evaluation Methods 0.000 title claims abstract description 58
- 238000005299 abrasion Methods 0.000 title claims abstract description 44
- 239000007787 solid Substances 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 39
- 238000012937 correction Methods 0.000 claims description 27
- 238000002347 injection Methods 0.000 claims description 16
- 239000007924 injection Substances 0.000 claims description 16
- 238000004590 computer program Methods 0.000 claims description 5
- WELIVEBWRWAGOM-UHFFFAOYSA-N 3-amino-n-[2-[2-(3-aminopropanoylamino)ethyldisulfanyl]ethyl]propanamide Chemical compound NCCC(=O)NCCSSCCNC(=O)CCN WELIVEBWRWAGOM-UHFFFAOYSA-N 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 9
- 230000002035 prolonged effect Effects 0.000 abstract description 5
- 238000012423 maintenance Methods 0.000 description 15
- 238000004364 calculation method Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 230000009471 action Effects 0.000 description 4
- 230000014759 maintenance of location Effects 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 239000010410 layer Substances 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000007726 management method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 230000002277 temperature effect Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000001550 time effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
Landscapes
- Read Only Memory (AREA)
Abstract
The invention discloses an evaluation method of the abrasion degree of a flash memory block and a solid state disk, which are used for obtaining the electron leakage degree value of the flash memory block just after electrons are injected; acquiring an electron leakage trend value of the flash memory block injected with electrons; and evaluating the abrasion degree of the flash memory block according to the electronic leakage degree value and the electronic leakage trend value of the flash memory block. Therefore, the method and the device can evaluate the abrasion degree of the flash memory block from two dimensions of the electronic leakage degree value and the electronic leakage trend value of the flash memory block, and compared with a method that the single erasing frequency is used as an abrasion evaluation index, the abrasion degree can be evaluated from the two dimensions more comprehensively and accurately, so that the abrasion balance effect is better, and the whole service life of the solid state disk is prolonged.
Description
Technical Field
The invention relates to the field of solid-state storage, in particular to a flash memory block abrasion degree evaluation method and a solid-state hard disk.
Background
Flash memory contains a plurality of flash blocks (blocks), each containing a plurality of flash pages (pages). The flash memory block is a basic unit for erasing the flash memory, and after data is written into a flash memory page, new writing operation can be performed only after the erasing operation is performed on the flash memory block.
At present, for a solid state disk based on a flash memory (a solid state disk using a flash memory chip as a storage medium), wear leveling of each flash memory block is a key factor for ensuring storage reliability of the solid state disk. In order to realize the balanced control of the abrasion of each flash memory block, the abrasion degree of each flash memory block needs to be accurately evaluated, which is also beneficial to evaluating the service life of the solid state disk based on the abrasion degree of each flash memory block.
In the prior art, the wear degree of a flash memory block is generally evaluated based on the erasing times of the flash memory block, and the wear condition of the flash memory block is more serious when the erasing times of the flash memory block are more. However, only a single erasing frequency is not comprehensive and accurate enough as a wear evaluation index, so that the wear balance effect is influenced, and the overall service life of the solid state disk is further influenced.
Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide an evaluation method of the abrasion degree of a flash memory block and a solid state disk, wherein the abrasion degree of the flash memory block is evaluated from two dimensions of an electronic leakage degree value and an electronic leakage trend value of the flash memory block, and compared with a single erasing frequency as an abrasion evaluation index, the abrasion degree is evaluated from the two dimensions more comprehensively and accurately, so that the abrasion balance effect is better, and the whole service life of the solid state disk is further prolonged.
In order to solve the technical problem, the invention provides a flash memory block wear degree evaluation method, which comprises the following steps:
acquiring an electron leakage degree value of the flash memory block immediately after electrons are injected;
acquiring an electron leakage trend value of the flash memory block injected with electrons;
and evaluating the abrasion degree of the flash memory block according to the electronic leakage degree value and the electronic leakage trend value of the flash memory block.
Preferably, the obtaining of the electron leakage degree value of the flash memory block immediately after the injection of the electrons comprises:
acquiring the erasing times of the flash memory block, and acquiring an initial error bit evaluation value of the flash memory block just after the electrons are injected;
determining an electron leakage degree value of the flash memory block just after the electrons are injected according to the erasing times and the initial error bit evaluation value; wherein the number of erasures and the initial error bit evaluation value have a positive correlation with the electron leakage level value.
Preferably, the obtaining an initial error bit evaluation value of the flash memory block immediately after the injection of electrons comprises:
acquiring an IRBER value or an IFBC value of the flash memory block just after the electrons are injected, and acquiring a temperature value of the flash memory block just after the electrons are injected;
and correspondingly correcting the IRBER value or the IFBC value according to the temperature value to obtain an IRBER correction value or an IFBC correction value of the flash memory block just after the electrons are injected, and using the IRBER correction value or the IFBC correction value as the initial error bit evaluation value.
Preferably, determining an electron leakage level value of the flash memory block immediately after injecting electrons according to the number of erasures and the initial error bit evaluation value includes:
calculating an electron leakage degree value LL of the flash block just after the electrons are injected according to LL ═ EPC δ IRBER or LL ═ EPC δ IFBC;
wherein EPC is the erasing times; δ IRBER is the IRBER correction value; δ IFBC is the IFBC correction value; and delta is a first temperature compensation coefficient corresponding to the temperature value.
Preferably, obtaining an electron leakage trend value of the flash memory block into which electrons have been injected comprises:
acquiring a unit error bit increase evaluation value of the flash memory block injected with electrons in a preset time, and acquiring an average temperature value of the flash memory block in the preset time;
and correcting the unit error bit increase evaluation value according to the average temperature value to obtain an electronic leakage trend value of the flash memory block in the preset time.
Preferably, obtaining a unit error bit growth evaluation value of the flash memory block into which electrons have been injected within a preset time includes:
acquiring the RBER growth amount or FBC growth amount of the flash memory block injected with electrons in a preset time;
dividing the RBER growth amount or the FBC growth amount by the preset time to correspondingly obtain the RBER growth rate or the FBC growth rate of the flash memory block in unit time, and taking the RBER growth rate or the FBC growth rate as the unit error bit growth evaluation value.
Preferably, the modifying the unit error bit increase evaluation value according to the average temperature value to obtain an electron leakage trend value of the flash memory block within the preset time includes:
judging whether the average temperature value is greater than a preset standard temperature or not;
if so, then according to
Or
Calculating an electron leakage trend value LT of the flash memory block in the preset time; wherein Δ t is the preset time; Δ RBER is the RBER growth; Δ FBC is the FBC growth;γa second temperature compensation coefficient corresponding to the average temperature value, wherein gamma is less than 1;
if not, according to
Or
And calculating an electron leakage trend value LT of the flash memory block in the preset time.
Preferably, the method for evaluating the wear degree of the flash memory block further comprises the following steps:
correspondingly subtracting the current RBER value or FBC value of the flash memory block from the preset error correction capability threshold value RBER 'or FBC' corresponding to the flash memory block to obtain the current RBER increase margin or FBC increase margin of the flash memory block;
and correspondingly dividing the current RBER increase margin or FBC increase margin of the flash memory block by the current RBER increase rate or FBC increase rate of the flash memory block to obtain the current data remaining holding time of the flash memory block.
Preferably, the evaluating the degree of wear of the flash memory block based on the electron leakage level value and the electron leakage tendency value of the flash memory block comprises:
calculating the abrasion degree Pa of the flash block according to Pa ═ (alpha LL, beta LT); wherein LL is an electron leakage degree value of the flash memory block; LT is an electron leakage tendency value of the flash memory block; pa is a two-dimensional value of LL and LT; alpha and beta are scaling factors for adjusting the proportional relation of LL and LT; the larger the LL and LT, the more severe the wear of the flash block.
In order to solve the above technical problem, the present invention further provides a solid state disk, including:
flashing;
a controller for implementing the steps of any of the above described methods for assessing flash block wear when executing the computer program.
The invention provides an evaluation method of the abrasion degree of a flash memory block, which comprises the steps of obtaining an electron leakage degree value of the flash memory block just after electrons are injected; acquiring an electron leakage trend value of the flash memory block injected with electrons; and evaluating the abrasion degree of the flash memory block according to the electronic leakage degree value and the electronic leakage trend value of the flash memory block. Therefore, the method and the device can evaluate the abrasion degree of the flash memory block from two dimensions of the electronic leakage degree value and the electronic leakage trend value of the flash memory block, and compared with a method that the single erasing frequency is used as an abrasion evaluation index, the abrasion degree can be evaluated from the two dimensions more comprehensively and accurately, so that the abrasion balance effect is better, and the whole service life of the solid state disk is prolonged.
The invention also provides a solid state disk which has the same beneficial effect as the abrasion degree evaluation method.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a flowchart of a method for evaluating the wear of a flash memory block according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an electron leakage of a memory cell according to an embodiment of the present invention;
FIG. 3 is a comparison graph of RBER of different flash blocks under the same DR conditions and EPC according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating the relationship between DR time and RBER of the same flash memory block at the same EPC and different temperatures according to an embodiment of the present invention;
FIG. 5 is a comparison graph of RBER of different flash blocks under the same EPC and different DR conditions according to an embodiment of the present invention;
FIG. 6 is a comparison graph of RBER of a flash block A and a flash block B under different DR conditions according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating the relationship between DR time and RBER of a flash block according to an embodiment of the present invention;
FIG. 8 is a two-dimensional graph of the wear level of a flash block provided by an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a solid state disk SSD according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a solid state disk SSD according to an embodiment of the invention;
fig. 11 is a conceptual diagram of a solid state disk SSD according to an embodiment of the invention;
fig. 12 is a schematic diagram of obtaining a Δ RBER parameter according to an embodiment of the present invention;
fig. 13 is a flowchart of maintaining a maintenance table according to an embodiment of the present invention.
Detailed Description
The core of the invention is to provide an evaluation method of the abrasion degree of the flash memory block and the solid state disk, the abrasion degree of the flash memory block is evaluated from two dimensions of an electronic leakage degree value and an electronic leakage trend value of the flash memory block, and compared with a single erasing frequency as an abrasion evaluation index, the abrasion degree is evaluated from the two dimensions more comprehensively and accurately, so that the abrasion balance effect is better, and the whole service life of the solid state disk is further prolonged.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart illustrating a method for evaluating wear of a flash memory block according to an embodiment of the present invention.
The method for evaluating the abrasion degree of the flash memory block comprises the following steps:
step S1: and acquiring the electron leakage degree value of the flash memory block just after the electrons are injected.
Step S2: an electron leakage tendency value of the flash memory block into which electrons have been injected is obtained.
Step S3: and evaluating the abrasion degree of the flash memory block according to the electronic leakage degree value and the electronic leakage trend value of the flash memory block.
Specifically, flash memory is a non-volatile storage medium, which is widely used and is suitable for various storage situations, and the architecture thereof is generally divided into three types, namely SLC (Single-Level Cell, Single-layer Cell, which means that 1 memory Cell can store 1 bit of data, and there are two cases of 0 and 1), MLC (Multi-Level Cell, double-layer Cell, which means that 1 memory Cell can store 2 bits of data, and there are four cases of (11, 10, 01, 00)), and TLC (Triple-Level Cell, three-layer Cell, which means that 1 memory Cell can store 3 bits of data, and there are 8 cases of (000, 001, 010, 011, 100, 101, 110, 111)).
For SLC flash, each flash page in a flash block is used to store a single bit of data. For the MLC flash memory, each data block includes two types of pages, which are called MSB (Most Significant Bit) page and LSB (Least Significant Bit) page, respectively, where the MSB page is used to store the high bits of the two bits, and the LSB page is used to store the low bits of the two bits; that is, the MSB page and the LSB page are a pair of pages, and the high bits in the MSB page and the corresponding low bits in the LSB page constitute the complete double bits. For the TLC flash memory, each data block includes three types of pages, which are called MSB (Most Significant Bit) page, CSB (Central Significant Bit) page and LSB (Least Significant Bit) page, respectively, where the MSB page is used for storing the upper bits of three bits, the CSB page is used for storing the middle bits of the three bits, and the LSB page is used for storing the lower bits of the three bits; that is, the MSB page, the CSB page, and the LSB page are a pair of pages, and the high bits in the MSB page, the corresponding middle bits in the CSB page, and the corresponding low bits in the LSB page constitute the complete three bits.
Flash memories actually store electrons in a memory Cell (Cell), and the number of stored electrons is represented as a voltage value to express a stored bit value by the voltage value. Flash memory errors are mainly read misjudgment caused by voltage changes of memory cells due to electron leakage, namely, a wrong bit value occurs, and if the number of wrong bits is larger than the error correction capability of a reading device, the flash memory is not usable.
And wear is a major factor affecting the electronic storage capacity of the memory cell. For easy understanding, as shown in fig. 2, the memory cell corresponds to a room with a door, the writing operation is to inject electrons, and the target is to inject 100 electrons, but due to wear and tear, only 90 electrons are injected (in the case of TLC, 3 bits of the memory cell are read, and 1 bit error is shown to the outside) when the actual completion is completed, the electrons continuously escape with time, and only 80 electrons remain when the reading is performed again (in the case of reading 3 bits of the memory cell, and 2 bit errors are shown to the outside). It will be appreciated that the degree of wear of a flash block can be assessed using two dimensions, the electron leakage level value and the electron leakage trend value of the flash block; the electronic leakage degree value of the flash memory block represents an initial state (difference between the actual quantity of injected electrons and the expected quantity of injected electrons) of the flash memory block just after the electrons are injected, and is externally represented by an initial error bit number of the flash memory block just after data are written; the trend value of electron leakage of a flash block is characterized by the change of state (electron escape speed) of the flash block into which electrons are injected, and is externally represented by the fact that the number of error bits is continuously increased on the basis of the initial number of error bits.
Based on the method, the electronic leakage degree value of the flash memory block just after the electrons are injected (the corresponding electronic leakage degree value can be obtained just after the electrons are injected each time) is obtained, the electronic leakage trend value of the flash memory block with the injected electrons is obtained, then the abrasion degree of the flash memory block is evaluated according to the electronic leakage degree value and the electronic leakage trend value of the flash memory block (the larger the electronic leakage degree value and the electronic leakage trend value of the flash memory block are, the more serious the abrasion condition of the flash memory block is, and once the electronic leakage degree value and the electronic leakage trend value of the flash memory block are changed, the abrasion condition of the flash memory block is changed along with the change of the electronic leakage degree value and the electronic leakage trend value of the flash memory block), and therefore the balanced control of the abrasion degree of each flash memory block in the solid state hard disk is achieved.
Therefore, the method and the device can evaluate the abrasion degree of the flash memory block from two dimensions of the electronic leakage degree value and the electronic leakage trend value of the flash memory block, and compared with a method that the single erasing frequency is used as an abrasion evaluation index, the abrasion degree can be evaluated from the two dimensions more comprehensively and accurately, so that the abrasion balance effect is better, and the whole service life of the solid state disk is prolonged.
On the basis of the above-described embodiment:
as an alternative embodiment, obtaining an electron leakage degree value of the flash memory block immediately after injecting electrons comprises:
acquiring the erasing times of the flash memory block, and acquiring an initial error bit evaluation value of the flash memory block just after the electrons are injected;
determining an electron leakage degree value of the flash memory block just after the electrons are injected according to the erasing times and the initial error bit evaluation value; wherein, the erasing times and the initial error bit evaluation value have positive correlation with the electron leakage degree value.
Specifically, it is considered that the number of times of erasing the flash memory block and the electron leakage degree value of the flash memory block immediately after the electrons are injected have a positive correlation, that is, the larger the number of times of erasing the flash memory block is, the larger the electron leakage degree value of the flash memory block immediately after the electrons are injected is; the method comprises the steps of obtaining an initial error bit evaluation value of a flash block immediately after electron injection and an electron leakage degree value of the flash block immediately after electron injection, wherein the initial error bit evaluation value of the flash block immediately after electron injection is larger, which indicates that the electron leakage degree value of the flash block immediately after electron injection is larger.
As an alternative embodiment, obtaining an initial error bit evaluation value of a flash block immediately after injecting electrons includes:
acquiring an IRBER value or an IFBC value of the flash memory block just after the electrons are injected, and acquiring a temperature value of the flash memory block just after the electrons are injected;
and correspondingly correcting the IRBER value or the IFBC value according to the temperature value to obtain an IRBER correction value or an IFBC correction value of the flash memory block just after the electrons are injected, and taking the IRBER correction value or the IFBC correction value as an initial error bit evaluation value.
Specifically, as shown in fig. 3, RBER (Raw Bit Error Rate) of different flash blocks is different under the same DR (Data Retention) condition and EPC (Erase-Program Cycles). For example, under the nominal EPC, the RBERs of the flash blocks B0, B1, B2 are different, so that introducing RBER as an index for wear evaluation has feasibility: RBER represents the wear of different flash blocks.
Research on the characteristics of flash memories shows that RBER can be strongly related to DR conditions (including but not limited to storage time and temperature) in practical application. As shown in fig. 4, the DR time (T) and RBER of the same flash memory block are plotted at different temperatures (T) and the same EPC. As can be seen from the horizontal axis of FIG. 4, the longer the DR time of the flash block, the larger the RBER of the flash block, e.g., at the same temperature T0, RBER (T0, T2) > RBER (T0, T1) > RBER (T0, T0). As can be seen from the vertical axis of fig. 4, the higher the temperature of the flash block is, the larger the RBER of the flash block is, and the shorter the DR time is, such as at the same time T0, RBER (T2, T0) > RBER (T1, T0) > RBER (T0, T0).
It can be seen that if RBER is used as an indicator for wear assessment, the effect of DR conditions must be considered. As shown in fig. 5, RBER (blockb) > RBER (blocka) in terms of attributes, but comparison was performed after RBER reading under different DR conditions (different temperatures and different times) and different flash memory blocks: RBER (blockab, T0, T2) > RBER (blockaa, T2, T0) > RBER (blockab, T0, T0) > RBER (blockaa, T0, T0), completely different conclusions are evident. For example, as shown in fig. 6, after the data is written into the flash block a for 1 day, the data is written into the flash block B, and the flash block a is at a higher temperature (50 ℃) within 1 day of the data writing, while the flash block B is at a normal temperature (25 ℃) 1 day after the data writing, and at this time, the rber (blocka) of the flash block a is more likely to be rber (blocka) > rber (blockb) than the rber (blockb) of the flash block B. Thus, if RBER is used as a wear assessment indicator, values without the impact of the DR condition need to be extracted, or based on the same DR condition, for comparability and usability, while the impact of the DR condition is somewhat limiting: the effect of the DR condition after re-erase is zeroed. As shown in fig. 7 (horizontal axis is data retention time, vertical axis is RBER; after data is written, there is an IRBER (Initial Raw Bit Error Rate), and as time increases, the Error Bit increases, i.e. it is represented as an increase in RBER, and the increase curve is affected by temperature, which is not expressed in the figure, and the temperature part refers to fig. 4).
Based on this, the IRBER value of the flash block just after the injection of electrons (initial RBER value just after the writing of data) is obtained, the temperature value T1 of the flash block just after the injection of electrons is obtained, then the IRBER value is correspondingly corrected (temperature influence is reduced) according to the temperature value T1, and the IRBER corrected value of the flash block just after the injection of electrons is obtained, and the IRBER corrected value of the flash block just after the injection of electrons is the initial error bit evaluation value of the flash block just after the injection of electrons.
The calculation relationship of the electron Leakage Level LL (Leakage Level) of any flash block just after the injection of electrons can be expressed as: the LL ═ f (EPC) f (f1(T1) × IRBER) indicates that the electron leakage level value LL is a functional relationship between EPC and IRBER, and it should be noted that the EPC and IRBER of the flash block are in a positive correlation with LL. In addition, since the IRBER value of the flash memory block immediately after the injection of electrons is affected by temperature, the present application further provides a first temperature compensation coefficient f1(T1) to correct the IRBER value by the first temperature compensation coefficient f1(T1), thereby reducing the effect of temperature on the IRBER value as much as possible.
It should be noted that FBC (Failure Bit Counter) and RBER of the flash block have similar meanings, and the relationship between FBC and RBER can be expressed as FBC ═ RBER BitCNT, and BitCNT is the total number of bits of the flash block. Therefore, the RBERs mentioned in this embodiment can be expressed by FBC instead, and similarly, IRBER can also be expressed by IFBC (Initial Failure Bit Counter).
As an alternative embodiment, determining an electron leakage level value of the flash memory block just after injecting electrons according to the number of erasures and the initial error bit evaluation value includes:
calculating an electron leakage degree value LL of the flash block just after the electrons are injected according to LL ═ EPC δ IRBER or LL ═ EPC δ IFBC;
wherein EPC is the number of times of erasing; delta. IRBER is an IRBER correction value; δ IFBC is an IFBC correction value; delta is a first temperature compensation coefficient corresponding to the temperature value.
Specifically, the calculation relation of the electron leakage level value LL of the flash memory block immediately after the injection of electrons is specifically as follows: LL ═ EPC × δ IRBER or LL ═ EPC × δ IFBC; wherein δ is a first temperature compensation coefficient corresponding to the temperature value T1, for example, δ ∈ {1.1,1.2,1.3,1.4 … … } (T1 ═ 40 ℃,50 ℃,60 ℃,70 ℃, … …), that is, δ is 1.1 when T1 ═ 40 ℃; when T1 is 50 ℃, delta is 1.2; when T1 is 60 ℃, delta is 1.3; when T1 is 70 ℃, δ is 1.4 … … (of course, δ may be set to other compensation values, and set according to actual requirements).
The equation for calculating the electron leakage level value LL of the flash memory block immediately after the injection of electrons may be: LL ═ EPC + k · (δ × IRBER), k is a preset coefficient; it is possible to consider a relational expression where LL is i × EPC + j (δ × IRBER), i and j are predetermined coefficients, and EPC, IRBER (or IFBC), and LL are in a positive correlation relationship.
As an alternative embodiment, the obtaining of the electron leakage trend value of the flash memory block with injected electrons comprises:
acquiring a unit error bit increase evaluation value of a flash memory block injected with electrons in preset time, and acquiring an average temperature value of the flash memory block in the preset time;
and correcting the unit error bit increase evaluation value according to the average temperature value to obtain an electronic leakage trend value of the flash memory block in a preset time.
Specifically, the electron leakage trend value of the flash memory block represents the electron escape speed, and as electrons escape from the flash memory block, more and more error bits occur, so the electron escape speed of the flash memory block in the preset time can be represented by the unit error bit increase evaluation value of the flash memory block in the preset time.
Based on the above, the present application obtains the unit error bit increase evaluation value of the flash memory block with injected electrons in the preset time, and in order to reduce the temperature influence, the present application also obtains the average temperature value T2 of the flash memory block in the preset time, and then corrects the unit error bit increase evaluation value of the flash memory block in the preset time according to the average temperature value T2 of the flash memory block in the preset time, and the corrected result is the electron leakage trend value of the flash memory block in the preset time.
As an alternative embodiment, obtaining a unit error bit growth evaluation value of a flash block into which electrons have been injected within a preset time includes:
acquiring the RBER growth amount or FBC growth amount of the flash memory block injected with electrons in a preset time;
and dividing the RBER growth amount or the FBC growth amount by preset time to correspondingly obtain the RBER growth rate or the FBC growth rate of the flash block in unit time, and taking the RBER growth rate or the FBC growth rate as a unit error bit growth evaluation value.
Specifically, the unit error bit growth evaluation value of the flash memory block in the preset time can be expressed as:
the method includes the steps that delta RBER is the RBER growth amount of flash blocks in a preset time delta t (the speed accuracy of the delta RBER depends on the value of the delta t, the delta t values among the flash blocks are kept consistent, the specific value of the delta t values is determined by the service type of a specific embodiment, for example, 24 hours and even 30 days can be considered), namely the RBER growth amount of the flash blocks with injected electrons in the preset time delta t is obtained, the RBER growth amount is divided by the preset time delta t to obtain the RBER growth rate of the flash blocks in unit time, and the RBER growth rate of the flash blocks in unit time is the unit error bit growth evaluation value of the flash blocks in the preset time.
The calculation relationship of the electron Leakage Trend value LT (Leakage Trend) of any flash memory block within the preset time Δ t can be expressed as: the LT ═ f (Δ RBER/Δ T) × f2(T2) indicates that the electron leakage tendency value LT is a functional relationship of Δ RBER/Δ T (RBER increase rate), and it should be noted that Δ RBER/Δ T of a flash block and LT are in a positive correlation relationship. In addition, since the RBER increase Δ RBER of the flash memory block within the preset time Δ T is affected by temperature, the present application also sets a second temperature compensation coefficient f1(T2) to correct the Δ RBER value by the second temperature compensation coefficient f1(T2) so as to reduce the influence of temperature on the Δ RBER value as much as possible.
To sum up, in order to accurately evaluate the increasing speed of the error bit number, the above-mentioned method for eliminating the influence of the DR condition (mainly time and temperature) is: the time effect is reduced by introducing
Such a rate of increase per unit time is used to calculate an estimate; reducing the temperature effect is a computational evaluation by introducing temperature as a compensation factor, as described with reference to figure 4,
expressing the slope of the line in the figure in stages, the higher the temperatureHigh, the slope of the line will be larger, so the slope due to high temperature becomes larger by "pulling back" with temperature as the compensation factor.
It should be noted that FBC and RBER of the flash block have similar meanings, and therefore, RBER mentioned in this embodiment can be expressed by FBC instead, and Δ RBER can also be expressed by Δ FBC instead.
As an alternative embodiment, the step of correcting the unit error bit increase evaluation value according to the average temperature value to obtain the electron leakage trend value of the flash memory block within the preset time includes:
judging whether the average temperature value is greater than a preset standard temperature or not;
if so, then according to
Or
Calculating an electron leakage trend value LT of the flash memory block in a preset time; wherein, the delta t is preset time; Δ RBER is the RBER growth; Δ FBC is the FBC growth; gamma is a second temperature compensation coefficient corresponding to the average temperature value, and gamma is less than 1;
if not, according to
Or
And calculating the electron leakage trend value LT of the flash memory block in a preset time.
Specifically, the calculation relation of the electron leakage tendency value LT of the flash memory block within the preset time Δ t is specifically as follows: when the average temperature value T2 of the flash memory block in the preset time delta T is greater than the preset standard temperature (25 ℃),
or
Gamma is the averageA second temperature compensation coefficient, γ < 1, corresponding to the temperature value T2, such as γ ∈ {0.9,0.8,0.7,0.6 … … } (T2 ═ 40 ℃,50 ℃,60 ℃,70 ℃, … …), i.e., when T2 ═ 40 ℃, γ is 0.9; when T2 is 50 ℃, gamma is 0.8; when T2 is 60 ℃, gamma is 0.7; when T2 is 70 ℃, γ is 0.6 … … (of course, γ may be set to other compensation values, and the RBER increase rate at the reduction standard temperature is considered); when the average temperature value T2 of the flash memory block in the preset time deltat is not greater than the preset standard temperature,
or
As an alternative embodiment, the method for evaluating the wear degree of the flash memory block further comprises:
correspondingly subtracting the current RBER value or FBC value of the flash memory block from the preset error correction capability threshold value RBER 'or FBC' corresponding to the flash memory block to obtain the current RBER increase margin or FBC increase margin of the flash memory block;
and correspondingly dividing the current RBER increase margin or FBC increase margin of the flash memory block by the current RBER increase rate or FBC increase rate of the flash memory block to obtain the current data remaining holding time of the flash memory block.
Further, the nominal reliability of a flash block refers to: data retention time under nominal erase times and error correction capability requirements of the reading device. All flash blocks have a nominal maximum retention time, since RBER increases in proportion to time, and for a sufficiently long time the RBER must exceed the error correction capability threshold (set as RBER') of the reading device.
Based on the method, the current RBER value of the flash memory block is subtracted from the error correction capacity threshold value RBER' corresponding to the flash memory block to obtain the current RBER growth allowance of the flash memory block, and then the current RBER growth allowance of the flash memory block is divided by the current RBER growth rate of the flash memory block to obtain the current data remaining holding time of the flash memory block.
It should be noted that FBC and RBER of the flash block have similar meanings, and therefore, RBER mentioned in this embodiment can be expressed by FBC instead, and similarly, RBER' can also be expressed by FBC instead.
As an alternative embodiment, the method for evaluating the degree of wear of a flash memory block based on an electron leakage level value and an electron leakage tendency value of the flash memory block comprises the following steps:
calculating the abrasion degree Pa of the flash block according to Pa ═ (alpha LL, beta LT); wherein LL is the electronic leakage degree value of the flash memory block; LT is the electron leakage tendency value of the flash memory block; pa is a two-dimensional value of LL and LT; alpha and beta are scaling factors for adjusting the proportional relation of LL and LT; the larger the LL and LT, the more severe the wear of the flash block.
Specifically, although there is a certain degree of correlation between the electron leakage level LL of the flash block and the electron leakage trend value LT of the flash block, it cannot be expressed by simple mathematical expression, and therefore the degree of wear Pa ═ α × LL, β × LT is expressed as a two-dimensional value, as shown in fig. 8.
It should be noted that α and β are scaling factors for adjusting the proportional relationship between LL and LT. Typically, α is 1- β, α, β ∈ {0.1,0.2,0.3,0.4 … … 0.9.9 }; specifically, the size of the scaling factor may be preset for adjusting different design requirements, for example, if some flash memories are located in a place with a higher working temperature, the ratio of the electron leakage trend value LT needs to be increased, and α < β, β is 0.6,0.7, etc. (the ratio may be set according to the temperature); some flash memories are novel QLCs (quad-Level cells, four-layer memory cells, which means that 1 memory Cell can store 4 bits of data), and if the nominal value is small, the electronic leakage Level LL occupation ratio needs to be increased, α > β, α is 0.6,0.7, and the like.
In addition, the flash-based Solid State Disk is generally referred to as SSD (Solid State Disk), and as shown in fig. 9, the Solid State Disk SSD includes: 1) SSD Controller (solid state hard disk Controller): as a control operation unit, managing an SSD internal system; 2) NAND Flash Array (non-volatile Flash memory Array): as storage units, storing data (user data and system data), typically presenting multiple Flash channels (channels, abbreviated as CH), one Channel independently connected to a set of NAND Flash Array, as in fig. 9 CH0/CH1 · · CHx; the NAND Flash (Flash memory) has the characteristics that erasing is required before writing, and the erasing times of each Flash memory are limited; 3) DDR (Double Data Rate, Double Data synchronous Dynamic Random Access Memory)/DRAM (Dynamic Random Access Memory): the cache is used as a cache; 4) connector: for connecting to a host, such as a PC (Personal Computer) or a server; 5) other Peripheral units, such as PMIC (Power Management IC), OSC (crystal Oscillator), JTAG (Joint Test Action Group) Interface, SPI (Serial Peripheral Interface) Interface, Sensor (Sensor), and UART (Universal Asynchronous Receiver/Transmitter) Interface.
It should be noted that the method for evaluating the wear degree of the flash memory block provided in the above embodiments may be implemented by controller programming or hardware logic circuits in the solid state disk based on the flash memory. Specifically, as shown in fig. 10, the Sensor is a temperature Sensor, and is used for acquiring the operating temperature of the flash memory; the DDR is used for storing a real-time maintenance table (the related parameter table related to the calculation formula is maintained and is called as a maintenance table). The solid state hard disk controller includes: 1) CPU (central processing unit): the method is used for running a computer program, such as execution of a calculation formula, statistical recording of the erasing times of a flash memory block, acquisition of external parameters (temperature, RBER and IRBER), acquisition of internal parameters (timing), updating of a maintenance table and the like; 2) I2C controller: the CPU reads a temperature Sensor through an I2C controller to obtain the working temperature of the flash memory; 3) the DDR controller: reading the DDR by the CPU through the DDR controller to obtain a maintenance table; 4) a timer: setting fixed time for periodic operation and recording; 5) RAM (random access Memory): used for storing computer programs, intermediate variables and data; 6) ECC Engine: the system is used for error correction coding and decoding, and simultaneously calculating and outputting RBER and IRBER of the flash memory block; 7) FLC (flash controller): for reading and writing the flash memory.
As shown in fig. 11, is a conceptual diagram of fig. 10, wherein the data storage module: the flash memory comprises a flash memory array and a DDR, and is used for storing EPC counting and maintaining tables and the like; the flash memory attribute acquisition module: reading RBER and IRBER; a time attribute acquisition module: reading time data; a temperature attribute acquisition module: reading temperature data; a calculation module: and calculating the values of Pa, LL and LT based on the relevant parameters.
The specific acquisition principle for the key parameter Δ RBER is as follows: as shown in fig. 12, when Δ t is t1-t0, Δ RBER is obtained by subtracting RBERs of the flash block at times t0 and t1, and therefore RBER of the flash block at time t0 (t0) and RBER of the flash block at time t 1(t1) need to be recorded, and after t1 finishes the calculation, RBER (t1) can be directly used as t0 value in the next stage. Moreover, the RBER of the flash block is recorded (t0), and the RBER can be used for evaluating the reliability of the current data of the flash block, and the data remaining holding time t ═ of the flash block can be predicted through RBER (t0) + Δ RBER/Δ t × < RBER (drt)) (RBER) (drt) -RBER (t 0))/(Δ RBER/Δ t); wherein rber (drt) is a known value, i.e. an error correction capability threshold. If t0 is the time immediately after writing, RBER is equal to IRBER (t 0).
The maintenance table stored for DDR includes at least two tables: 1) pa parameter table: the table contains the relationship between flash blocks and wear Pa and contains the calculated factor values related to Pa, as shown in table 1 below, the Pa parameter table records α, β, EPC, IRBER and RBER (t0), where RBER (t0) also records the timestamp t0 — PTS0 at which this value occurs.
TABLE 1
2) Timestamp thermometer: a temperature table is recorded which is tracked as a time stamp (TimeStamp) according to a fixed time period (e.g. 4 hours) and a power down period (PowerCycle), as shown in table 2 below.
TABLE 2
When Pa of a certain flash memory block is calculated, the following data are obtained according to a flash memory block table look-up: EPC, IRBER and RBER (T0), and also the average temperature value T of RBER (T1) and T0 to T1 of the flash block: and (3) reading the RBER (T1) when necessary, looking up a table to obtain T1 (PTS 1), and calculating the average temperature value T from T0 to T1 so as to calculate Pa of the flash memory block.
Referring to fig. 13, the maintenance flow of the maintenance table is:
step S11: and (4) restoring the maintenance table: and after the power is on, reading the historical maintenance table from the flash memory, updating the power-on period number, and setting and starting a timer according to the set period. It should be noted that, if the power is first powered on, the timestamp temperature table and the Pa parameter table need to be initialized; setting and starting the timer according to a set period specifically means setting and starting a temperature update period timer and an LT update period timer according to the set period; the set period is predetermined by design, and is generally an engineering empirical value.
Step S12: updating the maintenance table: 1) reading and updating the temperature in a temperature updating period; the temperature updating period is triggered by a temperature updating period timer, and a timestamp thermometer is read and updated under the control of a program; 2) when erasing flash memory blocks, updating EPC, and reading and updating IRBER; wherein, updating EPC is that 1 is added to the EPC of the flash memory block which is erased and written correspondingly when the flash memory block is erased and written once; reading the IRBER is to read the IRBER of the flash memory block immediately after the flash memory block is written into the Pa parameter table; 3) reading the corresponding flash block RBER (t1), calculating and updating LT, and updating RBER (t0) in LT updating period; wherein the LT update period is triggered by an LT update period timer; reading the RBER of the corresponding flash block (t1) is accomplished by the apparatus shown in fig. 10 at time t 1; updating LT and RBER (t0) comprises calculating LT according to a calculation formula, updating the obtained value to Pa parameter table, and updating RBER (t1) as new RBER (t0) to Pa parameter table; 4) when any one of the values 2) and 3) occurs, calculating and updating Pa, specifically calculating Pa according to a calculation formula, and updating the obtained value to a Pa parameter table.
Step S13: and (4) storing a maintenance table: when a power loss occurs, the real-time maintenance table is written to a non-volatile memory (flash memory). It will be appreciated that after the real-time maintenance table is written to the non-volatile memory, the table acts as a historical maintenance table for the next power-up.
The application also provides a solid state disk, including:
flashing;
a controller for implementing the steps of any of the above described methods for assessing flash block wear when executing the computer program.
For introduction of the solid state disk provided in the present application, please refer to the above embodiments of the method for evaluating the wear level, which are not described herein again.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method for evaluating wear of a flash memory block, comprising:
acquiring an electron leakage degree value of the flash memory block immediately after electrons are injected;
acquiring an electron leakage trend value of the flash memory block injected with electrons;
and evaluating the abrasion degree of the flash memory block according to the electronic leakage degree value and the electronic leakage trend value of the flash memory block.
2. The method of assessing the wear of a flash block according to claim 1, wherein obtaining an electron leakage level value of the flash block immediately after injecting electrons comprises:
acquiring the erasing times of the flash memory block, and acquiring an initial error bit evaluation value of the flash memory block just after the electrons are injected;
determining an electron leakage degree value of the flash memory block just after the electrons are injected according to the erasing times and the initial error bit evaluation value; wherein the number of erasures and the initial error bit evaluation value have a positive correlation with the electron leakage level value.
3. The method of evaluating the degree of wear of a flash block according to claim 2, wherein obtaining an initial error bit evaluation value of the flash block immediately after the injection of electrons comprises:
acquiring an IRBER value or an IFBC value of the flash memory block just after the electrons are injected, and acquiring a temperature value of the flash memory block just after the electrons are injected;
and correspondingly correcting the IRBER value or the IFBC value according to the temperature value to obtain an IRBER correction value or an IFBC correction value of the flash memory block just after the electrons are injected, and using the IRBER correction value or the IFBC correction value as the initial error bit evaluation value.
4. The method of evaluating the degree of wear of a flash memory block according to claim 3, wherein determining the electron leakage level value of the flash memory block immediately after injecting electrons from the number of erasures and the initial error bit evaluation value comprises:
calculating an electron leakage degree value LL of the flash block just after the electrons are injected according to LL ═ EPC δ IRBER or LL ═ EPC δ IFBC;
wherein EPC is the erasing times; δ IRBER is the IRBER correction value; δ IFBC is the IFBC correction value; and delta is a first temperature compensation coefficient corresponding to the temperature value.
5. The method of evaluating the degree of wear of a flash memory block according to claim 1, wherein obtaining an electron leakage tendency value of the flash memory block into which electrons have been injected, comprises:
acquiring a unit error bit increase evaluation value of the flash memory block injected with electrons in a preset time, and acquiring an average temperature value of the flash memory block in the preset time;
and correcting the unit error bit increase evaluation value according to the average temperature value to obtain an electronic leakage trend value of the flash memory block in the preset time.
6. The method for evaluating the degree of wear of a flash memory block according to claim 5, wherein obtaining a unit error bit growth evaluation value of the flash memory block into which electrons have been injected for a preset time comprises:
acquiring the RBER growth amount or FBC growth amount of the flash memory block injected with electrons in a preset time;
dividing the RBER growth amount or the FBC growth amount by the preset time to correspondingly obtain the RBER growth rate or the FBC growth rate of the flash memory block in unit time, and taking the RBER growth rate or the FBC growth rate as the unit error bit growth evaluation value.
7. The method for evaluating the wear of a flash memory block according to claim 6, wherein the correcting the unit error bit increase evaluation value according to the average temperature value to obtain the trend value of electron leakage of the flash memory block in the preset time comprises:
judging whether the average temperature value is greater than a preset standard temperature or not;
if so, then according to
Or
Calculating an electron leakage trend value LT of the flash memory block in the preset time; wherein Δ t is the preset time; Δ RBER is the RBER growth; Δ FBC is the FBC growth;γa second temperature compensation coefficient corresponding to the average temperature value, wherein gamma is less than 1;
if not, according to
Or
And calculating an electron leakage trend value LT of the flash memory block in the preset time.
8. The method of assessing flash block wear as claimed in claim 6, wherein said method of assessing flash block wear further comprises:
correspondingly subtracting the current RBER value or FBC value of the flash memory block from the preset error correction capability threshold value RBER 'or FBC' corresponding to the flash memory block to obtain the current RBER increase margin or FBC increase margin of the flash memory block;
and correspondingly dividing the current RBER increase margin or FBC increase margin of the flash memory block by the current RBER increase rate or FBC increase rate of the flash memory block to obtain the current data remaining holding time of the flash memory block.
9. The method for evaluating the degree of wear of a flash memory block according to any one of claims 1 to 8, wherein evaluating the degree of wear of the flash memory block based on the electron leakage level value and the electron leakage tendency value of the flash memory block comprises:
calculating the abrasion degree Pa of the flash block according to Pa ═ (alpha LL, beta LT); wherein LL is an electron leakage degree value of the flash memory block; LT is an electron leakage tendency value of the flash memory block; pa is a two-dimensional value of LL and LT; alpha and beta are scaling factors for adjusting the proportional relation of LL and LT; the larger the LL and LT, the more severe the wear of the flash block.
10. A solid state disk, comprising:
flashing;
a controller for implementing the steps of the method of assessing flash block wear according to any one of claims 1 to 9 when executing a stored computer program.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111064333.7A CN113793636B (en) | 2021-09-10 | 2021-09-10 | Flash memory block abrasion degree evaluation method and solid state disk |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111064333.7A CN113793636B (en) | 2021-09-10 | 2021-09-10 | Flash memory block abrasion degree evaluation method and solid state disk |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113793636A true CN113793636A (en) | 2021-12-14 |
| CN113793636B CN113793636B (en) | 2024-03-19 |
Family
ID=79183255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111064333.7A Active CN113793636B (en) | 2021-09-10 | 2021-09-10 | Flash memory block abrasion degree evaluation method and solid state disk |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113793636B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115472203A (en) * | 2022-06-30 | 2022-12-13 | 上海江波龙数字技术有限公司 | Flash memory wear frequency prediction method and device and storage medium |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090003058A1 (en) * | 2007-06-28 | 2009-01-01 | Samsung Electronics Co., Ltd. | Flash memory device and method for adjusting read voltage of flash memory device |
| JP2012212312A (en) * | 2011-03-31 | 2012-11-01 | Pioneer Electronic Corp | Memory control device and memory control method |
| US20170269994A1 (en) * | 2016-03-21 | 2017-09-21 | NandEXT S.r.l. | Method for decoding bits in a solid state drive, and related solid state drive |
| CN109285583A (en) * | 2018-09-11 | 2019-01-29 | 中国科学院空间应用工程与技术中心 | Nand flash memory solid state hard disk space environment effect test macro and test method |
| CN111078123A (en) * | 2018-10-19 | 2020-04-28 | 浙江宇视科技有限公司 | Method and device for evaluating wear degree of flash memory block |
| CN111143146A (en) * | 2019-12-26 | 2020-05-12 | 深圳大普微电子科技有限公司 | Health state prediction method and system of storage device |
-
2021
- 2021-09-10 CN CN202111064333.7A patent/CN113793636B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090003058A1 (en) * | 2007-06-28 | 2009-01-01 | Samsung Electronics Co., Ltd. | Flash memory device and method for adjusting read voltage of flash memory device |
| JP2012212312A (en) * | 2011-03-31 | 2012-11-01 | Pioneer Electronic Corp | Memory control device and memory control method |
| US20170269994A1 (en) * | 2016-03-21 | 2017-09-21 | NandEXT S.r.l. | Method for decoding bits in a solid state drive, and related solid state drive |
| CN109285583A (en) * | 2018-09-11 | 2019-01-29 | 中国科学院空间应用工程与技术中心 | Nand flash memory solid state hard disk space environment effect test macro and test method |
| CN111078123A (en) * | 2018-10-19 | 2020-04-28 | 浙江宇视科技有限公司 | Method and device for evaluating wear degree of flash memory block |
| CN111143146A (en) * | 2019-12-26 | 2020-05-12 | 深圳大普微电子科技有限公司 | Health state prediction method and system of storage device |
Non-Patent Citations (2)
| Title |
|---|
| JIANWEI LIAO ET AL.: "Adaptive Wear-Leveling in Flash-Based Memory", 《IEEE COMPUTER ARCHITECTURE LETTERS 》, vol. 14, no. 1, XP011585130, DOI: 10.1109/LCA.2014.2329871 * |
| 孙翠锋 等: "闪存技术发展趋势及在数据中心的应用", 《互联网天地》, vol. 1, no. 12 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115472203A (en) * | 2022-06-30 | 2022-12-13 | 上海江波龙数字技术有限公司 | Flash memory wear frequency prediction method and device and storage medium |
| CN115472203B (en) * | 2022-06-30 | 2023-11-14 | 上海江波龙数字技术有限公司 | Flash memory wear number prediction method, device and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113793636B (en) | 2024-03-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9355024B2 (en) | Systems and methods for nonvolatile memory performance throttling | |
| US10062442B2 (en) | Method for managing data blocks and method of data management for data storage device | |
| CN105556610B (en) | Data storage systems with dynamic read threshold mechanism and the method for operating it | |
| US11593261B2 (en) | Memory device with dynamic cache management | |
| US7596656B2 (en) | Memory cards with end of life recovery and resizing | |
| US8248856B2 (en) | Predictive read channel configuration | |
| TWI428739B (en) | End of life recovery and resizing of memory cards | |
| US20140208174A1 (en) | Storage control system with data management mechanism and method of operation thereof | |
| US9349489B2 (en) | Systems and methods to update reference voltages in response to data retention in non-volatile memory | |
| US10332613B1 (en) | Nonvolatile memory system with retention monitor | |
| US20140115428A1 (en) | Systems and methods for proactively refreshing nonvolatile memory | |
| CN113793636A (en) | Flash memory block abrasion degree evaluation method and solid state disk | |
| US10650879B2 (en) | Device and method for controlling refresh cycles of non-volatile memories | |
| US11748013B2 (en) | Grouping blocks based on power cycle and power on time | |
| Wei et al. | A page-granularity wear-leveling (PGWL) strategy for NAND flash memory-based sink nodes in wireless sensor networks | |
| Seif et al. | Refresh frequency reduction of data stored in SSDs based on A-timer and timestamps | |
| CN113782082B (en) | Two-dimensional wear balancing method for flash memory and solid state disk | |
| US11705192B2 (en) | Managing read level voltage offsets for low threshold voltage offset bin placements | |
| TW201933366A (en) | Method and device for adjusting a plurality of the threshold voltages of a non-volatile memory device | |
| US20230315312A1 (en) | Memory system and method | |
| Olson | NAND flash memory reliability in embedded computer systems | |
| CN117406910A (en) | Data storage method, storage device and computer readable storage device | |
| CN113383387A (en) | Memory device and management method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |