CN113793636B - Flash memory block abrasion degree evaluation method and solid state disk - Google Patents
Flash memory block abrasion degree evaluation method and solid state disk Download PDFInfo
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- 238000005299 abrasion Methods 0.000 title claims abstract description 30
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Abstract
The invention discloses an evaluation method of wear degree of a flash memory block and a solid state disk, which are used for acquiring an electron leakage degree value of the flash memory block immediately after electron injection; acquiring an electron leakage trend value of a flash memory block into which electrons are injected; and evaluating the abrasion degree of the flash memory block according to the electron leakage degree value and the electron leakage trend value of the flash memory block. Therefore, the wear degree of the flash memory block is estimated from two dimensions of the electron leakage degree value and the electron leakage trend value of the flash memory block, compared with the single erasing frequency serving as a wear estimation index, the wear degree is estimated from two dimensions more comprehensively and accurately, the wear balancing effect is better, and the overall service life of the solid state disk is further prolonged.
Description
Technical Field
The present invention relates to the field of solid state storage, and in particular, to a method for evaluating wear resistance of a flash memory block and a solid state disk.
Background
The flash memory includes a plurality of flash blocks (blocks), each of which includes a plurality of flash pages (pages). The flash block is a basic unit of flash erase, and when one flash page is written with data, a new write operation can be performed only after the erase operation is performed on the flash block.
Currently, for a solid state disk based on flash memory (a solid state disk adopting a flash memory chip as a storage medium), wear balance of each flash memory block is a key factor for guaranteeing storage reliability of the solid state disk. In order to realize the balanced control of the abrasion of each flash memory block, the abrasion degree of each flash memory block needs to be accurately estimated, which is also helpful for estimating the service life of the solid state disk based on the abrasion degree of each flash memory block.
In the prior art, the wear level of a flash block is generally estimated based on the number of erasures of the flash block, and the more the number of erasures of the flash block is, the more serious the wear condition of the flash block is. However, only a single erasing frequency is not comprehensive and accurate enough as a wear evaluation index, so that the wear balance effect is affected, and the overall service life of the solid state disk is further affected.
Therefore, how to provide a solution to the above technical problem is a problem that a person skilled in the art needs to solve at present.
Disclosure of Invention
The invention aims to provide an evaluation method for the abrasion degree of a flash memory block and a solid state disk, wherein the abrasion degree of the flash memory block is evaluated from two dimensions of an electronic leakage degree value and an electronic leakage trend value of the flash memory block, compared with the single erasure frequency serving as an abrasion evaluation index, the abrasion degree is evaluated from two dimensions more comprehensively and accurately, so that the abrasion balance effect is better, and the overall service life of the solid state disk is further prolonged.
In order to solve the above technical problems, the present invention provides a method for evaluating wear degree of a flash memory block, including:
acquiring an electron leakage degree value of a flash memory block immediately after electron injection;
acquiring an electron leakage trend value of the flash memory block into which electrons are injected;
and evaluating the abrasion degree of the flash memory block according to the electron leakage degree value and the electron leakage trend value of the flash memory block.
Preferably, acquiring the value of the electron leakage degree of the flash memory block immediately after the electron injection includes:
acquiring the erasing times of the flash memory block, and acquiring an initial error bit evaluation value of the flash memory block immediately after the electron injection;
determining an electron leakage degree value of the flash memory block immediately after electron injection according to the erasing times and the initial error bit evaluation value; wherein a positive correlation is made between the erasure number and the initial erroneous bit evaluation value and the electron leakage degree value.
Preferably, obtaining an initial error bit evaluation value of the flash memory block immediately after the electron injection includes:
obtaining an IRBER value or an IFBC value of the flash memory block immediately after the electrons are injected, and obtaining a temperature value of the flash memory block immediately after the electrons are injected;
and correcting the IRBER value or the IFBC value according to the temperature value, obtaining an IRBER corrected value or an IFBC corrected value of the flash memory block immediately after the electrons are injected, and taking the IRBER corrected value or the IFBC corrected value as the initial error bit evaluation value.
Preferably, determining the value of the electron leakage degree of the flash memory block immediately after the electron injection according to the erase count and the initial error bit evaluation value includes:
calculating an electron leakage degree value LL of the flash memory block immediately after electron injection according to LL=EPC=delta×IRBER or LL=EPC=delta×IFBC;
wherein EPC is the erase count; delta is IRBER corrected value of IRBER; δ is the IFBC correction value; and delta is a first temperature compensation coefficient corresponding to the temperature value.
Preferably, acquiring the electron leakage trend value of the flash memory block into which electrons have been injected includes:
acquiring a unit error bit increase evaluation value of the flash memory block with injected electrons within a preset time, and acquiring an average temperature value of the flash memory block within the preset time;
and correcting the unit error bit increase evaluation value according to the average temperature value to obtain an electron leakage trend value of the flash memory block in the preset time.
Preferably, the obtaining the unit error bit growth evaluation value of the flash memory block injected with electrons in a preset time includes:
acquiring RBER increment or FBC increment of the flash memory block with injected electrons in a preset time;
dividing the RBER increment or the FBC increment by the preset time to correspondingly obtain the RBER increment rate or the FBC increment rate of the flash memory block in unit time, and taking the RBER increment rate or the FBC increment rate as the unit error bit increment evaluation value.
Preferably, the correcting the unit error bit increase evaluation value according to the average temperature value to obtain an electronic leakage trend value of the flash memory block in the preset time includes:
judging whether the average temperature value is larger than a preset standard temperature or not;
if yes, then according toOr->Calculating an electron leakage trend value LT of the flash memory block in the preset time; wherein Δt is the preset time; Δrber is the RBER increase amount; Δfbc is the FBC increment; γ a second temperature compensation coefficient corresponding to the average temperature value, wherein gamma is smaller than 1;
if not, according toOr->And calculating an electron leakage trend value LT of the flash memory block in the preset time.
Preferably, the method for evaluating the wear degree of the flash memory block further comprises:
subtracting the current RBER value or the current FBC value of the flash memory block from a preset error correction capability threshold RBER 'or a preset FBC' corresponding to the flash memory block to obtain the current RBER increase allowance or the current FBC increase allowance of the flash memory block;
and dividing the current RBER increase allowance or FBC increase allowance of the flash memory block by the current RBER increase rate or FBC increase rate of the flash memory block to obtain the current data remaining holding time of the flash memory block.
Preferably, evaluating the wear degree of the flash memory block according to the electron leakage degree value and the electron leakage trend value of the flash memory block includes:
calculating the wear degree Pa of the flash memory block according to pa= (α×ll, β×lt); wherein LL is an electron leakage level value of the flash memory block; LT is the electron leakage trend value of the flash memory block; pa is two-dimensional values of LL and LT; alpha and beta are scale factors for adjusting the proportional relationship of LL and LT; the larger LL and LT, the more severe the wear of the flash blocks.
In order to solve the technical problem, the invention also provides a solid state disk, which comprises:
a flash memory;
and a controller for implementing any one of the above-described methods for evaluating the wear level of the flash memory blocks when executing the computer program.
The invention provides an evaluation method of wear degree of a flash memory block, which comprises the steps of obtaining an electron leakage degree value of the flash memory block immediately after electron injection; acquiring an electron leakage trend value of a flash memory block into which electrons are injected; and evaluating the abrasion degree of the flash memory block according to the electron leakage degree value and the electron leakage trend value of the flash memory block. Therefore, the wear degree of the flash memory block is estimated from two dimensions of the electron leakage degree value and the electron leakage trend value of the flash memory block, compared with the single erasing frequency serving as a wear estimation index, the wear degree is estimated from two dimensions more comprehensively and accurately, the wear balancing effect is better, and the overall service life of the solid state disk is further prolonged.
The invention also provides a solid state disk which has the same beneficial effects as the abrasion degree evaluation method.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for evaluating wear level of a flash memory block according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating an electron leakage of a memory cell according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of RBER comparison of different flash memory blocks under the same DR condition and EPC according to an embodiment of the present invention;
FIG. 4 is a schematic diagram showing the relationship between DR time and RBER of the same flash memory block under the same EPC and different temperatures according to the embodiment of the present invention;
FIG. 5 is a schematic diagram of RBER comparison of different flash memory blocks under the same EPC and different DR conditions according to an embodiment of the present invention;
FIG. 6 is a RBER comparison chart of a flash block A and a flash block B under different DR conditions according to an embodiment of the present invention;
FIG. 7 is a schematic diagram showing a relationship between DR time and RBER of a flash memory block according to an embodiment of the present invention;
FIG. 8 is a two-dimensional graph of wear level of a flash memory block according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a solid state disk SSD according to an embodiment of the invention;
fig. 10 is a schematic diagram of a specific structure of a solid state disk SSD according to an embodiment of the invention;
fig. 11 is a conceptual diagram of a solid state disk SSD according to an embodiment of the invention;
FIG. 12 is a diagram of an embodiment of the present invention obtaining a schematic diagram of a seed delta RBER parameter;
fig. 13 is a maintenance flow chart of a maintenance table according to an embodiment of the present invention.
Detailed Description
The invention provides a method for evaluating the abrasion degree of a flash memory block and a solid state disk, wherein the abrasion degree of the flash memory block is evaluated from two dimensions of an electronic leakage degree value and an electronic leakage trend value of the flash memory block, compared with the single erasing frequency serving as an abrasion evaluation index, the abrasion degree is evaluated from two dimensions more comprehensively and accurately, so that the abrasion balancing effect is better, and the overall service life of the solid state disk is further prolonged.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a flowchart of a method for evaluating wear level of a flash memory block according to an embodiment of the invention.
The method for evaluating the abrasion degree of the flash memory block comprises the following steps:
step S1: and acquiring an electron leakage degree value of the flash memory block immediately after electron injection.
Step S2: and acquiring an electron leakage trend value of the flash memory block into which electrons are injected.
Step S3: and evaluating the abrasion degree of the flash memory block according to the electron leakage degree value and the electron leakage trend value of the flash memory block.
Specifically, the flash memory is a non-volatile storage medium, which is widely used in various storage occasions, and is generally classified into SLC (Single-Level Cell, single-layer Cell, 1 Cell can store 1 bit of data, 0 and 1, two cases), MLC (Multi-Level Cell, double-layer Cell, 1 Cell can store 2 bits of data, four cases (11, 10, 01, 00), TLC (Triple-Level Cell, three-layer Cell, 1 Cell can store 3 bits of data, and 8 cases (000, 001, 010, 011, 100, 101, 110, 111)) in terms of its architecture.
For SLC flash, each flash page in a flash block is used to store a single bit of data. For MLC flash, each data block contains two major classes of pages, called MSB (Most Significant Bit ) page and LSB (Least Significant Bit, least significant bit) page, respectively, the MSB page being used to store the high bit of the double bits, the LSB page being used to store the low bit of the double bits; that is, the MSB page and the LSB page are a pair of pages, and the upper bit in the MSB page and the lower bit corresponding thereto in the LSB page can constitute the complete double bit. For TLC flash memory, each data block contains three major types of pages, called MSB (Most Significant Bit ) page, CSB (Central Significant Bit, central significant bit) page, and LSB (Least Significant Bit ) page, respectively, the MSB page being used to store the upper bits of the three bits, the CSB page being used to store the middle bits of the three bits, and the LSB page being used to store the lower bits of the three bits; that is, the MSB page, the CSB page and the LSB page are a pair of pages, and the upper bit in the MSB page, the middle bit corresponding to the CSB page and the lower bit corresponding to the LSB page can form a complete three-bit.
Flash memory is actually a memory that stores electrons in one memory Cell (Cell), and the number of stored electrons is presented as a voltage value to express a stored bit value by the voltage value. Flash memory errors are mainly caused by the fact that the voltage of a storage unit changes due to electronic leakage, so that read misjudgment is caused, namely, an error bit value is generated, and if the number of the error bits is larger than the error correction capability of a reading device, then the flash memory is not available.
And wear is a major factor affecting the electronic storage capacity of the memory cell. For ease of understanding, as shown in fig. 2, the memory cell corresponds to a room with a door, the writing operation is to inject electrons, and the goal is to inject 100 electrons, but due to wear and other reasons, only 90 electrons are actually injected (for example, TLC, where 3 bits of the memory cell are read and 1 bit error appears on the outside), and over time, electrons escape, and only 80 electrons remain during the reading (where 3 bits of the memory cell are read and 2 bit errors appear on the outside). It will be appreciated that the wear level of a flash block can be evaluated in two dimensions, the electron leakage level value and the electron leakage trend value of the flash block; the electronic leakage degree value of the flash memory block represents an initial state (a difference between the actual injection quantity and the expected injection quantity) of the flash memory block just after the electrons are injected, and the initial state is externally represented as an initial error bit number of the flash memory block just after the data are written; the electron leakage trend value of the flash memory block characterizes the state change (electron escape speed) of the flash memory block injected with electrons, and is externally represented by the increasing number of error bits based on the initial number of error bits.
Based on the above, the present application obtains the electron leakage degree value of the flash memory block immediately after electron injection (the electron leakage degree value corresponding to this time can be obtained after electron injection each time), and obtains the electron leakage trend value of the flash memory block into which electron has been injected, and then evaluates the abrasion degree of the flash memory block according to the electron leakage degree value and the electron leakage trend value of the flash memory block (the larger the electron leakage degree value and the electron leakage trend value of the flash memory block, the more serious the abrasion condition of the flash memory block is, once the electron leakage degree value and the electron leakage trend value of the flash memory block are changed, the abrasion condition of the flash memory block is also changed accordingly), thereby realizing the balanced control of the abrasion degree of each flash memory block in the solid state hard disk.
Therefore, the wear degree of the flash memory block is estimated from two dimensions of the electron leakage degree value and the electron leakage trend value of the flash memory block, compared with the single erasing frequency serving as a wear estimation index, the wear degree is estimated from two dimensions more comprehensively and accurately, the wear balancing effect is better, and the overall service life of the solid state disk is further prolonged.
Based on the above embodiments:
as an alternative embodiment, obtaining the value of the electron leakage degree of the flash memory block immediately after the electron injection includes:
acquiring the erasing times of a flash memory block, and acquiring an initial error bit evaluation value of the flash memory block immediately after electron injection;
determining an electron leakage degree value of the flash memory block immediately after electron injection according to the erasing times and the initial error bit evaluation value; wherein, the erasure number and the initial error bit evaluation value and the electron leakage degree value have positive correlation.
Specifically, considering that the number of times of erasure of the flash memory block and the electron leakage degree value of the flash memory block just after electron injection are in positive correlation, namely that the larger the number of times of erasure of the flash memory block is, the larger the electron leakage degree value of the flash memory block just after electron injection is described; the method comprises the steps of obtaining the erasing times of the flash memory block, obtaining the initial error bit evaluation value of the flash memory block immediately after electron injection, and then determining the electron leakage degree value of the flash memory block immediately after electron injection according to the erasing times of the flash memory block and the initial error bit evaluation value of the flash memory block immediately after electron injection.
As an alternative embodiment, obtaining an initial erroneous bit evaluation value of a flash block immediately after injection of electrons includes:
obtaining an IRBER value or an IFBC value of the flash memory block immediately after the electrons are injected, and obtaining a temperature value of the flash memory block immediately after the electrons are injected;
and correcting the IRBER value or the IFBC value according to the temperature value to obtain an IRBER corrected value or an IFBC corrected value of the flash memory block immediately after the electrons are injected, and taking the IRBER corrected value or the IFBC corrected value as an initial error bit evaluation value.
Specifically, as shown in fig. 3, RBER (Raw Bit Error Rate, original bit error rate) of different flash blocks is different under the same DR (Data Retention) condition and EPC (Erase-Program Cycles). For example, under the nominal EPC, the RBER of the flash blocks B0, B1, B2 are different, so it is feasible to introduce RBER as a wear-assessment index: RBER embodies wear conditions for different flash memory blocks.
Research into flash memory characteristics has found that RBER is strongly correlated to DR conditions (including, but not limited to, storage time and temperature) in practical applications. As shown in fig. 4, the relationship between DR time (T) and RBER is shown for the same flash memory block at the same EPC and different temperatures (T). As can be seen from the horizontal axis of fig. 4, when the DR time of the flash block is longer, the RBER of the flash block is larger, such as RBER (T0, T2) > RBER (T0, T1) > RBER (T0, T0) at the same temperature T0. It can be seen from the vertical axis of fig. 4 that the higher the temperature of the flash block, the larger the RBER of the flash block, and the shorter the DR time, for example, at the same time T0, RBER (T2, T0) > RBER (T1, T0) > RBER (T0, T0).
It can be seen that if RBER is used as an abrasion assessment indicator, the effect of DR conditions must be considered. As shown in fig. 5, from the perspective of properties RBER (BlockB) > RBER (BlockA), but under different DR conditions (different temperatures and different times), different flash blocks, read RBER and then compare: RBER (BlockB, T0, T2) > RBER (BlockA, T2, T0) > RBER (BlockB, T0, T0) > RBER (BlockA, T0, T0), clearly a completely different conclusion. For example, as shown in fig. 6, after 1 day of writing data in flash block a, flash block B has data written therein, and the flash block a is at a higher temperature (50 ℃) within 1 day of writing data, and the flash block B is at normal temperature (25 ℃) within 1 day of writing data, at this time, the RBER (BlockA) of flash block a is more likely to be RBER (BlockA) > RBER (BlockB) than the RBER (BlockB) of flash block B. Thus, if RBER is used as an abrasion assessment indicator, it is necessary to extract values that are not affected by DR conditions, or are comparable and applicable based on the same DR conditions, while the impact of DR conditions is time-limited: the effect of the DR condition is zeroed after re-erasure. As shown in fig. 7 (the horizontal axis is data retention time, the vertical axis is RBER; there is an IRBER (Initial Raw Bit Error Rate, initial raw error bit rate) after data writing, and as time increases, the error bit increases, namely, is represented by RBER increase, the increase curve of which is affected by temperature, the graph is not expressed, and the temperature part is referred to in fig. 4), and under the same EPC, the IRBER is introduced, so that the influence of DR condition can be greatly eliminated, and the wear base degree of the flash memory block can be accurately represented.
Based on the above, the method and the device acquire the IRBER value (initial RBER value after data is just written) of the flash memory block just after the electrons are injected, acquire the temperature value T1 of the flash memory block just after the electrons are injected, and then correspondingly correct the IRBER value (reduce temperature influence) according to the temperature value T1 to obtain the IRBER correction value of the flash memory block just after the electrons are injected, wherein the IRBER correction value of the flash memory block just after the electrons are the initial error bit evaluation value of the flash memory block just after the electrons are injected.
The calculation relation of the electron Leakage Level value LL (Leakage Level) of any flash block immediately after electron injection can be expressed as: ll=f (EPC) ×f (f 1 (T1) ×irber), which indicates that the electronic leakage level value LL is a functional relationship between EPC and IRBER, it should be noted that EPC and IRBER of a flash block have a positive correlation with LL. In addition, since the IRBER value of the flash memory block immediately after electron injection is affected by temperature, the present application further sets the first temperature compensation coefficient f1 (T1) to correct the IRBER value by the first temperature compensation coefficient f1 (T1), thereby reducing the influence of temperature on the IRBER value as much as possible.
It should be noted that, the FBC (Failure Bit Counter, number of error bits) and RBER of the flash memory block have similar meanings, and the relationship between the FBC and RBER may be expressed as fbc=rber×bitcnt, where BitCNT is the total number of bits of the flash memory block. Therefore, all RBER mentioned in this embodiment can be expressed by FBC instead, and IRBER can be expressed by IFBC (Initial Failure Bit Counter, initial number of error bits) instead.
As an alternative embodiment, determining the value of the electron leakage degree of the flash memory block immediately after the electron injection according to the number of erasures and the initial error bit evaluation value includes:
calculating an electron leakage degree value LL of the flash memory block immediately after electron injection according to LL=EPC=delta×IRBER or LL=EPC=delta×IFBC;
wherein EPC is the number of erasures; delta IRBER is IRBER correction value; δ is IFBC correction value; delta is a first temperature compensation coefficient corresponding to the temperature value.
Specifically, the calculation relation of the electron leakage degree value LL of the flash memory block immediately after electron injection is specifically: ll=epc δ IRBER or ll=epc δ IFBC; wherein δ is a first temperature compensation coefficient corresponding to the temperature value T1, for example δ e {1.1,1.2,1.3,1.4 … … } (t1=40 ℃,50 ℃,60 ℃,70 ℃, … …), i.e. δ is 1.1 when t1=40 ℃; t1=50 ℃, δ is 1.2; t1=60 ℃, δ is 1.3; t1=70 ℃, δ is 1.4. 1.4 … … (of course, δ may be set by other compensation values according to actual requirements).
The calculation relation of the electron leakage level value LL of the flash memory block immediately after the electron injection may be: ll=epc+k (δ IRBER), k being a preset coefficient; ll=i epc+j (δ IRBER), i, j being preset coefficients, any relational expression indicating positive correlation between EPC, IRBER (or IFBC) and LL may be considered.
As an alternative embodiment, acquiring the electron leakage trend value of the flash memory block into which electrons have been injected includes:
acquiring a unit error bit increase evaluation value of the flash memory block injected with electrons in a preset time, and acquiring an average temperature value of the flash memory block in the preset time;
and correcting the unit error bit increase evaluation value according to the average temperature value to obtain an electronic leakage trend value of the flash memory block in a preset time.
Specifically, the electron leakage trend value of the flash memory block represents the electron escape speed, and as electrons in the flash memory block escape, more and more error bits occur, so that the electron escape speed of the flash memory block in the preset time can be represented by the unit error bit increase evaluation value of the flash memory block in the preset time.
Based on the above, the present application obtains the unit error bit growth evaluation value of the flash memory block injected with electrons in the preset time, and in order to reduce the temperature influence, the present application also obtains the average temperature value T2 of the flash memory block in the preset time, and then corrects the unit error bit growth evaluation value of the flash memory block in the preset time according to the average temperature value T2 of the flash memory block in the preset time, where the correction result is the electron leakage trend value of the flash memory block in the preset time.
As an alternative embodiment, obtaining an evaluation value of unit error bit growth of the flash memory block into which electrons have been injected in a preset time includes:
acquiring RBER increment or FBC increment of the flash memory block injected with electrons in a preset time;
dividing the RBER increment or the FBC increment by the preset time to obtain the RBER increment rate or the FBC increment rate of the flash memory block in unit time, and taking the RBER increment rate or the FBC increment rate as a unit error bit increment evaluation value.
Specifically, the unit error bit growth evaluation value of the flash memory block in the preset time may be expressed as:the delta RBER is the RBER increment of the flash memory blocks within the preset time delta t (the speed accuracy of the delta RBER depends on the value of delta t, and the delta t values among the flash memory blocks keep consistent, the specific value of the delta RBER is determined by the service type of a specific embodiment, such as 24 hours and even 30 days, which can be considered), namely the RBER increment of the flash memory blocks injected with electrons within the preset time delta t is obtained, and the RBER increment is divided by the preset time delta t to obtainThe RBER growth rate of the flash memory block in unit time is the unit error bit growth evaluation value of the flash memory block in preset time.
The calculation relation of the electron Leakage Trend value LT (Leakage Trend) of any flash block within the preset time Δt can be expressed as follows: lt=f (Δrber/Δt) ×f2 (T2), which indicates that the electron leakage trend LT is a function of Δrber/Δt (RBER growth rate), it should be noted that the Δrber/Δt of the flash memory block has a positive correlation with LT. In addition, since the RBER increment ΔRBER of the flash memory block within the preset time Δt is affected by temperature, the present application further sets the second temperature compensation coefficient f1 (T2) to correct the ΔRBER value through the second temperature compensation coefficient f1 (T2), thereby reducing the influence of temperature on the ΔRBER value as much as possible.
To sum up, in order to accurately evaluate the increase speed of the number of erroneous bits, the above-mentioned way of excluding the influence of DR conditions (mainly time and temperature) is as follows: reducing the time effect is by introducingSuch rate increase per unit time to calculate an estimate; the temperature influence is reduced by introducing temperature as compensation factor to calculate the evaluation as shown in FIG. 4,/for example>The gradient of the line is expressed in the graph in a stepwise manner, and the higher the temperature is, the larger the gradient of the line is, so that the gradient of the line is increased by using the temperature as a compensation coefficient factor for 'pulling back'.
It should be noted that FBC and RBER of the flash memory block have similar meanings, and therefore, all RBER mentioned in this embodiment may be expressed by using FBC instead, and Δrber may be expressed by using Δfbc instead.
As an alternative embodiment, correcting the unit error bit increase evaluation value according to the average temperature value to obtain an electronic leakage trend value of the flash memory block in a preset time, including:
judging whether the average temperature value is larger than a preset standard temperature or not;
if yes, then according toOr->Calculating an electron leakage trend value LT of the flash memory block in a preset time; wherein Δt is a preset time; Δrber is the RBER increase; Δfbc is the FBC increment; gamma is a second temperature compensation coefficient corresponding to the average temperature value, and gamma is smaller than 1;
if not, according toOr->And calculating an electron leakage trend value LT of the flash memory block in a preset time.
Specifically, the calculation relation of the electron leakage tendency value LT of the flash memory block within the preset time Δt is specifically: when the average temperature value T2 of the flash memory block within the preset time Δt is greater than the preset standard temperature (25 ℃),or (b)Gamma is a second temperature compensation coefficient corresponding to the average temperature value T2, and gamma is less than 1, if gamma is {0.9,0.8,0.7,0.6 … … } (T2=40 ℃,50 ℃,60 ℃,70 ℃ … …), namely, when T2=40 ℃, gamma is 0.9; at t2=50 ℃, γ takes 0.8; t2=60 ℃, γ is 0.7; when t2=70 ℃, γ takes 0.6 … … (of course, γ may be set with other compensation values, as long as it meets the RBER acceleration at the reduction standard temperature; when the average temperature value T2 of the flash memory block within the preset time delta T is not more than the preset standard temperature, the flash memory block is in the +.>Or->
As an alternative embodiment, the method for evaluating the wear degree of the flash memory block further includes:
subtracting the current RBER value or the current FBC value of the flash memory block from a preset error correction capability threshold RBER 'or a preset FBC' corresponding to the flash memory block to obtain the current RBER increase allowance or the current FBC increase allowance of the flash memory block;
and dividing the current RBER increase allowance or FBC increase allowance of the flash memory block by the current RBER increase rate or FBC increase rate of the flash memory block to obtain the current data remaining holding time of the flash memory block.
Further, the nominal reliability of a flash block refers to: the data retention time is provided under the nominal erase count and error correction capability requirements of the reading device. All flash blocks have a nominal maximum retention time because the RBER increase is proportional to the time, and over a sufficiently long time the RBER must exceed the error correction capability threshold of the reading device (set to RBER').
Based on the above, the present application subtracts the current RBER value of the flash memory block from the error correction capability threshold RBER' corresponding to the flash memory block to obtain the current RBER increase allowance of the flash memory block, and divides the current RBER increase allowance of the flash memory block by the current RBER increase rate of the flash memory block to obtain the current data remaining retention time of the flash memory block.
It should be noted that, the FBC and RBER of the flash memory block have similar meanings, so that the RBER mentioned in this embodiment can be expressed by using the FBC instead, and similarly, the RBER' can be expressed by using the FBC instead.
As an alternative embodiment, evaluating the wear level of the flash block according to the electron leakage degree value and the electron leakage trend value of the flash block includes:
calculating the abrasion degree Pa of the flash memory block according to Pa= (alpha x LL, beta x LT); wherein LL is the electron leakage level value of the flash memory block; LT is the electron leakage trend value of a flash memory block; pa is two-dimensional values of LL and LT; alpha and beta are scale factors for adjusting the proportional relationship of LL and LT; the larger LL and LT, the more severe the wear of the flash blocks.
Specifically, although there is a certain degree of correlation between the electron leakage degree value LL of the flash memory block and the electron leakage trend value LT of the flash memory block, the abrasion degree pa= (α×ll, β×lt) is expressed in two dimensions, which is not expressed by simple mathematics, as shown in fig. 8.
It should be noted that α and β are scaling factors for adjusting the proportional relationship between LL and LT. Typically, α=1- β, α, β e {0.1,0.2,0.3,0.4 … … 0.9}; specifically, the size of the scaling factor can be preset for adjusting different design requirements, for example, if some flash memories are located in places with higher working temperatures, the LT ratio of the electronic leakage trend value needs to be adjusted higher, and α < β, β is 0.6,0.7, etc. (the scaling can be set according to the temperature); some flash memories are novel QLCs (quad-Level cells, which refer to 1 Cell capable of storing 4 bits of data), and if the nominal value is smaller, the electronic leakage Level value LL needs to be increased, and α > β, α is 0.6,0.7, etc.
In addition, the Solid State Disk based on flash memory is generally referred to as an SSD (Solid State Disk), and as shown in fig. 9, the Solid State Disk SSD includes: 1) SSD Controller (solid state disk Controller): as a control operation unit, managing an SSD internal system; 2) NAND Flash Array: as a storage unit, storing data (user data and system data), typically presenting multiple Flash channels (CH for short), one Channel being independently connected to a set of NAND Flash Array, such as CH0/CH1 CHx in fig. 9; the NAND Flash (Flash) has the characteristics that the NAND Flash must be erased before writing, and each Flash has limited erasing times; 3) DDR (Double Data Rate), double Rate synchronous dynamic random Access memory)/DRAM (Dynamic Random Access Memory ): as a cache; 4) Connector: for connecting to a host, such as a PC (Personal Computer ) or server; 5) Other peripheral units, such as PMIC (Power Management IC, power management Integrated Circuit), OSC (Oscillator), JTAG (Joint Test Action Group ) interface, SPI (Serial Peripheral Interface, serial peripheral interface) interface, sensor and UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous receiver Transmitter) interfaces, and the like.
It should be noted that, the method for evaluating the wear level of the flash memory block provided in the above embodiment may be implemented by a controller program or a hardware logic circuit in a solid state disk based on flash memory. Specifically, as shown in fig. 10, the Sensor is a temperature Sensor, and is used for obtaining the working temperature of the flash memory; DDR is used to store a real-time maintenance table (the relevant parameters related to the calculation formula are maintained by the table, which is called maintenance table). The solid state disk controller includes: 1) CPU (central processing unit): the method is used for running computer programs, such as execution of a calculation formula, statistics recording of flash memory block erasing times, obtaining external parameters (temperature, RBER and IRBER), obtaining internal parameters (timing), updating a maintenance table and the like; 2) I2C controller: the CPU reads the temperature Sensor through the I2C controller to obtain the working temperature of the flash memory; 3) DDR controller: the CPU reads the DDR through the DDR controller to obtain a maintenance table; 4) And (3) a timer: setting a fixed time for periodic operation and recording; 5) RAM (RandomAccess Memory ): for storing computer programs, intermediate variables and data; 6) ECC Engine: the method is used for correcting error and encoding and decoding, and simultaneously calculating and outputting RBER and IRBER of the flash memory block; 7) FLC (flash memory controller): the method is used for reading and writing the flash memory.
As shown in fig. 11, which is a conceptual diagram of fig. 10, the data storage module: the system comprises a flash memory array and a DDR, wherein the flash memory array and the DDR are used for storing an EPC count and maintenance table and the like; flash memory attribute acquisition module: reading RBER and IRBER; a time attribute acquisition module: reading time data; a temperature attribute acquisition module: reading temperature data; the calculation module: and (5) calculating the equivalent values of Pa, LL and LT based on the related parameters.
The specific acquisition principle for the key parameter Δrber is as follows: as shown in fig. 12, Δt=t1-t 0, Δrber is obtained by subtracting the RBER of the flash memory block obtained at time t0 and time t1, so it is necessary to record the RBER (t 0) of the flash memory block at time t0 and the RBER (t 1) of the flash memory block at time t1, and after the completion of the calculation of t1, the RBER (t 1) can be directly used as the t0 value of the next stage. Also, the RBER (t 0) of the flash block is recorded, and also can be used to evaluate the reliability of the current data of the flash block, and the remaining retention time t= (RBER (DRt) -RBER (t 0)) ≡ (Δrber/Δt) of the flash block can be predicted by RBER (t 0) +Δrber/Δt < RBER (DRt); where RBER (DRt) is a known value, i.e., an error correction capability threshold. If t0 is the time immediately after writing, irber=rber (t 0).
For the maintenance table stored in DDR, at least two tables are included: 1) Pa parameter table: the table contains the relationship between the flash blocks and the wear Pa and contains calculated factor values related to Pa, as shown in table 1 below, the Pa parameter table records α, β, EPC, IRBER, and RBER (t 0), where RBER (t 0) also records the timestamp t0=pts0 of the occurrence of this value.
TABLE 1
2) Timestamp temperature table: a temperature table is recorded that tracks as a time stamp (TimeStamp) for a fixed period of time (e.g., 4 hours) and a power down period (PowerCycle), as shown in table 2 below.
TABLE 2
When Pa of a certain flash memory block is calculated, obtaining according to the flash memory block table lookup: EPC, IRBER, and RBER (T0), and also the average temperature values T of RBER (T1) and T0 to T1 of the flash block are required to be obtained: RBER (T1) is read when needed, and then a table is searched to obtain t1=PTS1, and an average temperature value T from T0 to T1 is calculated, so that Pa of the flash memory block can be calculated.
In addition, referring to fig. 13, the maintenance flow of the maintenance table is:
step S11: restoring the maintenance table: and after power-on, reading a history maintenance table from the flash memory, updating the power-on cycle number, and setting and starting a timer according to the set cycle. If the power is first powered on, a time stamp temperature table and a Pa parameter table are initialized; setting and starting a timer according to a set period, specifically, setting and starting a temperature update period timer and an LT update period timer according to the set period; the set period is predetermined, and is generally an engineering experience value.
Step S12: updating a maintenance table: 1) Reading and updating the temperature in a temperature updating period; the temperature updating period is triggered by a temperature updating period timer, and a time stamp temperature table is read and updated under the control of a program; 2) Updating EPC when erasing flash memory block, and reading and updating IRBER; the update EPC is that each time a flash memory block is erased, the EPC of the corresponding erased flash memory block is added with 1; the IRBER reading is that when each writing of the flash memory block is finished, the IRBER of the flash memory block is immediately read and updated to the Pa parameter table; 3) Reading a corresponding flash block RBER (t 1), calculating and updating LT, and updating RBER (t 0) in an LT update period; wherein the LT update period is triggered by an LT update period timer; reading RBER (t 1) of the corresponding flash memory block is completed by the device shown in FIG. 10 at time t 1; updating LT and RBER (t 0) is to calculate LT according to a calculation formula, update the obtained value to a Pa parameter table, and update RBER (t 1) as a new RBER (t 0) to the Pa parameter table; 4) When any one of 2) and 3) occurs, pa is calculated and updated, specifically Pa is calculated according to a calculation formula, and the obtained value is updated to a Pa parameter table.
Step S13: and (3) storing a maintenance table: when a power failure occurs, a real-time maintenance table is written into a nonvolatile memory (flash memory). It will be appreciated that after the real-time maintenance table is written into the non-volatile memory, the table serves as a history maintenance table for the next power up.
The application also provides a solid state disk, comprising:
a flash memory;
and a controller for implementing any one of the above-described methods for evaluating the wear level of the flash memory blocks when executing the computer program.
The description of the solid state disk provided in the present application refers to the embodiment of the wear degree evaluation method, and the description is omitted herein.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (5)
1. A method for evaluating wear level of a flash memory block, comprising:
acquiring an electron leakage degree value of a flash memory block immediately after electron injection;
acquiring an electron leakage trend value of the flash memory block into which electrons are injected;
evaluating the abrasion degree of the flash memory block according to the electron leakage degree value and the electron leakage trend value of the flash memory block;
the method for obtaining the electron leakage degree value of the flash memory block immediately after electron injection comprises the following steps:
acquiring the erasing times of the flash memory block, and acquiring an initial error bit evaluation value of the flash memory block immediately after the electron injection;
determining an electron leakage degree value of the flash memory block immediately after electron injection according to the erasing times and the initial error bit evaluation value; wherein a positive correlation is formed between the erasure number and the initial error bit evaluation value and the electron leakage degree value;
wherein, obtaining the initial error bit evaluation value of the flash memory block immediately after the electron injection comprises:
obtaining an IRBER value or an IFBC value of the flash memory block immediately after the electrons are injected, and obtaining a temperature value of the flash memory block immediately after the electrons are injected;
correcting the IRBER value or the IFBC value according to the temperature value, obtaining an IRBER correction value or an IFBC correction value of the flash memory block immediately after the electrons are injected, and taking the IRBER correction value or the IFBC correction value as the initial error bit evaluation value;
wherein determining the electron leakage degree value of the flash memory block immediately after electron injection according to the erasing times and the initial error bit evaluation value comprises:
calculating an electron leakage degree value LL of the flash memory block immediately after electron injection according to LL=EPC=delta×IRBER or LL=EPC=delta×IFBC;
wherein EPC is the erase count; delta is IRBER corrected value of IRBER; δ is the IFBC correction value; delta is a first temperature compensation coefficient corresponding to the temperature value;
wherein obtaining the electron leakage trend value of the flash memory block into which electrons have been injected includes:
acquiring a unit error bit increase evaluation value of the flash memory block with injected electrons within a preset time, and acquiring an average temperature value of the flash memory block within the preset time;
correcting the unit error bit increase evaluation value according to the average temperature value to obtain an electronic leakage trend value of the flash memory block in the preset time;
the method for acquiring the unit error bit increase evaluation value of the flash memory block injected with electrons in the preset time comprises the following steps:
acquiring RBER increment or FBC increment of the flash memory block with injected electrons in a preset time;
dividing the RBER increment or the FBC increment by the preset time to correspondingly obtain the RBER increment rate or the FBC increment rate of the flash memory block in unit time, and taking the RBER increment rate or the FBC increment rate as the unit error bit increment evaluation value.
2. The method for evaluating the wear level of a flash memory block according to claim 1, wherein correcting the unit error bit increase evaluation value based on the average temperature value to obtain the electron leakage trend value of the flash memory block within the preset time comprises:
judging whether the average temperature value is larger than a preset standard temperature or not;
if yes, then according toOr->Calculating an electron leakage trend value LT of the flash memory block in the preset time; wherein Δt is the preset time; delta RBER is the RBER increase; Δfbc is the FBC increment; gamma is a second temperature compensation coefficient corresponding to the average temperature value, and gamma is smaller than 1;
if not, according toOr->And calculating an electron leakage trend value LT of the flash memory block in the preset time.
3. The method for evaluating the wear level of a flash block according to claim 1, further comprising:
subtracting the current RBER value or the current FBC value of the flash memory block from a preset error correction capability threshold RBER 'or a preset FBC' corresponding to the flash memory block to obtain the current RBER increase allowance or the current FBC increase allowance of the flash memory block;
and dividing the current RBER increase allowance or FBC increase allowance of the flash memory block by the current RBER increase rate or FBC increase rate of the flash memory block to obtain the current data remaining holding time of the flash memory block.
4. The method for evaluating the wear level of a flash block according to any one of claims 1 to 3, wherein evaluating the wear level of the flash block based on the electron leakage level value and the electron leakage tendency value of the flash block comprises:
calculating the wear degree Pa of the flash memory block according to pa= (α×ll, β×lt); wherein LL is an electron leakage level value of the flash memory block; LT is the electron leakage trend value of the flash memory block; pa is two-dimensional values of LL and LT; alpha and beta are scale factors for adjusting the proportional relationship of LL and LT; the larger LL and LT, the more severe the wear of the flash blocks.
5. A solid state disk, comprising:
a flash memory;
a controller for implementing the steps of the method of evaluating the wear level of a flash block according to any one of claims 1 to 4 when executing a stored computer program.
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