CN113764504A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113764504A
CN113764504A CN202010492484.1A CN202010492484A CN113764504A CN 113764504 A CN113764504 A CN 113764504A CN 202010492484 A CN202010492484 A CN 202010492484A CN 113764504 A CN113764504 A CN 113764504A
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gate
layer
semiconductor substrate
isolation structure
grid
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蔡巧明
张云香
魏兰英
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Zhongxin North Integrated Circuit Manufacturing Beijing Co ltd
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Zhongxin North Integrated Circuit Manufacturing Beijing Co ltd
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Priority to CN202010492484.1A priority Critical patent/CN113764504A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The application provides a semiconductor structure and a forming method thereof, comprising the following steps: providing a semiconductor substrate, wherein an isolation structure is formed in the semiconductor substrate; forming a grid structure on the surfaces of the semiconductor substrate and the isolation structure, wherein the grid structure comprises a grid dielectric layer formed on the surfaces of the semiconductor substrate and the isolation structure and a grid layer formed on the surface of the grid dielectric layer; forming side walls on two sides of the grid structure; and removing part of the gate layer on the isolation structure to expose the surface of part of the gate dielectric layer, and filling a metal gate at a corresponding position. The semiconductor structure and the forming method thereof can solve the problems of electric leakage and mismatching of the existing devices, and greatly improve the fault tolerance of a semiconductor manufacturing process.

Description

Semiconductor structure and forming method thereof
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the continuous development of integrated circuit technology, the number of semiconductor devices that can be integrated in a single chip is required to be as large as possible, and when designing an integrated circuit, several semiconductor devices with the same electrical parameters, such as MOS transistors, are generally used. However, in the design and production process of the device, due to uncertainty, random error and the like, some MOS transistors which are completely the same in design have errors after production, that is, electrical parameters of nominally the same MOS transistors often drift, so that mismatch (mismatch) of electrical parameters of the MOS transistors which should be the same originally is caused, that is, matching characteristics are reduced, and thus semiconductor performance is affected.
The specific reasons for this mismatch of transistor electrical parameters are many, and mainly include: when a Metal Gate (MG) is formed at a connection portion between a polysilicon Gate on the isolation structure and the contact hole, a Critical Dimension (CD) of an adopted mask is too large or is not aligned with a front layer during exposure, so that the Metal Gate is also formed on an Active Area (AA). The Threshold voltage (Vt) of the device having the metal gate region formed on the active region is controlled by the metal gate, the Threshold voltage of the rest of the device is still controlled by the polysilicon gate, and the Vt controlled by the metal gate is smaller than the Vt controlled by the polysilicon gate. After voltage is supplied, the device controlled by the metal gate is started earlier than the device controlled by the polysilicon gate, so that the leakage phenomenon is caused, and further, the Vt of the devices with the same size are different.
Disclosure of Invention
The technical problem to be solved by the application is that the fault tolerance of the existing metal gate structure is very high, however, when the existing process forms a metal gate on an isolation structure, the metal gate is often formed in a partial area of an active area due to the existence of process errors, and thus the problems of electric leakage and mismatch of devices in the active area are caused.
In order to solve the above technical problem, the present application discloses a method for forming a semiconductor structure, including: providing a semiconductor substrate, wherein an isolation structure is formed in the semiconductor substrate; forming a grid structure on the surfaces of the semiconductor substrate and the isolation structure, wherein the grid structure comprises a grid dielectric layer formed on the surfaces of the semiconductor substrate and the isolation structure and a grid layer formed on the surface of the grid dielectric layer; forming side walls on two sides of the grid structure; and removing part of the gate layer on the isolation structure to expose the surface of part of the gate dielectric layer, and filling a metal gate at a corresponding position.
In an embodiment of the present application, the process of removing a portion of the gate layer on the isolation structure to expose a surface of a portion of the gate dielectric layer and then filling the metal gate at a corresponding position includes: removing a part of the gate layer on the isolation structure to form a groove, wherein the groove does not penetrate through the gate layer in the width direction of the gate layer; and filling metal in the groove to form a metal gate.
In an embodiment of the present application, the metal gate has a width of at least 160 nm.
In an embodiment of the present application, the depth of the metal gate is 250 to 600 nm.
In an embodiment of the present application, the metal gate is located on both sides of the remaining gate layer.
In an embodiment of the present application, the distance between the metal gates is at least 160 nanometers.
In the embodiment of the application, a dry etching process is adopted to remove part of the gate layer on the surface of the isolation structure.
In an embodiment of the present application, a top surface of the metal gate is flush with a top surface of the gate layer.
In the embodiment of the present application, after forming the sidewalls on both sides of the gate structure, the method further includes: and forming a source electrode and a drain electrode in the semiconductor substrate at two sides of the grid structure.
In an embodiment of the present application, after forming the metal gate, the method further includes: forming an interlayer dielectric layer on the surfaces of the metal gate, the gate layer and the side wall; and etching the interlayer dielectric layer until the metal gate is exposed to form a contact hole.
An embodiment of the present application further provides a semiconductor structure, including: a semiconductor substrate having an isolation structure formed therein; the grid structure comprises a grid dielectric layer positioned on the surfaces of the semiconductor substrate and the isolation structure and a grid layer positioned on the surface of the grid dielectric layer; the metal gate is positioned on the surface of part of the gate dielectric layer on the isolation structure and is flush with the gate layer; and the side walls are positioned on the surfaces of the semiconductor substrate and the isolation structure at two sides of the grid structure and are flush with the grid layer.
In an embodiment of the present application, the metal gate has a width of at least 160 nm.
In an embodiment of the present application, the metal gate has a thickness of 250 to 600 nm.
In an embodiment of the present application, the metal gate is located on both sides of the gate layer.
In an embodiment of the present application, the distance between the metal gates is at least 160 nanometers.
In an embodiment of the present application, a top surface of the metal gate is flush with a top surface of the gate layer.
Compared with the prior art, the technical scheme of the application has at least the following beneficial effects: in the semiconductor structure of the application, the metal gate does not penetrate through the gate layer in the width direction of the gate layer, even when the gate layer on the isolation structure is etched to form the metal gate, process parameters have errors, for example, the mask is oversized or the mask is not aligned with the gate layer, so that the metal gate is also formed on an active area, but the threshold voltage of a device on an active area semiconductor is not controlled by the metal gate and is still controlled by the gate structure because the metal gate does not penetrate through the gate layer in the width direction of the gate layer, the problems of electric leakage and mismatch of the device on the active area semiconductor are avoided, and the fault tolerance of a semiconductor manufacturing process is greatly improved.
Furthermore, in order to meet the current process manufacturing requirements, metal gates are preferably formed on two sides of the gate layer on the surface of the isolation structure, the metal gate structure reduces the harsh requirements of an etching process on a mask layer CD, and if the mask layer CD is large, the metal gate structure can extend to the interlayer dielectric layers on two sides beyond the gate layer.
Furthermore, the method adopts a dry etching process with a high etching ratio, and can realize etching of the gate layer to avoid loss of the interlayer dielectric layer.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIGS. 1-3 are schematic views of a semiconductor structure;
fig. 4 to 14 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "upper", "lower", "top", "bottom", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.
Referring to fig. 1 to 3, fig. 1 is a schematic perspective view of a semiconductor structure, fig. 2 is a top view of fig. 1, and fig. 3 is a cross-sectional view of fig. 1 along a direction a-a. The semiconductor structure comprises a semiconductor substrate 100, wherein an isolation structure 110 is formed in the semiconductor substrate 100, and the isolation structure 110 may be a shallow trench isolation.
A gate structure is formed on the surface of the semiconductor substrate 100 and the isolation structure 110. Side walls 140 are formed on both sides of the gate structure. Interlayer dielectric layers 170 are formed on the surfaces of the semiconductor substrate 100 and the isolation structure 110 on the two sides of the sidewall 140.
The gate structure includes a gate dielectric layer 131 formed on the surfaces of the semiconductor substrate 100 and the isolation structure 110, and a gate layer 132 formed on the surface of the gate dielectric layer 131, and when a metal gate is formed in a subsequent process, the gate layer 132 on the surface of the isolation structure 110 is etched, and a metal gate material is filled in a corresponding position.
Referring to fig. 1 and fig. 3, a metal gate 150 is formed on the surface of the gate dielectric layer 131 on the isolation structure 110, and a top surface of the metal gate 150 is flush with a top surface of the gate layer 132 on the surface of the semiconductor substrate 100. When the metal gate 150 is formed, the gate layer 132 is removed to form a recess, and then the recess is filled with metal to form the metal gate 150.
Referring to fig. 1 and fig. 2, a gate layer 132 on the isolation structure 110 is usually removed by a dry etching process, and there is an error in CD of a mask used for etching, which may cover the active region semiconductor substrate, or the mask is not aligned with a previous layer (e.g., the gate layer) strictly during exposure, which may etch the gate layer 132 on the active region semiconductor substrate, and a metal gate 160 is also formed on the active region semiconductor substrate 100 during metal filling, thereby generating a parasitic MOS device.
Specifically, for devices on the semiconductor substrate 100, the Vt of the device is controlled by the metal gate 160 where the metal gate 160 is formed, and the Vt of the device remains controlled by the gate layer 132 on the semiconductor substrate 100 elsewhere.
When the gate layer 132 is a polysilicon gate, the Vt of the device controlled by the metal gate 160 is less than the Vt of the device controlled by the polysilicon gate. Therefore, after applying a voltage to the devices on the semiconductor substrate 100, the devices controlled by the metal gate 160 will be turned on earlier than the devices controlled by the gate layer 132, resulting in a leakage phenomenon, and further causing a difference in Vt of the devices of the same size.
Based on this, the semiconductor structure provided by the application improves the existing metal gate structure penetrating through the polysilicon gate, and even if the CD of a mask plate is too large or is not aligned during etching, the problems of electric leakage and mismatching of devices can not be caused.
The forming method of the semiconductor structure comprises the following steps:
step S1: providing a semiconductor substrate, wherein an isolation structure is formed in the semiconductor substrate;
step S2: forming a grid structure on the surfaces of the semiconductor substrate and the isolation structure, wherein the grid structure comprises a grid dielectric layer formed on the surfaces of the semiconductor substrate and the isolation structure and a grid layer formed on the surface of the grid dielectric layer;
step S3: forming side walls on two sides of the grid structure;
step S4: and removing part of the gate layer on the isolation structure to expose the surface of part of the gate dielectric layer, and filling a metal gate in a corresponding position, wherein the metal gate does not penetrate through the gate layer in the width direction of the gate layer.
The above specific processes are described in detail with reference to the accompanying drawings, and fig. 4 to 14 are schematic structural diagrams of the formation process of the semiconductor structure according to the embodiment of the present application.
Referring to fig. 4, in step S1, a semiconductor substrate 200 is provided. The semiconductor substrate 200 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and further includes a multilayer structure composed of the material layers or silicon-on-insulator (SOI), stacked-on-insulator (SSOI), or the like. In this embodiment, the material of the semiconductor substrate 200 is single crystal silicon or silicon-on-insulator.
An isolation structure is formed on the semiconductor substrate 200, the isolation structure may be a shallow trench isolation, the isolation structure may include an insulating dielectric layer 210 and an oxide layer 220 located between the insulating dielectric layer 210 and the semiconductor substrate 200, the oxide layer 220 may be formed by a thermal oxidation process, for example, a silicon oxide layer, and the insulating dielectric layer 210 may be made of silicon oxide, silicon nitride, silicon oxynitride, or the like. In this embodiment, the insulating dielectric layer 210 is made of silicon oxide, and the process for forming the insulating dielectric layer 210 may be a chemical vapor deposition process or a physical vapor deposition process, and optionally, the chemical vapor deposition process is, for example, a High Aspect Ratio (HARP) deposition process. Of course, the isolation structure may also be any other known trench isolation structure, and the formation method of the isolation structure may also be any manufacturing method of a trench isolation structure, which is not limited in this application.
Step S2, forming a gate structure on the surfaces of the semiconductor substrate and the isolation structure, where the gate structure includes a gate dielectric layer formed on the surfaces of the semiconductor substrate and the isolation structure and a gate layer formed on the surface of the gate dielectric layer.
Referring to fig. 5 and 6, fig. 6 is a sectional view taken along the direction B-B in fig. 5. Firstly, a gate dielectric material and a gate material are sequentially grown on the surfaces of the semiconductor substrate 200 and the isolation structure. Deposition methods such as furnace tube process, chemical vapor deposition process or physical vapor deposition process can be adopted. The gate dielectric material may include high dielectric materials such as silicon oxide, silicon oxynitride, hafnium oxide, titanium nitride, etc., and the deposited gate dielectric material may include a single layer or multiple layers. The gate material may be polysilicon, and in other embodiments of the present application, the gate material may further include at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon.
And etching the gate material and the gate dielectric material to form a gate layer 310 and a gate dielectric layer 320, wherein the gate layer 310 and the gate dielectric layer 320 form a gate structure. In other embodiments, the gate structure may also be a single-layer structure, and accordingly, the gate structure includes a gate layer 310, and the thickness of the gate layer 310 is 250 to 600 nm.
Referring to fig. 7, in step S3, spacers 410 are formed on two sides of the gate structure. The sidewall 410 also serves to protect the gate structure by defining the position of ion implantation in subsequent processes.
In the embodiment of the present application, the sidewall spacer 410 has a single-layer structure, and the material of the sidewall spacer 410 is silicon nitride. In other embodiments of the present application, the material of the sidewall may also be silicon oxide, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, boron carbonitride or other materials. In other embodiments of the present invention, the sidewall spacer may also have a stacked structure.
The method for forming the sidewall 410 is to deposit a barrier material layer on the surface of the semiconductor substrate 200, the surface of the gate structure, the sidewall and the surface of the isolation structure, and the barrier material layer can be deposited by a chemical vapor deposition method or grown by a furnace tube process. And then removing the barrier material layers on the surface of the isolation structure, the surface of the gate layer 310 of the gate structure and the surface of the semiconductor substrate 200, and forming side walls on two sides of the gate layer 310 and the gate dielectric layer 320 of the gate structure.
After the forming the sidewall spacers 410, the forming method may further include: source and drain lightly doped regions (not shown) are formed in the semiconductor substrate 200 at both sides of the gate structure. Specifically, with the side walls 410 as masks, doping ions are implanted into the semiconductor substrate 200 on both sides of the gate structure, and annealing treatment is performed after the ion implantation to activate the doping ions.
And then, forming a first interlayer dielectric layer on the surfaces of the semiconductor substrate and the isolation structure on the two sides of the side wall, wherein the top surface of the first interlayer dielectric layer is flush with the top surface of the gate layer.
Referring to fig. 8, a chemical vapor deposition process or a physical vapor deposition process may be used to deposit an interlayer dielectric material, such as silicon oxide, on the surface of the semiconductor substrate 200, the surface of the isolation structure, and the surface of the gate structure. The interlayer dielectric material is then planarized to expose the surface of the gate layer 310, and a first interlayer dielectric layer 510 is formed on the surface of the semiconductor substrate 200 and the surface of the isolation structure, and is flush with the top surface of the gate layer 310.
Then, in step S4, a portion of the gate layer on the isolation structure is removed to expose a surface of a portion of the gate dielectric layer, and then a metal gate is filled in a corresponding position.
A portion of the gate layer 310 over the isolation structure is first removed to form a recess. Unlike the prior art structure of forming the groove penetrating the gate layer 310 in the width direction of the gate layer 310, the groove formed in the present application does not penetrate the gate layer 310 in the width direction of the gate layer 310. The improvement has the advantages that if the CD of a mask used for forming the groove is too large or is not aligned with the gate layer 310 during etching, one part of the formed groove is positioned on the isolation structure, the other part of the formed groove is positioned on the active area semiconductor substrate, and the groove does not penetrate through the gate layer 310 in the width direction of the gate layer 310, so that the groove positioned on the active area semiconductor substrate does not penetrate through the gate layer on the semiconductor substrate, and after a metal gate is formed in the groove in the subsequent process, the metal gate positioned on the active area semiconductor substrate does not penetrate through the gate layer on the active area semiconductor substrate, so that the threshold voltage of a device at the metal gate on the active area semiconductor substrate is not controlled by the metal gate or is controlled by the original gate structure, and the problems of electric leakage and mismatching of the device caused by process errors are solved.
The present application forms a recess structure that does not penetrate through the gate layer 310 in the width direction of the gate layer 310, and has the following embodiments.
Referring to fig. 9, in an embodiment of the present invention, a portion of the gate layer 310 on the surface of the isolation structure is removed to expose a portion of the surface of the gate dielectric layer 320, and a groove is formed on each of two sides of the remaining gate layer 310, specifically, the groove is located between the sidewall 410 and the gate layer 310, such as the groove 611 and the groove 612 in the figure. The width of the groove 611 and the groove 612 is at least 160 nm, the groove 611 and the groove 612 are not communicated, the distance between the groove 611 and the groove 612 is at least 160 nm, that is, the width of the gate layer 310 between the groove 611 and the groove 612 is at least 160 nm, and the depth of the groove 611 and the groove 612 is 250 to 600 nm.
When the grooves 611 and 612 are formed, a mask layer (not shown in the figure) is formed on the surface of the gate layer 310, and if the size of the mask layer exceeds the size of the gate layer 310 in the actual process, the mask layer can be extended to the surface of the interlayer dielectric layer 510 on both sides, the mask layer is patterned, and the gate layer 310 is etched to form the grooves, because the dry etching process with a high selectivity ratio is adopted in the etching process, the interlayer dielectric layer 510 is hardly damaged. In the embodiment of the application, the gas used in the dry etching may be oxygen, fluorocarbon, or the like.
Referring to fig. 10, in a second embodiment of the present invention, a portion of the gate layer 310 on the surface of the isolation structure is removed to expose a portion of the gate dielectric layer 320, a groove 610 is formed between the gate layer 310 and the sidewall 410, the width of the groove 610 is at least 160 nm, the specific width of the groove 610 is matched with other processes, such as the current density of the contact hole, if the current density is higher, the number of the required contact holes is also larger, the width of the groove 610 is also increased, and when the width requirement is higher, the groove extends outward from the width of the polysilicon gate to the interlayer dielectric layer, and the width direction does not penetrate through the gate layer 310. The formation process is similar to that of the first embodiment.
Referring to fig. 11, in another embodiment of the present invention, a portion of the gate layer 310 on the surface of the isolation structure is removed, and a recess 610 is formed between the remaining gate layers 310. This method has a problem in that when the width of the gate layer 310 itself is small, it cannot be guaranteed that a recess is formed only in the middle of the gate layer 310 due to the limitation of the CD of the mask layer used in the current etching process. The grooves formed in the two previous modes are located between the gate layer 310 and the side walls 410, the mask layer can extend towards the interlayer dielectric layers on the two sides, and the grooves 610 can be formed only at the gate layer by combining with a dry etching process with a high etching ratio.
Taking the formation of the grooves on the two sides of the rest of the gate layer 310 as an example, the following process steps will be described.
Referring to fig. 12, metal is filled into the grooves 611 and 612 to form metal gates 711 and 712. The top surfaces of the metal gate 711 and the metal gate 712 are flush with the top surface of the gate layer 310. The metal gate 711 and the metal gate 712 have a width of at least 160 nm and a thickness of 250 to 600 nm. The distance between the metal gate 711 and the metal gate 712 is at least 160 nanometers.
Referring to fig. 13 and 14, fig. 13 is a schematic perspective view of a metal gate 711 and a metal gate 712 after being formed, and fig. 14 is a top view of fig. 13, in which a dotted line indicates a boundary between an isolation structure and an active region. The reason why the metal gate structure formed by the embodiment of the present application can solve the problems of leakage and mismatch of the device will now be analyzed in detail.
The metal gate of the embodiment of the present application shown in fig. 13 and 14 is formed in the presence of process errors. When the groove is etched, the gate layer 310 on a part of the active area semiconductor is covered due to the overlarge CD of the mask, so that the gate layer 310 on the isolation structure is etched, and meanwhile, the gate layer 310 on the part of the active area semiconductor is also etched. And filling metal into the groove formed by etching to form a metal gate. It can be seen that in the figure a portion of the metal gate is also formed over the active area semiconductor.
However, since the metal gate 711 and the metal gate 712 are not completely covered with the gate layer 131 on the active area semiconductor in the width direction, that is, a part of the gate layer 310 exists between the metal gate 711 and the metal gate 712, the threshold voltage of the device at the metal gate 711 and the metal gate 712 is not controlled by the metal gate 711 and the metal gate 712, but is still controlled by the gate structure, so that even if the metal gate is formed on the active area semiconductor substrate due to process errors, the threshold voltage of the device on the active area semiconductor substrate is not affected, and the fault tolerance of the semiconductor manufacturing process is improved.
After the metal gate 711 and the metal gate 712 are formed, some conventional steps may be performed as follows:
and depositing an interlayer dielectric material on the surfaces of the metal gate, the gate layer, the side wall and the first interlayer dielectric layer, flattening the interlayer dielectric material after the interlayer dielectric material is deposited to the specified thickness to form a second interlayer dielectric layer, and then etching the second interlayer dielectric layer until the metal gate is exposed to form a contact hole.
Referring to fig. 12, an embodiment of the present invention further provides a semiconductor structure, which mainly includes: a semiconductor substrate 200 having an isolation structure formed therein; the gate structure comprises a gate dielectric layer 320 positioned on the surfaces of the semiconductor substrate 200 and the isolation structure and a gate layer 310 positioned on the surface of the gate dielectric layer 320; the metal gate is positioned on the surface of a part of the gate dielectric layer 320 on the isolation structure and is flush with the gate layer 310; and the side walls 410 are positioned on the surfaces of the semiconductor substrate and the isolation structure at two sides of the gate structure and are flush with the gate layer 310.
In the embodiment of the present application, the metal gates are located on two sides of the gate layer, that is, the metal gate 711 and the metal gate 712 are located between the sidewall 410 and the gate layer 310.
In the embodiment of the present application, the width of the metal gate is at least 160 nm, the thickness of the metal gate is 250 to 600 nm, and the distance between the metal gate 711 and the metal gate 712 is at least 160 nm.
In the embodiment of the present application, the material of the gate layer 310 is polysilicon. The material of the metal gate 711 and the metal gate 712 includes a work function metal, for example, including at least one of tungsten, aluminum, and cobalt.
In this embodiment, the semiconductor structure may further include a first interlayer dielectric layer 510, where the first interlayer dielectric layer 510 is located on the semiconductor substrate 200 and the isolation structure surface at two sides of the sidewall spacer 410, and is flush with the top surface of the gate layer 310.
In other embodiments of the present application, the metal gate is formed by filling metal into the recess of fig. 10 or fig. 11.
In conclusion, upon reading the present detailed disclosure, those skilled in the art will appreciate that the foregoing detailed disclosure can be presented by way of example only, and not limitation. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, improvements, and modifications are intended to be suggested by this disclosure, and are within the spirit and scope of the exemplary embodiments of this disclosure.
Furthermore, certain terminology has been used in this application to describe embodiments of the disclosure. For example, "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present disclosure. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various portions of this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined as suitable in one or more embodiments of the disclosure.
It should be appreciated that in the foregoing description of embodiments of the disclosure, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of the subject disclosure. Alternatively, various features may be dispersed throughout several embodiments of the application. This is not to be taken as an admission that any of the features of the claims are essential, and it is fully possible for a person skilled in the art to extract some of them as separate embodiments when reading the present application. That is, embodiments in the present application may also be understood as an integration of multiple sub-embodiments. And each sub-embodiment described herein is equally applicable to less than all features of a single foregoing disclosed embodiment.
In some embodiments, numbers expressing quantities or properties used to describe and claim certain embodiments of the application are to be understood as being modified in certain instances by the term "about", "approximately" or "substantially". For example, "about," "approximately," or "substantially" can mean a ± 20% variation of the value it describes, unless otherwise specified. Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that may vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the embodiments of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible.
Each patent, patent application, publication of a patent application, and other material, such as articles, books, descriptions, publications, documents, articles, and the like, cited herein is hereby incorporated by reference. All matters hithertofore set forth herein except as related to any prosecution history, may be inconsistent or conflicting with this document or any prosecution history which may have a limiting effect on the broadest scope of the claims. Now or later associated with this document. For example, if there is any inconsistency or conflict in the description, definition, and/or use of terms associated with any of the included materials with respect to the terms, descriptions, definitions, and/or uses associated with this document, the terms in this document are used.
Finally, it should be understood that the embodiments of the application disclosed herein are illustrative of the principles of the embodiments of the present application. Other modified embodiments are also within the scope of the present application. Accordingly, the disclosed embodiments are presented by way of example only, and not limitation. Those skilled in the art may implement the present application in alternative configurations according to the embodiments of the present application. Thus, embodiments of the present application are not limited to those embodiments described with accuracy in the application.

Claims (15)

1. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate, wherein an isolation structure is formed in the semiconductor substrate;
forming a grid structure on the surfaces of the semiconductor substrate and the isolation structure, wherein the grid structure comprises a grid dielectric layer formed on the surfaces of the semiconductor substrate and the isolation structure and a grid layer formed on the surface of the grid dielectric layer;
forming side walls on two sides of the grid structure;
and removing part of the gate layer on the isolation structure to expose the surface of part of the gate dielectric layer, and filling a metal gate at a corresponding position.
2. The method of claim 1, wherein the step of removing a portion of the gate layer on the isolation structure to expose a portion of the gate dielectric layer and filling a metal gate at a corresponding position comprises:
removing a part of the gate layer on the isolation structure to form a groove, wherein the groove does not penetrate through the gate layer in the width direction of the gate layer;
and filling metal in the groove to form a metal gate.
3. The method of claim 1, wherein the metal gate has a width of at least 160 nm.
4. The method of claim 1, wherein the depth of the metal gate is 250 to 600 nm.
5. The method of claim 1, wherein the metal gate is on both sides of the remaining gate layer.
6. The method of claim 5, wherein a distance between the metal gates is at least 160 nm.
7. The method as claimed in claim 1, wherein a portion of the gate layer on the surface of the isolation structure is removed by a dry etching process.
8. The method of claim 1, wherein a top surface of the metal gate is flush with a top surface of the gate layer.
9. The method for forming a semiconductor structure according to claim 1, further comprising, after forming spacers on both sides of the gate structure: and forming a source electrode and a drain electrode in the semiconductor substrate at two sides of the grid structure.
10. The method of claim 1, further comprising, after forming the metal gate:
forming an interlayer dielectric layer on the surfaces of the metal gate, the gate layer and the side wall;
and etching the interlayer dielectric layer until the metal gate is exposed to form a contact hole.
11. A semiconductor structure, comprising:
a semiconductor substrate having an isolation structure formed therein;
the grid structure comprises a grid dielectric layer positioned on the surfaces of the semiconductor substrate and the isolation structure and a grid layer positioned on the surface of the grid dielectric layer;
the metal gate is positioned on the surface of part of the gate dielectric layer on the isolation structure and is flush with the gate layer;
and the side walls are positioned on the surfaces of the semiconductor substrate and the isolation structure at two sides of the grid structure and are flush with the grid layer.
12. The method of claim 11, wherein the metal gate has a width of at least 160 nm.
13. The method of claim 11, wherein the metal gate has a thickness of 250 to 600 nm.
14. The method of claim 11, wherein the metal gate is on both sides of the gate layer.
15. The method of claim 14, wherein a distance between the metal gates is at least 160 nm.
CN202010492484.1A 2020-06-03 2020-06-03 Semiconductor structure and forming method thereof Pending CN113764504A (en)

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