CN113764505A - Semiconductor structure and method of forming the same - Google Patents
Semiconductor structure and method of forming the same Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/512—Disposition of the gate electrodes, e.g. buried gates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
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Abstract
The present application provides a semiconductor structure and a method of forming the same, the semiconductor structure comprising: the semiconductor substrate comprises a first region, a second region and an isolation structure for isolating the first region from the second region, the isolation structure comprises a first isolation part adjacent to the first region and a second isolation part adjacent to the second region, and the top surface of the first isolation part is connected with the top surface of the second isolation part through an inclined surface; the residual dielectric layer is positioned on the surfaces of part of the first isolation part, part of the second isolation part and the inclined plane; the barrier layer covers the surface of the residual dielectric layer; and the side wall covers the side walls of the barrier layer and the residual dielectric layer. The semiconductor structure can solve the problem of metal pollution of residual dielectric layers.
Description
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In the manufacturing process of the high-voltage device, the medium-voltage device and the low-voltage device, in order to enable the heights of the top surfaces of the dummy gate layers in different areas to be the same during grinding of the interlayer dielectric layer, the height of the top surface of the semiconductor substrate in the area where the high-voltage device or the medium-voltage device is located is reduced before the gate oxide layer is grown, and therefore a slope is formed between the area where the high-voltage device is located and the area where the low-voltage device is located, or between the area where the medium-voltage device is located and the area where the low-voltage device is located. When the gate dielectric layer is etched by adopting an etching process subsequently, the gate dielectric layer on the surface of the slope is difficult to completely remove.
The gate dielectric layer remaining on the "sloped" surface is likely to be exposed in subsequent processes, resulting in metal contamination problems.
Disclosure of Invention
The method solves the technical problem that a residual dielectric layer formed on an inclined plane after a gate dielectric layer is etched is exposed in a subsequent process, so that the metal pollution is caused.
To solve the above technical problem, the present application discloses a semiconductor structure, comprising: the semiconductor substrate comprises a first region, a second region and an isolation structure for isolating the first region and the second region, wherein the top surface of the semiconductor substrate of the second region is lower than that of the semiconductor substrate of the first region, the isolation structure comprises a first isolation part adjacent to the first region and a second isolation part adjacent to the second region, the top surface of the second isolation part is flush with the top surface of the semiconductor substrate of the second region and lower than that of the first isolation part, and the top surface of the first isolation part is connected with the top surface of the second isolation part through an inclined surface; the residual dielectric layer is positioned on the surfaces of part of the first isolation part, part of the second isolation part and the inclined plane; the barrier layer covers the surface of the residual dielectric layer; and the side wall covers the side walls of the barrier layer and the residual dielectric layer.
In an embodiment of the present application, a height difference between the top surface of the semiconductor substrate of the second region and the top surface of the semiconductor substrate of the first region is 50 to 250 angstroms.
In an embodiment of the present application, the semiconductor structure further includes: the first grid structure comprises a first dielectric layer positioned on the surface of the semiconductor substrate in the first area and a first grid layer positioned on the surface of the first dielectric layer; and the second gate structure comprises a second dielectric layer positioned on the surface of the semiconductor substrate in the second area and a second gate layer positioned on the surface of the second dielectric layer.
In an embodiment of the present application, the thickness of the first dielectric layer is 5 to 80 angstroms, and the thickness of the second dielectric layer is 100 to 250 angstroms.
In an embodiment of the present application, the materials of the first dielectric layer, the second dielectric layer and the residual dielectric layer include SiO2、HfO2At least one of HfSiON or TiN.
In an embodiment of the present application, the thicknesses of the first gate layer, the second gate layer and the barrier layer are 300 to 1000 angstroms.
In an embodiment of the present application, the material of the first gate layer, the second gate layer and the blocking layer is polysilicon.
In an embodiment of the present application, the first region is a low voltage device region, and the second region is a high voltage device region or a medium voltage device region.
The application also provides a method for forming a semiconductor structure, which comprises the following steps: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region, a second region and an isolation structure for isolating the first region and the second region, the top surface of the semiconductor substrate of the second region is lower than that of the semiconductor substrate of the first region, the isolation structure comprises a first isolation part adjacent to the first region and a second isolation part adjacent to the second region, the top surface of the second isolation part is flush with the top surface of the semiconductor substrate of the second region and lower than that of the first isolation part, and the top surface of the first isolation part is connected with the top surface of the second isolation part through a bevel; forming residual dielectric layers on the surfaces of part of the first isolation part, part of the second isolation part and the inclined plane, and forming a barrier layer on the surface of the residual dielectric layer; and forming a side wall on the side walls of the residual dielectric layer and the barrier layer.
In an embodiment of the present application, a height difference between the top surface of the semiconductor substrate of the second region and the top surface of the semiconductor substrate of the first region is 50 to 250 angstroms.
In an embodiment of the present application, the process of forming the residual dielectric layer and the barrier layer includes: forming a second dielectric material layer on the surfaces of the semiconductor substrate, the first isolation part, the second isolation part and the inclined plane of the first region and the second region; removing the semiconductor substrate in the first area and the second medium material layer on the surface of the first isolation part; forming a first dielectric material layer on the surfaces of the semiconductor substrate, the first isolation part and the second dielectric material layer in the first region; forming a gate material layer on the surface of the first dielectric material layer; and etching part of the gate material layer, the first dielectric material layer and the second dielectric material layer, forming a first gate structure on the surface of the semiconductor substrate in the first area, forming a second gate structure on the surface of the semiconductor substrate in the second area, forming a residual dielectric layer on the surface of the inclined plane, and forming a barrier layer on the surface of the residual dielectric layer.
In an embodiment of the present application, the first gate structure includes a first dielectric layer located on the surface of the semiconductor substrate in the first region and a first gate layer located on the first dielectric layer, and the second gate structure includes a second dielectric layer located on the surface of the semiconductor substrate in the second region and a second gate layer located on the surface of the second dielectric layer.
In the embodiment of the application, a first dielectric layer is formed after etching a part of the first dielectric material layer in the first region, and a second dielectric layer is formed after etching a part of the second dielectric material layer in the second region and the first dielectric material layer.
In an embodiment of the present application, the thicknesses of the first gate layer, the second gate layer and the barrier layer are 300 to 1000 angstroms.
In an embodiment of the present application, the material of the first gate layer, the second gate layer and the blocking layer is polysilicon.
In an embodiment of the present application, the materials of the first dielectric layer, the second dielectric layer and the residual dielectric layer include SiO2、HfO2At least one of HfSiON or TiN.
In an embodiment of the present application, a top surface of the first dielectric layer is flush with a top surface of the second dielectric layer.
In an embodiment of the present application, a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer.
In an embodiment of the present application, the thickness of the first dielectric layer is 5 to 80 angstroms, and the thickness of the second dielectric layer is 100 to 250 angstroms.
Compared with the prior art, the technical scheme of the application has at least the following beneficial effects: the height difference is formed on the surfaces of the semiconductor substrates of the first area and the second area, so that the top surface of the gate material layer of the second area in the subsequent process can be flush with the top surface of the gate material layer of the first area, and the phenomenon that a part of the gate layer of the second area is ground in the subsequent CMP process, so that the thickness of the finally formed metal gate is influenced, the performance of a device is influenced, and even the device in the second area cannot work is avoided.
Furthermore, the gate material layer on the inclined plane is left when the gate material layer is etched to form the gate structure, so that the gate material layer covers the surface of the residual dielectric layer, namely a barrier layer is arranged on the residual dielectric layer, and side walls are formed on the side walls of the first gate structure, the second gate structure, the residual dielectric layer and the barrier layer, so that the barrier layer and the side walls can prevent the residual dielectric layer from being exposed in the subsequent technological process, and the problem of metal pollution caused by the exposure of the residual dielectric layer after etching is solved under the condition that other redundant steps are not introduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIGS. 1-2 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 3 to 12 are schematic structural diagrams of steps of a semiconductor structure forming method according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "upper", "lower", "top", "bottom", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred devices or elements must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," and the like are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.
In some semiconductor structures, the top surfaces of the semiconductor substrate in the high-voltage device region and the low-voltage device region have a height difference, or the top surface of the semiconductor substrate between the medium-voltage device region and the low-voltage device region has a height difference, so that an inclined surface exists on the isolation structure, when the gate dielectric material layer is etched to form a gate structure, the gate dielectric material layer on the inclined surface is equivalent to a thick "side wall", and is difficult to completely etch and remove, the residual gate dielectric material layer has a high probability of being exposed in a subsequent process to cause a metal pollution problem, and the reason for the situation is analyzed by combining one semiconductor structure.
Referring to fig. 1, a semiconductor structure includes a semiconductor substrate 100, where the semiconductor substrate 100 includes a first region 110 and a second region 120, and an isolation structure 130 for isolating the first region 110 from the second region 120. Wherein the top surface of the second region 120 is lower than the top surface of the first region 110.
The isolation structure 130 includes a first isolation portion 130a adjacent to the first region 110 and a second isolation portion 130b adjacent to the second region 120, and a top surface of the second isolation portion 130b is flush with a top surface of the semiconductor substrate of the second region 120. The first isolation portion 130a is integrally connected to the second isolation portion 130b, a top surface of the second isolation portion 130b is lower than a top surface of the first isolation portion 130a, and an inclined surface 130c is formed between the first isolation portion 130a and the second isolation portion 130 b.
Referring to fig. 2, when forming gate structures on the semiconductor substrates in the first region 110 and the second region 120, a gate dielectric layer 140 and a gate layer 150 need to be sequentially formed on the semiconductor substrates in the first region 110 and the second region 120 and on the surfaces of the isolation structure 130.
Then, the gate layer 150 and the gate dielectric layer 140 are etched, so that gate structures are formed on the semiconductor substrate in the first region 110 and the second region 120, but the gate dielectric layer 140 is also formed on the inclined surface while being formed on other surfaces, so that the gate dielectric layer 140 on the inclined surface is similar to a "sidewall", and is difficult to be completely etched, and the gate dielectric layer 140 remaining on the inclined surface causes metal contamination in a subsequent process.
In the process of forming the gate structure by etching, the gate layer 150 may remain on the inclined surface, and the gate dielectric layer 140 is not directly exposed at this time, but in subsequent processes, such as sidewall etching, PSR (PMOS silicon Recess, PMOS Si process), NSR (NMOS silicon Recess, NMOS Si process), source and drain, the remaining thin gate layer 150 is finally completely removed, and cannot play a role in protecting the gate dielectric layer 140, so that the gate dielectric layer 140 is exposed, thereby causing metal contamination.
Therefore, when the grid structure is formed through etching, the grid dielectric layer and the grid layer on the inclined surface are purposefully reserved, and the grid layer covers the grid dielectric layer, so that the grid dielectric layer is not exposed in the subsequent process, and metal pollution is avoided.
The application provides a method for forming a semiconductor structure, which comprises the following steps:
step S1, providing a semiconductor substrate, where the semiconductor substrate includes a first region and a second region, and an isolation structure isolating the first region and the second region, the top surface of the second region semiconductor substrate is lower than the top surface of the first region semiconductor substrate, the isolation structure includes a first isolation portion adjacent to the first region and a second isolation portion adjacent to the second region, the top surface of the second isolation portion is flush with the top surface of the second region semiconductor substrate and lower than the top surface of the first isolation portion, and the top surface of the first isolation portion is connected to the top surface of the second isolation portion through an inclined surface;
step S2, forming residual dielectric layers on the surfaces of part of the first isolation part, part of the second isolation part and the inclined plane, wherein a barrier layer is formed on the surface of the residual dielectric layer;
and step S3, forming side walls on the side walls of the residual dielectric layer and the barrier layer.
The above specific processes are described in detail with reference to the accompanying drawings, and fig. 3 to 12 are schematic structural diagrams of the formation process of the semiconductor structure according to the embodiment of the present application.
Referring to fig. 3, step S1, a semiconductor substrate 200 is provided. The semiconductor substrate 200 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and further includes a multilayer structure composed of the material layers or silicon-on-insulator (SOI), stacked-on-insulator (SSOI), or the like. In this embodiment, the material of the semiconductor substrate 200 is single crystal silicon or silicon-on-insulator.
The semiconductor substrate 200 includes a first region 210 and a second region 220, and each of the first region 210 and the second region 220 may include N-type or P-type dopant ions. The device formed on the semiconductor substrate in the first region 210 is a first device, the device formed on the semiconductor substrate in the second region 220 is a second device, and the operating voltage of the first device is lower than that of the second device, for example, the first device may be a low-voltage device, the second device may be a high-voltage device or a medium-voltage device, in this embodiment, the first device is a low-voltage device, and the second device is a medium-voltage device.
The semiconductor substrate 200 further comprises an isolation structure 230 isolating the first region 210 and the second region 220. The isolation structure 230 includes a first isolation portion 231 adjacent to the first region 210 and a second isolation portion 232 adjacent to the second region 220, a top surface of the second isolation portion 232 is flush with a top surface of the semiconductor substrate in the second region 220 and lower than the top surface of the first isolation portion 231 and the top surface of the semiconductor substrate in the first region 210, and the top surface of the first isolation portion 231 is connected to the top surface of the second isolation portion 232 through a bevel 233.
Wherein, the top surface of the semiconductor substrate of the second region 220 is lower than the top surface of the semiconductor substrate of the first region 210, that is, there is a height difference between the semiconductor substrate of the first region 210 and the semiconductor substrate of the second region 220, and the height difference is realized by:
the semiconductor substrate 200 of the second region 220 is etched by using a dry etching process or a wet etching process, and according to the difference between the etching process and the etching gas or etching solution used in the etching process, the isolation structure 230 adjacent to the second region 220 is also partially etched, that is, the second isolation portion 232 is also etched, and in fig. 3, the surface of the second isolation portion 232 is schematically shown to be flush with the surface of the semiconductor substrate of the second region 220 after being etched.
The thickness of the semiconductor substrate etched to remove the second region 220 ranges from 50 a to 250 a, for example, that is, the height difference between the top surface of the semiconductor substrate of the second region 220 and the top surface of the semiconductor substrate of the first region 210 ranges from 50 a to 250 a, for example, 50 a, 80 a, 100 a, 150 a, 200 a, 250 a, etc.
Referring to fig. 3, each of the first isolation portion 231 and the second isolation portion 232 may include an insulating dielectric layer 230a and an oxide layer 230b located between the insulating dielectric layer 230a and the semiconductor substrate, where the oxide layer 230b may be made of, for example, a silicon oxide layer and may be formed by a thermal oxidation process, and the insulating dielectric layer 230a may be made of, for example, silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the insulating dielectric layer 230a is made of silicon oxide, and the process for forming the insulating dielectric layer 230a may be a chemical vapor deposition process or a physical vapor deposition process, and optionally, the chemical vapor deposition process may be, for example, a High Aspect Ratio (HARP) deposition process. Of course, the isolation structure 230 may also be any other known trench isolation structure, and the forming method of the isolation structure 230 may also be any manufacturing method of a trench isolation structure, which is not limited in this application.
Step S2, forming a residual dielectric layer on the surfaces of part of the first isolation portion, part of the second isolation portion, and the inclined surface, and forming a barrier layer on the surface of the residual dielectric layer. The method specifically comprises the following steps:
referring to fig. 4, a second dielectric material layer 242 is formed on the surfaces of the semiconductor substrate, the first isolation portion 231, the second isolation portion 232 and the inclined surface 233 of the first region 210 and the second region 220, and in some embodiments, the second dielectric material layer may be formed by a thermal oxidation process or a chemical vapor deposition process, and the thermal oxidation process may be performed in a furnace tube.
The semiconductor substrate of the first region 210 and the second dielectric material layer 242 on the surface of the first isolation portion 231 are then removed. In some embodiments, a photoresist mask may be formed on the surfaces of the semiconductor substrate of the second region 220, the second isolation portion 232 and the inclined surface 233, the second dielectric material layer 242 on the surfaces of the semiconductor substrate of the first region 210 and the first isolation portion 231 is removed, and the surfaces of the semiconductor substrate of the first region 210 and the first isolation portion 231 are cleaned.
Then, a first dielectric material layer 241 is formed on the surface of the semiconductor substrate, the first isolation portion 231 and the second dielectric material layer 242 in the first region 210, for example, by physical vapor deposition or atomic layer deposition. At this time, the top surface of the first dielectric material layer 241 of the first region 210 and the top surface of the first dielectric material layer 241 of the second region 220 are flush.
Referring to fig. 5, a gate material layer 260 is formed on the surface of the first dielectric material layer 241 by a chemical vapor deposition process or a physical vapor deposition process.
Referring to fig. 6, a patterned mask layer (not shown) is formed on the surface of the gate material layer 260, and the patterned mask layer defines the size and position of the gate structure to be formed on the surface of the semiconductor substrate in the first region 210, the second region 220, and the isolation structure. And etching part of the gate material layer 260, the first dielectric material layer 241 and the second dielectric material layer 242, forming a first gate structure on the surface of the semiconductor substrate in the first region 210, forming a second gate structure on the surface of the semiconductor substrate in the second region 220, and forming a residual dielectric layer 253 and a blocking layer 263 on the surface of the inclined plane 233.
In the embodiment of the present application, the first gate structure includes a first dielectric layer 251 located on the surface of the semiconductor substrate in the first region 210 and a first gate layer 261 located on the first dielectric layer 251, and the second gate structure includes a second dielectric layer 252 located on the surface of the semiconductor substrate in the second region 220 and a second gate layer 262 located on the surface of the second dielectric layer 252. And etching part of the gate material layer 260 of the first region 210 to form a first gate layer 261, and etching part of the first dielectric material layer 241 of the first region 210 to form a first dielectric layer 251. And etching part of the gate material layer 260 in the second region 220 to form a second gate layer 262, and etching part of the first dielectric material layer 241 and the second dielectric material layer 242 in the second region 220 to form a second dielectric layer 252.
And etching part of the gate material layer 260 on the surfaces of the first isolation structure 231 and the second isolation structure 232 to form a barrier layer 263, and etching part of the first dielectric material layer 241 on the surface of the first isolation structure 231, part of the first dielectric material layer 241 on the surface of the second isolation structure 232 and the second dielectric material layer 242 to form a residual dielectric layer 253. The blocking layer 263 covers the surface of the residual dielectric layer 253, so that the metal pollution phenomenon caused by the exposure of the residual dielectric layer 253 can be effectively avoided. It should be noted that the size of the blocking layer 263 is designed according to an actual process, and only the blocking layer 263 needs to be ensured to cover the residual dielectric layer 253 that is left due to incomplete etching in the past, which can be realized by designing a mask layer pattern during etching.
In the embodiment of the present application, the thickness of the first dielectric layer 251 is smaller than that of the second dielectric layer 252. The thickness of the first dielectric layer 251 may be 5 to 80 angstroms, such as 5, 30 or 60 angstroms, and the thickness of the second dielectric layer 252 may be 100 to 250 angstroms, such as 120, 160, 200, 220, 240 or 250 angstroms, which are designed according to the actual process. The material of the first dielectric layer 251 and the second dielectric layer 252 may be silicon oxide or a high dielectric constant (HK) material, and the HK material may be HfO2HfSiON, TiN, or the like.
In an actual process, the residual dielectric layer 253 is inevitably formed additionally when the first dielectric layer 251 or the second dielectric layer 252 is formed. In the subsequent process, the residual dielectric layer 253 is expected to be etched and removed, but the residual dielectric layer 253 is not easy to etch because the residual dielectric layer 253 is positioned on the inclined surface 233, so that the thickness of the residual dielectric layer 253 is not specified in the actual process.
Referring to fig. 7, a spacer material layer is formed on the first region 210, the second region 220 and the isolation structure, and the spacer material layer is etched to form a spacer 320 on the sidewalls of the first gate structure, the second gate structure, the residual dielectric layer and the barrier layer. The sidewall spacers 320 may cover sidewalls of the residual dielectric layer to prevent the residual dielectric layer from being exposed and causing metal contamination.
After the sidewall spacers 320 are formed, a subsequent process may be performed. For example, the following conventional steps may be included:
referring to fig. 8, an ion implantation process is performed in the semiconductor substrate at two sides of the first gate structure and the second gate structure to form a source 270 and a drain 280. In the sidewall process or the source/drain process, if the surface of the residual dielectric layer 253 is not covered by the blocking layer 263, metal contamination is easily caused.
Referring to fig. 9, a polishing stop layer 290 is formed on the semiconductor substrate and the isolation structure of the first region 210 and the second region 220, the surface of the first gate structure and the second gate structure, and the surface of the sidewall. The material of the polishing stop layer 290 may include silicon nitride, titanium nitride, etc. and have a thickness ranging from 80 to 150 angstroms, such as 100 angstroms, 120 angstroms, 130 angstroms, 135 angstroms, 150 angstroms, etc. The method for forming the polishing stop layer 290 may include a chemical vapor deposition process or a physical vapor deposition process.
Referring to fig. 10, a dielectric material layer 300a is formed on the surface of the polishing stop layer 290, wherein the material of the dielectric material layer 300a includes silicon oxide. The process of forming the dielectric material layer 300a may be a chemical vapor deposition process or a physical vapor deposition process, such as a plasma vapor deposition process.
Referring to fig. 11, the dielectric material layer 300a is planarized until the surfaces of the first gate layer 261 and the second gate layer 262 are completely exposed, the dielectric material layer 300a is transformed into a dielectric layer 300, and the surface of the dielectric layer 300 is flush with the top surfaces of the first gate layer 261 and the second gate layer 262.
Referring to fig. 12, a dry etching process is used to remove the first gate layer 261 and the second gate layer 262, and a metal gate 310 is formed on the surfaces of the first dielectric layer 251 and the second dielectric layer 252. The process of forming the metal gate 310 is, for example, chemical vapor deposition or physical vapor deposition. And performing a chemical mechanical polishing process until the surface of the metal gate 310 is flush with the surface of the dielectric layer 300, wherein the metal gate is made of a work function metal, such as metal tungsten, metal aluminum, metal diamond, and the like. The metal gate material described in the embodiments of the present application is, for example, metal aluminum.
In addition to the above-listed processes, PSR, NSR processes, etc. may be included, and in these processes, if the residual dielectric layer 253 is exposed, metal contamination may occur, so it is highly desirable to design the barrier layer 263 on the residual dielectric layer 253.
According to the method, when the grid electrode structure is formed through etching, a part of the first isolation structure, a part of the second isolation structure and the grid electrode material layer on the inclined surface are designed and reserved, so that the grid electrode material layer covers the surface of the residual medium layer, namely, a barrier layer is arranged on the surface of the residual medium layer through etching at ordinary times, and the problem of metal pollution caused by exposure of the residual medium layer can be solved under the condition that the original process steps are not changed.
Meanwhile, the height difference is formed on the surfaces of the semiconductor substrates of the first area and the second area, so that the top surface of the gate material layer of the second area can be flush with the top surface of the gate material layer of the first area in the subsequent process, and the gate material layer of the second area is prevented from being ground in the subsequent CMP process.
Referring to fig. 7, an embodiment of the present invention further provides a semiconductor structure, including: a semiconductor substrate 200, wherein the semiconductor substrate comprises a first region 210 and a second region 220, and an isolation structure 230 isolating the first region 210 and the second region 220, the top surface of the semiconductor substrate of the second region 220 is lower than that of the semiconductor substrate of the first region 210, the isolation structure 230 comprises a first isolation portion 231 adjacent to the first region 210 and a second isolation portion 232 adjacent to the second region 220, the top surface of the second isolation portion 232 is flush with the top surface of the semiconductor substrate of the second region 220 and lower than the top surface of the first isolation portion 232, and the top surface of the first isolation portion 231 is connected with the top surface of the second isolation portion 232 through a bevel 233;
a residual dielectric layer 253 located on the surfaces of a part of the first isolation portion 231, a part of the second isolation portion 232 and the inclined surface 233;
a blocking layer 263 covering the surface of the residual dielectric layer 253;
and the side walls cover the side walls of the first gate structure, the second gate structure, the barrier layer 263 and the residual dielectric layer 253.
The first region 210 may be a low voltage device region, and the second region 220 may be a medium voltage device region or a high voltage device region. The isolation structure 230 may be a shallow trench isolation.
The height difference between the top surface of the semiconductor substrate of the second region 220 and the top surface of the semiconductor substrate of the first region 210 may be 50 to 250 angstroms.
In some embodiments, the semiconductor structure may further include: a first gate structure including a first dielectric layer 251 located on the surface of the semiconductor substrate in the first region 210 and a first gate layer 261 located on the surface of the first dielectric layer 251; and the second gate structure comprises a second dielectric layer 252 positioned on the surface of the semiconductor substrate in the second region 220 and a second gate layer 262 positioned on the surface of the second dielectric layer 252.
The thickness of the first dielectric layer 251 may be 5 to 80 angstroms, and the thickness of the second dielectric layer 252 may be 100 to 250 angstroms. The materials of the first dielectric layer 251, the second dielectric layer 252 and the residual dielectric layer 253 can include SiO2、HfO2At least one of HfSiON or TiN.
The thickness of the first gate layer 261, the second gate layer 262 and the blocking layer 263 can be 300-1000 angstroms. The material of the first gate layer 261, the second gate layer 262 and the blocking layer 263 may be polysilicon.
In conclusion, upon reading the present detailed disclosure, those skilled in the art will appreciate that the foregoing detailed disclosure can be presented by way of example only, and not limitation. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, improvements, and modifications are intended to be suggested by this disclosure, and are within the spirit and scope of the exemplary embodiments of this disclosure.
Furthermore, certain terminology has been used in this application to describe embodiments of the disclosure. For example, "one embodiment," "an embodiment," and/or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present disclosure. Therefore, it is emphasized and should be appreciated that two or more references to "an embodiment" or "one embodiment" or "an alternative embodiment" in various portions of this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined as suitable in one or more embodiments of the disclosure.
It should be appreciated that in the foregoing description of embodiments of the disclosure, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of the subject disclosure. Alternatively, various features may be dispersed throughout several embodiments of the application. This is not to be taken as an admission that any of the features of the claims are essential, and it is fully possible for a person skilled in the art to extract some of them as separate embodiments when reading the present application. That is, embodiments in the present application may also be understood as an integration of multiple sub-embodiments. And each sub-embodiment described herein is equally applicable to less than all features of a single foregoing disclosed embodiment.
In some embodiments, numbers expressing quantities or properties used to describe and claim certain embodiments of the application are to be understood as being modified in certain instances by the term "about", "approximately" or "substantially". For example, "about," "approximately," or "substantially" can mean a ± 20% variation of the value it describes, unless otherwise specified. Accordingly, in some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that may vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the embodiments of the application are approximations, the numerical values set forth in the specific examples are reported as precisely as possible.
Each patent, patent application, publication of a patent application, and other material, such as articles, books, descriptions, publications, documents, articles, and the like, cited herein is hereby incorporated by reference. All matters hithertofore set forth herein except as related to any prosecution history, may be inconsistent or conflicting with this document or any prosecution history which may have a limiting effect on the broadest scope of the claims. Now or later associated with this document. For example, if there is any inconsistency or conflict in the description, definition, and/or use of terms associated with any of the included materials with respect to the terms, descriptions, definitions, and/or uses associated with this document, the terms in this document are used.
Finally, it should be understood that the embodiments of the application disclosed herein are illustrative of the principles of the embodiments of the present application. Other modified embodiments are also within the scope of the present application. Accordingly, the disclosed embodiments are presented by way of example only, and not limitation. Those skilled in the art may implement the present application in alternative configurations according to the embodiments of the present application. Thus, embodiments of the present application are not limited to those embodiments described with accuracy in the application.
Claims (19)
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