CN113764403A - 阻容耦合快速开启的可控硅静电防护器件及其制作方法 - Google Patents
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- 230000008878 coupling Effects 0.000 title claims abstract description 31
- 238000010168 coupling process Methods 0.000 title claims abstract description 31
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 18
- 239000010703 silicon Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000002347 injection Methods 0.000 claims abstract description 128
- 239000007924 injection Substances 0.000 claims abstract description 128
- 238000002955 isolation Methods 0.000 claims abstract description 51
- 238000005859 coupling reaction Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000007943 implant Substances 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000003990 capacitor Substances 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 12
- 230000015556 catabolic process Effects 0.000 claims description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 7
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 230000005012 migration Effects 0.000 claims description 3
- 238000013508 migration Methods 0.000 claims description 3
- 230000005516 deep trap Effects 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 238000004528 spin coating Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000002513 implantation Methods 0.000 description 12
- 238000004088 simulation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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Abstract
本发明公开了一种阻容耦合快速开启的可控硅静电防护器件,包括P型衬底;P型衬底中设有N型埋层;N型埋层上方为第一N型深阱、第二N型深阱和P型衬底外延层P‑EPI;第二N型深阱上有N阱;P型衬底外延层P‑EPI上有第二P阱;第二P阱内设有第二P+注入区和内嵌N型MOS管,第N阱内设有横跨第二P阱与N阱的第二N+注入区、第三P+注入区与第三N+注入区;第一N型深阱、第二N型深阱、N阱与N型埋层构成N型隔离带;第一P+注入区、第二P+注入区、第四P+注入区和第一N+注入区连接在一起并作为器件的阴极,第三P+注入区与第三N+注入区Ⅱ连接在一起并作为器件的阳极。
Description
技术领域
本发明涉及静电防护领域,特别涉及一种阻容耦合快速开启的可控硅静电防护器件及其制作方法。
背景技术
随着半导体制程工艺的进步,集成电路特征尺寸越来越小,芯片集成度越来越高,静电造成芯片以及电子产品失效的情况愈加严重了,对电子产品以及集成电路芯片进行ESD防护成为了产品工程师们面临的主要难题之一。
传统的可控硅静电防护器件的剖面图见图1,其等效电路图见图2,当ESD脉冲加在SCR阳极时,N阱与P阱形成反偏PN节,当这个脉冲电压高于这个PN结的雪崩击穿电压的时候,器件的内部就会产生大量的雪崩电流,电流的流通路径为经过第二P阱流向阴极,当电流在第二P阱的寄生阱电阻两端形成的电压高于纵向NPN三极管的be结(由第二P阱与第一N+注入构成)的正向的导通电压的时候,此三极管开启。此三极管开通后,为横向PNP三极管提供基极电流,促使横向PNP也开启,纵向NPN与横向PNP形成正反馈回路,相互促进,使SCR最后能完全开启,当阴极出现正向ESD脉冲的时候,阴极到阳极之间相当于一个正偏PN结,其放电效果往往比SCR开启还要好,但是SCR具有高触发电压以及低维持电压,易超出设计窗口,容易造成闩锁,故需要降低触发电压并提高其维持电压。
发明内容
为了解决上述技术问题,本发明提供一种结构简单的阻容耦合快速开启的可控硅静电防护器件及其制作方法。
本发明实施例提供了一种阻容耦合快速开启的可控硅静电防护器件,包括P型衬底;
所述P型衬底中设有N型埋层;
所述N型埋层上方为第一N型深阱、第二N型深阱和P型衬底外延层P-EPI;
所述第二N型深阱上有N阱;
所述P型衬底外延层P-EPI上有第二P阱;
所述第二P阱内设有第二P+注入区和内嵌N型MOS管,其中,所述内嵌N型MOS管包括第一N+注入区、第二N+注入区与栅区,所述第二N+注入区横跨所述第二P阱与所述N阱;
所述内嵌N型MOS管的源漏两端,所述第一N+注入区、所述第二N+注入区表面有硅化物阻挡层;
所述第N阱内设有横跨所述第二P阱与所述N阱的第二N+注入区、第三P+注入区与第三N+注入区;
所述第一N型深阱、所述第二N型深阱、所述N阱与所述N型埋层构成N型隔离带;
所述第一P阱、所述第一P+注入区、所述第三P阱、所述第四P+注入区为常规保护环;
所述第一P+注入区、所述第二P+注入区、所述第四P+注入区和所述第一N+注入区连接在一起并作为器件的阴极,所述第三P+注入区与所述第三N+注入区Ⅱ连接在一起并作为器件的阳极;
所述栅区位于所述第一N+注入区与所述第二N+注入区之间;
所述栅区与所述阴极之间包括电阻R,所述栅区与所述阳极之间包括电容C。
其中,所述第一N+注入区和所述第二N+注入区之间由所述栅区隔开,每一所述注入区之间都由场氧隔离区隔开,从左到右依次为第一场氧隔离区、第二场氧隔离区、第三场氧隔离区、第四场氧隔离区和第五场氧隔离区。
其中,所述第一场氧隔离区的左部位于所述第一P阱的表面,所述第一场氧隔离区右部位于所述第二P阱的表面;所述第五场氧隔离区左部位于所述N阱的表面,所述第五场氧隔离区右部位于所述第三P阱的表面;所述第二场氧隔离区位于所述第二P阱的表面,所述第三场氧隔离区和所述第四场氧隔离区位于N阱的表面。
其中,当高压ESD脉冲到达器件的阳极,器件的阴极接低电位时,阴阳极之间并联了电阻R和电容C,电阻R两端形成电压差;电阻R一端接阴极,一端接内嵌NMOS栅端,ESD脉冲耦合一个电压到内嵌NMOS管的栅端,随着耦合电压增大,内嵌NMOS沟道开启得更大,引导电流从第二N+注入区经由栅下沟道流向所述第一N+注入区与所述第二P阱,最终流向所述阴极。
其中,当高压ESD脉冲到达器件的阳极时,器件阴极接低电位,所述N阱以及所述第二N+注入区与所述第二P阱形成反偏的PN结,若脉冲电压高于该结的雪崩击穿电压,器件的内部产生雪崩电流,雪崩电流注入所述第二P阱,使可控硅的寄生三极管开启,触发可控硅的开启;所述第二N+注入区的掺杂浓度比所述N阱高,使得所述第二N+注入区与所述第二P阱之间的反偏击穿电压小,降低器件的触发电压。
其中,所述N型埋层与所述第一N型深阱、所述第二N型深阱构成N型隔离带。
本发明实施例还提供了一种根据本发明任一实施例提供的阻容耦合快速开启的可控硅静电防护器件的制作方法,包括以下步骤:
步骤一:在P型衬底中形成N型埋层;
步骤二:在所述N型埋层上方生成第一N型深阱和第二N型深阱;
步骤三:在所述第二N型深阱上方生成N阱;
步骤四:在所述P型衬底上,与N阱同深度的地方,生成第一P阱、第二P阱、第三P阱,所述第二P阱与所述N阱之间距离为零;
步骤五:在所述第一P阱上生成第一P+注入,在所述第二P阱上生成第二P+注入与第一N+注入,在所述N阱上生成第三P+注入与第三N+注入,在所述第三P阱上生成P+注入,在所述第二P阱与所述N阱交界处生成第二N+注入;
步骤六:在所述第一N+注入和所述第二N+注入之间生成栅;
步骤七:除了所述第一N+注入区与所述第二N+注入区之间之外,在其他注入之间从左至右依次生成第一场氧隔离区至第五场氧隔离区;
步骤八:对每一注入区进行退火处理,消除杂质在注入区进行的迁移;
步骤九:第一N+注入区与第二N+注入区表面添加硅化物阻挡层;
步骤十:用金属层将所述第一P+注入区、所述第二P+注入区、所述第四P+注入区和所述第一N+注入区连接在一起并作为器件的阴极,将所述第三N+注入区和所述第三P+注入区连接在一起并作为器件的阳极,所述栅端和所述阴极之间连一个电阻,所述栅端和所述阳极之间连接一个电容。
其中,所述步骤一之前还包括如下步骤:
在所述P型衬底上生长一层二氧化硅薄膜,之后淀积一层氮化硅;旋涂光刻胶层于晶圆上,加掩膜版对其进行曝光以及显影,形成隔离浅槽;将二氧化硅、氮化硅和隔离浅槽进行刻蚀,去除光刻胶层,淀积一层二氧化硅,然后进行化学机抛光,直到氮化硅层为止,去除掉氮化硅层。
本发明的有益效果在于:
1、本发明的第二N+注入区能够转移器件击穿面,降低击穿电压,调节该注入区的宽度,还能调节击穿电压的大小。
2、本发明可以在不同工艺下进行栅极耦合电压仿真,得出该工艺下合适的RC值与合适的栅端耦合电压,使沟道稍微开启,帮助SCR开启,达到降低器件触发电压与提升器件开启速度的目的。
3、本发明的第二N型深阱与N型埋层的使用不仅有很好的隔离效果,减少不必要的寄生效应,还能引入纵向NPN的SCR路径,增加器件的维持电压,一定程度上避免闩锁的发生;
附图说明
图1为传统SCR静电防护器件的剖面图。
图2为传统SCR静电防护器件的等效电路图。
图3为本发明实施例提供的一种阻容耦合快速开启的可控硅静电防护器件的剖面图。
图4为本发明实施例提供的一种阻容耦合快速开启的可控硅静电防护器件的等效电路图。
具体实施方式
下面结合附图和实施例对本发明作进一步的说明。
如图3所示,一种阻容耦合快速开启的可控硅静电防护器件,包括P型衬底101;所述衬底中设有N型埋层201;所述N型埋层上方为第一N型深阱301、第二N型深阱302、P型外延层衬底102;所述第二N型深阱上有N阱403;所述P型外延层P-EPI上有第二P阱402;所述第二P阱内设有第二P+注入区502和内嵌N型MOS管,其中内嵌N型MOS管包括第一N+注入区503、第二N+注入区504与栅区701,而第二N+注入区504横跨第二P阱402与N阱403;所述内嵌N型MOS管的源漏两端,也就是第一、二N+注入区表面有硅化物阻挡层(salicide block SAB层);所述第N阱内设有横跨第二P阱402与N阱403的第二N+注入区504、第三P+注入区505与第三N+注入区506;所述第一、二N型深阱(301、302)、N阱403与N型埋201层构成N型隔离带,包围着器件的核心区域;所述第一P阱401、第一P+注入区501和第三P阱404、第四P+注入区507是常规保护环;所述第一、二、四P+注入区(501、502、507)、第一N+注入区503连接在一起并作为器件的阴极,第三P+注入区505与第三N+注入区506连接在一起并作为器件的阳极;所述栅区701位于第一N+503与第二N+注入区504之间;栅区与阴极之间接了电阻R801,栅区与阳极之间接了电容C802;
上述的阻容耦合快速开启的可控硅静电防护器件,其特征在于:第一和第二N+注入区(503、504)之间是由栅区701隔开,除此以外,各个注入区之间都由场氧FOX隔开,从左到右依次为第一至第五场氧隔离区(601-605);
上述场氧区的特征在于:所述第一场氧隔离区601的左部位于第一P阱401的表面,第一场氧隔离区601右部位于第二P阱402的表面;所述第五场氧隔离区605左部位于N阱403的表面,第五场氧隔离区605右部位于第三P阱404的表面;所述第二场氧隔离区602位于第二P阱402的表面,第三、四场氧隔离区603、604位于N阱403的表面。
所述的内嵌N型MOS管以及电容电阻R801、C802,其特征在于:当高压ESD脉冲到达器件的阳极,器件的阴极接低电位时,由于阴阳极之间并联了电阻R801和电容C802,形成阻容耦合效应,电阻R801两端就会马上形成一个电压差;又由于电阻R801一端接阴极,一端接内嵌NMOS栅端701,所以ESD脉冲就会耦合一个电压到内嵌NMOS管的栅端701,随着耦合电压增大,内嵌NMOS沟道也会开启得更大,引导一部分电流从第二N+注入区504经由栅下沟道流向第一N+注入区503与第二P阱402,最终流向阴极。
上述的内嵌N型MOS管,其特征还有:MOS管源漏两端,即第一、二N+注入区503、504表面电阻率较高,是由于制作工艺上在相应位置添加了硅化物阻挡层(salicide blockSAB层);
根据所述电阻R801和电容C802,其特征有:电阻R801的大小影响耦合电压的持续时间,电阻越大耦合电压持续越久,电容C802影响耦合电压大小,电容越大耦合电压越大;电阻在几十到上百千欧不等,电容在几皮法到几十皮法不等,具体看实现工艺下仿真来确定,一般来说RC的值应该使耦合电压在MOS开启电压Vth左右,持续时间在几微秒以内;
所述的阻容耦合快速开启的可控硅静电防护器件,其特征在于:当高压ESD脉冲到达器件的阳极时,器件阴极接低电位,N阱403以及第二N+注入区504与第二P阱402形成一个反偏的PN结,若脉冲电压高于该结的雪崩击穿电压,器件的内部产生大量的雪崩电流,大量雪崩电流注入第二P阱402,使可控硅的寄生三极管得以开启,从而触发整个可控硅的开启;由于第二N+注入区504的掺杂浓度比N阱403高,使得第二N+注入区504与第二P阱402之间的反偏击穿电压更小,相应地也降低了器件的触发电压。
所述的N型埋层201与第一、二N型深阱301、302,其特征在于:N型埋层201与第一、二N型深阱301、302构成N型隔离带,包围着器件的核心区域,减少寄生效应,同时还能提高维持电压。
上述的阻容耦合快速开启的可控硅静电防护器件的制作方法,包括以下步骤:
步骤一:在P型衬底101中形成N型埋层201;
步骤二:在N型埋层201上方生成第一N型深阱301和第二N型深阱302;
步骤三:在第二N型深阱302上方生成N阱403;
步骤四:在P型衬底102上,与N阱403同样深度的地方,生成第一、二、三P阱401、402、404,第二P阱402与N阱403之间距离为零;
步骤五:在第一P阱401上生成第一P+注入501,在第二P阱402上生成第二P+注入502与第一N+注入503,在N阱403上生成第三P+注入505与第三N+注入506,在第三P阱404上生成P+注入507,在第二P阱402与N阱403交界处生成第二N+注入504;
步骤六:在第一N+注入503和第二N+注入504之间生成POLY栅701;
步骤七:除了第一N+注入区503与第二N+注入区504之间外,在其他注入之间从左至右依次生成第一场氧隔离区至第五场氧隔离区601-605;
步骤八:对第所有注入区进行退火处理,消除杂质在注入区进行的迁移;
步骤九:第一N+注入区503与第二N+注入区504表面添加硅化物阻挡层(SAB层),提高注入区表面电阻率;
步骤十:用金属层将第一、二、四P+注入区501、502、507和第一N+注入区503连接在一起并作为器件的阴极,将三N+注入区506和第三P+注入区505连接在一起并作为器件的阳极,栅端701和阴极之间连一个电阻R801,栅端701和阳极之间连接一个电容C802。
本发明阻容耦合快速开启的可控硅静电防护器件的制作方法过程简单、操作方便。制作出的阻容耦合快速开启的可控硅静电防护器件结构,器件中的电容R和电阻C不是固定的,可以通过不同工艺下进行栅极耦合电压仿真,得出该工艺下合适的RC值与合适的栅端耦合电压,使沟道稍微开启,帮助SCR开启,达到降低器件触发电压与提升器件开启速度的目的;如果器件触发电压过高,可以适当增大RC耦合参数,增大栅端耦合电压,或者调节S1、S2、S3的距离,来降低器件触发电压。本发明实例器件件采用0.18μm的BCDMOS工艺。
Claims (8)
1.一种阻容耦合快速开启的可控硅静电防护器件,其特征在于,包括P型衬底;
所述P型衬底中设有N型埋层;
所述N型埋层上方为第一N型深阱、第二N型深阱和P型衬底外延层P-EPI;
所述第二N型深阱上有N阱;
所述P型衬底外延层P-EPI上有第二P阱;
所述第二P阱内设有第二P+注入区和内嵌N型MOS管,其中,所述内嵌N型MOS管包括第一N+注入区、第二N+注入区与栅区,所述第二N+注入区横跨所述第二P阱与所述N阱;
所述内嵌N型MOS管的源漏两端,所述第一N+注入区、所述第二N+注入区表面有硅化物阻挡层;
所述第N阱内设有横跨所述第二P阱与所述N阱的第二N+注入区、第三P+注入区与第三N+注入区;
所述第一N型深阱、所述第二N型深阱、所述N阱与所述N型埋层构成N型隔离带;
所述第一P阱、所述第一P+注入区、所述第三P阱、所述第四P+注入区为常规保护环;
所述第一P+注入区、所述第二P+注入区、所述第四P+注入区和所述第一N+注入区连接在一起并作为器件的阴极,所述第三P+注入区与所述第三N+注入区Ⅱ连接在一起并作为器件的阳极;
所述栅区位于所述第一N+注入区与所述第二N+注入区之间;
所述栅区与所述阴极之间包括电阻R,所述栅区与所述阳极之间包括电容C。
2.根据权利要求1所述的阻容耦合快速开启的可控硅静电防护器件,其特征在于,所述第一N+注入区和所述第二N+注入区之间由所述栅区隔开,每一所述注入区之间都由场氧隔离区隔开,从左到右依次为第一场氧隔离区、第二场氧隔离区、第三场氧隔离区、第四场氧隔离区和第五场氧隔离区。
3.根据权利要求2所述的阻容耦合快速开启的可控硅静电防护器件,其特征在于,所述第一场氧隔离区的左部位于所述第一P阱的表面,所述第一场氧隔离区右部位于所述第二P阱的表面;所述第五场氧隔离区左部位于所述N阱的表面,所述第五场氧隔离区右部位于所述第三P阱的表面;所述第二场氧隔离区位于所述第二P阱的表面,所述第三场氧隔离区和所述第四场氧隔离区位于N阱的表面。
4.根据权利要求1所述的阻容耦合快速开启的可控硅静电防护器件,其特征在于,当高压ESD脉冲到达器件的阳极,器件的阴极接低电位时,阴阳极之间并联了电阻R和电容C,电阻R两端形成电压差;电阻R一端接阴极,一端接内嵌NMOS栅端,ESD脉冲耦合一个电压到内嵌NMOS管的栅端,随着耦合电压增大,内嵌NMOS沟道开启得更大,引导电流从第二N+注入区经由栅下沟道流向所述第一N+注入区与所述第二P阱,最终流向所述阴极。
5.根据权利要求4所述的阻容耦合快速开启的可控硅静电防护器件,其特征在于,当高压ESD脉冲到达器件的阳极时,器件阴极接低电位,所述N阱以及所述第二N+注入区与所述第二P阱形成反偏的PN结,若脉冲电压高于该结的雪崩击穿电压,器件的内部产生雪崩电流,雪崩电流注入所述第二P阱,使可控硅的寄生三极管开启,触发可控硅的开启;所述第二N+注入区的掺杂浓度比所述N阱高,使得所述第二N+注入区与所述第二P阱之间的反偏击穿电压小,降低器件的触发电压。
6.根据权利要求1所述的阻容耦合快速开启的可控硅静电防护器件,其特征在于,所述N型埋层与所述第一N型深阱、所述第二N型深阱构成N型隔离带。
7.一种根据权利要求1-6中任一项所述的阻容耦合快速开启的可控硅静电防护器件的制作方法,包括以下步骤:
步骤一:在P型衬底中形成N型埋层;
步骤二:在所述N型埋层上方生成第一N型深阱和第二N型深阱;
步骤三:在所述第二N型深阱上方生成N阱;
步骤四:在所述P型衬底上,与N阱同深度的地方,生成第一P阱、第二P阱、第三P阱,所述第二P阱与所述N阱之间距离为零;
步骤五:在所述第一P阱上生成第一P+注入,在所述第二P阱上生成第二P+注入与第一N+注入,在所述N阱上生成第三P+注入与第三N+注入,在所述第三P阱上生成P+注入,在所述第二P阱与所述N阱交界处生成第二N+注入;
步骤六:在所述第一N+注入和所述第二N+注入之间生成栅;
步骤七:除了所述第一N+注入区与所述第二N+注入区之间之外,在其他注入之间从左至右依次生成第一场氧隔离区至第五场氧隔离区;
步骤八:对每一注入区进行退火处理,消除杂质在注入区进行的迁移;
步骤九:第一N+注入区与第二N+注入区表面添加硅化物阻挡层;
步骤十:用金属层将所述第一P+注入区、所述第二P+注入区、所述第四P+注入区和所述第一N+注入区连接在一起并作为器件的阴极,将所述第三N+注入区和所述第三P+注入区连接在一起并作为器件的阳极,所述栅端和所述阴极之间连一个电阻,所述栅端和所述阳极之间连接一个电容。
8.根据权利要求7所述的阻容耦合快速开启的可控硅静电防护器件的制作方法,其特征在于,所述步骤一之前还包括如下步骤:
在所述P型衬底上生长一层二氧化硅薄膜,之后淀积一层氮化硅;旋涂光刻胶层于晶圆上,加掩膜版对其进行曝光以及显影,形成隔离浅槽;将二氧化硅、氮化硅和隔离浅槽进行刻蚀,去除光刻胶层,淀积一层二氧化硅,然后进行化学机抛光,直到氮化硅层为止,去除掉氮化硅层。
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EP4333059A1 (en) * | 2022-09-01 | 2024-03-06 | GlobalFoundries U.S. Inc. | Gated protection device structures for an electrostatic discharge protection circuit |
CN115513201B (zh) * | 2022-10-26 | 2024-06-04 | 湖南静芯微电子技术有限公司 | 高维持低阻均匀导通双向可控硅静电防护器件及制作方法 |
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EP4333059A1 (en) * | 2022-09-01 | 2024-03-06 | GlobalFoundries U.S. Inc. | Gated protection device structures for an electrostatic discharge protection circuit |
CN115513201A (zh) * | 2022-10-26 | 2022-12-23 | 湖南静芯微电子技术有限公司 | 高维持低阻均匀导通双向可控硅静电防护器件及制作方法 |
CN115513201B (zh) * | 2022-10-26 | 2024-06-04 | 湖南静芯微电子技术有限公司 | 高维持低阻均匀导通双向可控硅静电防护器件及制作方法 |
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