CN113764332B

CN113764332B - Semiconductor structure and forming method thereof

Info

Publication number: CN113764332B
Application number: CN202010509211.3A
Authority: CN
Inventors: 金吉松; 亚伯拉罕·庾
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2020-06-07
Filing date: 2020-06-07
Publication date: 2024-07-02
Anticipated expiration: 2040-06-07
Also published as: CN113764332A; US20210384072A1

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate; forming a plurality of conductive functional layers extending along a first direction and sequentially arranged along a second direction on a substrate, a bottom dielectric layer positioned on the substrate between the conductive functional layers, and a blocking structure positioned in the conductive functional layers, wherein the blocking structure segments the conductive functional layers positioned on two sides of the blocking structure along the first direction; forming a top dielectric layer covering the bottom dielectric layer, the conductive functional layer and the blocking structure; etching the top dielectric layer positioned above the junction position of the blocking structure and the conductive functional layer and a part of the blocking structure positioned on the side wall of the conductive functional layer to form a through hole penetrating through the top dielectric layer and exposing part of the top and part of the side wall of the conductive functional layer; and filling a through hole interconnection structure in the through hole, wherein the through hole interconnection structure is contacted with part of the top and part of the side wall of the conductive functional layer. The embodiment of the invention is further beneficial to improving the performance of the semiconductor structure.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

As integrated circuit fabrication moves toward ultra large scale integrated circuits (ULSI), the density of circuitry within them increases, and the number of devices contained therein increases, such that the surface of the wafer does not provide sufficient area to fabricate the desired interconnect lines. In order to meet the increased interconnect demands of devices after shrinking, the design of multi-layered metal interconnect structures with more than two layers realized by interconnect trenches and vias has become a necessary approach for very large scale integrated circuit technology.

In the back-end fabrication of semiconductor devices, a metal interconnect structure formation process is typically required. The metal interconnect structure formation process is typically performed on a semiconductor substrate that typically has an active region on which semiconductor devices such as transistors and capacitors are formed. In the metal interconnection structure, there may be a plurality of layers of conductive plugs and metal interconnection lines, and the plurality of layers of metal interconnection lines may be electrically connected through the conductive plugs. When forming a subsequent metal interconnect on a previous layer of conductive plugs or forming a subsequent layer of conductive plugs on a previous layer of metal interconnect, an interlayer dielectric layer is typically formed on the previous layer of metal plugs or metal interconnect, then a Via (Via) and an interconnect Trench (Trench) are formed in the interlayer dielectric layer, and finally the Via and the interconnect Trench are filled with metal to form the subsequent layer of conductive plugs or metal interconnect.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, which are beneficial to improving the performance of the semiconductor structure.

In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of conductive functional layers extending along a first direction and sequentially arranged along a second direction on the substrate, a bottom dielectric layer positioned on the substrate between the conductive functional layers, and a blocking structure positioned in the conductive functional layers, wherein the blocking structure divides the conductive functional layers positioned on two sides of the blocking structure along the first direction; forming a top dielectric layer covering the bottom dielectric layer, the conductive functional layer and the blocking structure; etching a top dielectric layer positioned above the junction position of the blocking structure and the conductive functional layer and a part of the blocking structure positioned on the side wall of the conductive functional layer to form a through hole penetrating through the top dielectric layer and exposing a part of the top and a part of the side wall of the conductive functional layer; and filling a through hole interconnection structure in the through hole, wherein the through hole interconnection structure is contacted with part of the top and part of the side wall of the conductive functional layer.

Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; a plurality of conductive functional layers positioned on the substrate, extending along a first direction and sequentially arranged along a second direction; the bottom dielectric layer is positioned on the substrate between the conductive functional layers; a blocking structure in the conductive functional layer, the blocking structure dividing the conductive functional layer located at both sides of the blocking structure along the first direction; the top dielectric layer is covered on the bottom dielectric layer, the conductive functional layer and the blocking structure; the through hole interconnection structure comprises a first part, a second part and a top dielectric layer, wherein the first part is positioned in the partial width blocking structure of the side wall of the conductive functional layer and is in contact with the partial side wall of the conductive functional layer, the second part is connected with the first part and positioned on the first part, penetrates through the top dielectric layer above the junction position of the blocking structure and the conductive functional layer and is in contact with the partial top of the conductive functional layer.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

In the method for forming the semiconductor structure provided by the embodiment of the invention, the through hole interconnection structure is contacted with the partial top of the conductive functional layer, and the through hole interconnection structure can be partially positioned on the end part of the conductive functional layer, which is close to the blocking structure, so that the degree of freedom of layout design of the through hole interconnection structure is improved; in addition, in the step of forming the through hole, the top dielectric layer located above the junction position of the blocking structure and the conductive functional layer and part of the blocking structure on the side wall of the conductive functional layer are etched, so that the through hole also exposes part of the side wall of the conductive functional layer, accordingly, in the process of forming the through hole interconnection structure, the through hole interconnection structure is not only in contact with part of the top of the conductive functional layer, but also in contact with part of the side wall of the conductive functional layer, that is, the through hole interconnection structure covers the corner of the top of the conductive functional layer adjacent to the blocking structure, which is beneficial to increasing the contact area between the through hole interconnection structure and the conductive functional layer, thereby reducing the contact resistance between the through hole interconnection structure and the conductive functional layer, and further improving the performance of the semiconductor structure.

Drawings

FIG. 1 is a schematic diagram of a semiconductor structure;

Fig. 2 to 19 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention;

fig. 20 to 23 are schematic structural views corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

The interconnection performance of the devices formed at present is poor. A semiconductor structure analysis device is now incorporated for reasons of poor interconnect performance.

Referring to fig. 1, a schematic structural diagram of a semiconductor structure is shown.

The semiconductor structure includes: a substrate 1; a bottom dielectric layer 2 on the substrate 1; a plurality of interconnection lines 3 extending in the first direction and sequentially arranged in the second direction, located in the bottom dielectric layer 2; a blocking structure 4 located in the interconnect line 3, the blocking structure 4 dividing the interconnect line 3 located at both sides of the blocking structure 4 along the first direction; a top dielectric layer 5 covering the interconnect lines 3, blocking structures 4 and bottom dielectric layer 2; a via interconnect structure 6 extending through the top dielectric layer 5 above the junction of the blocking structure 4 and the interconnect line 3 and contacting a portion of the top of the interconnect line 3.

In the above semiconductor structure, the process of partially contacting (PARTIAL VIA LANDING) the via interconnection structure 6 with the interconnection line 3 is utilized, the via interconnection structure 6 is located in the top dielectric layer 5 and covers the junction between the blocking structure 4 and the interconnection line 3, that is, only part of the bottom of the via interconnection structure 6 contacts with the interconnection line 3, the via interconnection structure 6 can directly fall on the end of the interconnection line 3 near the blocking structure 4, which is favorable for improving the degree of freedom of layout design of the via interconnection structure 6, and correspondingly improving the friendliness to the subsequent winding.

However, in the above semiconductor structure, only a part of the bottom of the via interconnection structure 6 is in contact with the interconnection line 3, and the contact area between the via interconnection structure 6 and the interconnection line 3 is small, which easily results in a large contact resistance between the via interconnection structure 6 and the interconnection line 3, and thus results in poor interconnection performance of the device.

In order to solve the technical problem, in the method for forming a semiconductor structure provided by the embodiment of the invention, the through hole interconnection structure is contacted with part of the top of the conductive functional layer, and the through hole interconnection structure can be partially positioned on the end part of the conductive functional layer, which is close to the blocking structure, so that the degree of freedom of layout design of the through hole interconnection structure is improved; in addition, in the step of forming the through hole, the top dielectric layer located above the junction position of the blocking structure and the conductive functional layer and part of the blocking structure on the side wall of the conductive functional layer are etched, so that the through hole also exposes part of the side wall of the conductive functional layer, accordingly, in the process of forming the through hole interconnection structure, the through hole interconnection structure is not only in contact with part of the top of the conductive functional layer, but also in contact with part of the side wall of the conductive functional layer, that is, the through hole interconnection structure covers the corner of the top of the conductive functional layer adjacent to the blocking structure, which is beneficial to increasing the contact area between the through hole interconnection structure and the conductive functional layer, thereby reducing the contact resistance between the through hole interconnection structure and the conductive functional layer, and further improving the performance of the semiconductor structure.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Fig. 2 to 19 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Referring to fig. 2, a substrate 100 is provided. The substrate 100 is used to provide a process platform for subsequent processing.

In this embodiment, a semiconductor device such as a transistor or a capacitor may be formed in the substrate 100, and a functional structure such as a resistor structure or a conductive structure may be formed in the substrate 100.

Referring to fig. 2 to 16 in combination, a plurality of conductive functional layers 110 (shown in fig. 14) extending in a first direction (shown in an x-direction in fig. 2) and sequentially arranged in a second direction (shown in a y-direction in fig. 2) in a bottom dielectric layer 101, a bottom dielectric layer 101 (shown in fig. 14) on the substrate 100 between the conductive functional layers 110, and blocking structures 120 (shown in fig. 11) in the conductive functional layers 110 are formed on the substrate 100, the blocking structures 120 dividing the conductive functional layers 110 located on both sides of the blocking structures 120 in the first direction. In this embodiment, the second direction is perpendicular to the first direction.

The bottom dielectric layer 101 is used to achieve electrical isolation between the conductive functional layers 110.

In this embodiment, the bottom dielectric layer 101 is an inter-metal dielectric (INTER METAL DIELECTRIC, IMD) layer, and the bottom dielectric layer 101 is used to realize electrical isolation between adjacent interconnect structures in a Back end of line (BEOL) process. For this purpose, the material of the bottom dielectric layer 101 is a low-k dielectric material (low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less), an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant of less than 2.6), silicon oxide, silicon nitride, silicon oxynitride, or the like.

The bottom dielectric layer 101 has a single-layer structure or a multi-layer structure. As an example, the bottom dielectric layer 101 is a single-layer structure, and the material of the bottom dielectric layer 101 is an ultra-low k dielectric material, so as to reduce parasitic capacitance between the back-end interconnection structures, thereby reducing the back-end RC delay. In particular, the ultra-low k dielectric material may be SiOCH.

In this embodiment, the bottom dielectric layer 101 is further formed between the conductive functional layer 110 and the substrate 100, and between the blocking structure 120 and the substrate 100.

In this embodiment, the bottom dielectric layer 101 exposes the top surfaces of the conductive functional layer 110 and the blocking structure 120. The bottom dielectric layer 101 exposes the top surface of the conductive functional layer 110 for subsequent formation of other interconnect structures electrically connected to the conductive functional layer 110.

Accordingly, in the present embodiment, the conductive functional layer 110 is an interconnection line 110, and the bottom dielectric layer 101 is used to achieve electrical isolation between adjacent interconnection lines 110.

The interconnect lines 110 are used to make electrical connection between the substrate 100 and external circuitry or other interconnect structures. As an example, the interconnection line 110 is a single-layer structure, and the material of the interconnection line 110 is copper. The resistivity of copper is lower, which is beneficial to improving the signal delay of the back RC, improving the processing speed of the chip, reducing the resistance of the interconnection line and correspondingly reducing the power consumption. In other embodiments, the material of the interconnection line may be conductive material such as cobalt, tungsten, aluminum, etc., and the interconnection line may be a multi-layer structure.

In this embodiment, the bottom dielectric layer 101 and the interconnect line 110 are formed on the substrate 100 as an example. In a practical process, one or more dielectric layers can be formed between the bottom dielectric layer 101 and the substrate 100, and each dielectric layer can have an interconnection line or a conductive plug formed therein.

The blocking structure 120 is used to divide the conductive functional layer 110 along the first direction, so that the conductive functional layer 110 is disconnected at a position where interconnection is not required, and the pattern of the conductive functional layer 110 meets the design requirement.

Moreover, the subsequent steps further comprise: forming a top dielectric layer covering the blocking structure 120, the conductive functional layer 110, and the bottom dielectric layer 101; etching the top dielectric layer above the junction of the blocking structure 120 and the conductive functional layer 110 and a portion of the blocking structure 120 on the sidewall of the conductive functional layer 110 to form a via hole penetrating the top dielectric layer and exposing a portion of the top and a portion of the sidewall of the conductive functional layer 110; the via hole is filled with a via hole interconnection structure that is in contact with a portion of the top and a portion of the sidewall of the conductive functional layer 110.

In this embodiment, the blocking structure 120 includes an etching stop layer 122 and a liner layer 121 between the etching stop layer 122 and the sidewall of the conductive functional layer 110, and the liner layer 121 is also formed at the bottom of the etching stop layer 122.

By including the etching stop layer 122 and the pad layer 121 in the blocking structure 120, the pad layer 121 located on the side wall of the conductive functional layer 110 can be etched in the subsequent process of forming the through hole, wherein the etching stop layer 122 can define an etching stop position in the process of forming the through hole, the etching selection of the top dielectric layer and the etching stop layer 122 by the process of etching the top dielectric layer is relatively high, the etching selection of the pad layer 121 and the etching stop layer 122 by the process of etching the pad layer 121 is relatively high, the probability of misetching the etching of the etching stop layer 122 by the process of etching the top dielectric layer and the pad layer 121 is low, which is beneficial to reducing the probability that the through hole located on one side of the blocking structure 120 exposes the conductive functional layer 110 located on the other side of the blocking structure 120, and correspondingly, the probability that the through hole interconnection structure and the adjacent conductive functional layer 110 are short-circuited is relatively low, so that the subsequent through hole interconnection structure can be partially dropped on the end part of the conductive functional layer 110 close to the blocking structure 120, thereby being beneficial to improving the layout design freedom of the through hole interconnection structure, and being beneficial to increasing the process window of the through hole interconnection structure.

The material of the liner layer 121 includes one or more of silicon oxide, silicon nitride, aluminum oxide, titanium oxide, nitrogen doped silicon carbide, carbon doped silicon oxide, and silicon carbide. The liner layer 121 is made of a dielectric material, which is advantageous in reducing the influence on the performance of the semiconductor structure, while ensuring that the blocking structure 120 is capable of electrically isolating the conductive functional layers 110 located on both sides of the blocking structure 120 in the first direction.

In this embodiment, the material of the liner layer 121 is silicon oxide. Silicon oxide is a dielectric material which is easily obtained and commonly used in the semiconductor process, is beneficial to improving the process compatibility and reducing the process cost, has lower dielectric constant, is beneficial to reducing the parasitic capacitance between the conductive functional layers 110, and is correspondingly beneficial to improving the TDDB characteristics.

The material of etch stop layer 122 includes one or more of silicon oxide, silicon nitride, aluminum oxide, titanium oxide, nitrogen doped silicon carbide, carbon doped silicon oxide, and silicon carbide. The etch stop layer 122 and liner layer 121 are of different materials. In this embodiment, the etching stop layer 122 is alumina. In the subsequent etching process of forming the through hole, the etching process has a larger etching selection ratio to the material of the top dielectric layer, the alumina and the silica and the alumina, so that the etching stop layer 122 can play a role in defining the etching stop position.

In this embodiment, the blocking structure 120 includes an etching stop layer 122 and a liner layer 121 between the etching stop layer 122 and the sidewall of the conductive functional layer 110, and the liner layer 121 is also formed at the bottom of the etching stop layer 122 as an example.

In other embodiments, the blocking structure can further include an etch stop layer and a liner layer between the etch stop layer and the conductive functional layer sidewall. In this embodiment, the liner layer is located only between the etch stop layer and the sidewalls of the conductive feature layer, i.e., the etch stop layer has a greater thickness, which advantageously increases the effect of the etch stop layer in defining the etch stop location of the etch process for forming the via, and correspondingly further increases the process window for forming the via interconnect structure.

The present embodiment takes the blocking structure 120 as an example of a multi-layer structure. In other embodiments, the blocking structure may also be a single layer structure.

The steps of forming the interconnection line 110, the bottom dielectric layer 101, and the blocking structure 120 according to this embodiment are described in detail below with reference to the accompanying drawings.

Referring to fig. 2 and 3, fig. 2 is a top view, and fig. 3 is a cross-sectional view taken along line a-a in fig. 2, a bottom dielectric layer 101 is formed on a substrate 100. In this embodiment, a deposition process is used to form the bottom dielectric layer 101. Specifically, the deposition process includes a chemical vapor deposition process, a plasma enhanced deposition process, and the like.

With continued reference to fig. 2 and 3, a plurality of hard mask layers 105 extending in a first direction and sequentially arranged in a second direction are formed on the bottom dielectric layer 101.

The hard mask layer 105 is used as a mask for subsequent etching of the bottom dielectric layer 101 to form interconnect trenches. Wherein the interconnect trench is used to provide a spatial location for forming the interconnect line. In this embodiment, the bottom dielectric layer 101 is an inter-metal dielectric layer, and the hard mask layer is a metal hard mask layer correspondingly.

In this embodiment, the material of the hard mask layer 105 is silicon nitride. In other embodiments, the material of the hard mask layer may be silicon oxide, silicon oxynitride, silicon carbide, titanium oxide, titanium nitride, tantalum oxide, tantalum nitride, boron nitride, copper nitride, aluminum nitride, or tungsten nitride.

The hard mask layer 105 can be formed by patterning processes such as a self-aligned double patterning process (SADP), a self-aligned quadruple patterning process (SAQP), and the like.

Referring to fig. 4 to 8, the bottom dielectric layer 101 between portions of adjacent hard mask layers 105 is etched in the second direction, forming blocking trenches 10 (shown in fig. 8) surrounded by the hard mask layers 105 and the bottom dielectric layer 101. The blocking slot 10 is used to provide space for forming a blocking structure.

In the present embodiment, the step of forming the blocking groove 10 includes: as shown in fig. 4 to 7, fig. 4 and 6 are top views, and fig. 5 and 7 are cross-sectional views taken along line a-a in fig. 4 and 6, respectively, a pattern layer 130 covering the hard mask layer 105 is formed on the bottom dielectric layer 101, and mask openings 20 exposing portions of the top surface of the bottom dielectric layer 101 and sidewalls of the hard mask layer 105 between adjacent hard mask layers 105 are formed in the pattern layer 130 along a second direction; as shown in fig. 8, the bottom dielectric layer 101 is etched to a partial thickness where the mask opening 20 is exposed, using the pattern layer 130 as a mask, thereby forming the blocking trench 10.

The patterned layer 130 is used as a mask for etching the bottom dielectric layer 101 to form the blocking trenches 10. Thus, the pattern and position of the pattern layer 130 define the pattern and position of the blocking slot 10. In this embodiment, the material of the graphics layer 130 includes Spin-On Carbon (SOC). The spin-on carbon has good filling performance, and the spin-on carbon can be formed by a spin-on process, which is beneficial to reducing the difficulty and the process cost of forming the pattern layer 130. In other embodiments, the material of the graphics layer may be other suitable materials.

In this embodiment, the step of forming the graphic layer 130 includes: as shown in fig. 4 and 5, a fill layer 111 is formed on the bottom dielectric layer 101 to cover the hard mask layer 105; forming an anti-reflection coating 112 on the filling layer 111; forming a photoresist layer 113 on the anti-reflection coating layer 112; as shown in fig. 6 and 7, the photoresist layer 113 is used as a mask, and the anti-reflection coating 112 and the filling layer 111 are sequentially etched to form a mask opening 20, and the remaining filling layer 111 is used as a pattern layer 130.

The fill layer 111 is used to form the patterned layer 130, and the fill layer 111 is also used to provide a planar surface for forming the anti-reflective coating 112 and the photoresist layer 113.

In this embodiment, the anti-reflection coating 112 is used to reduce the reflection effect at the time of exposure, thereby improving the transfer accuracy of the pattern. In this embodiment, the anti-reflective coating 112 is a Si-ARC layer, which is beneficial to increasing the depth of field (DOF) of exposure during the photolithography process, improving the uniformity of exposure, and is rich in silicon, so that the hardness of the anti-reflective coating 112 is also improved, thereby further improving the transfer accuracy of the pattern. In other embodiments, the anti-reflective coating may also be other suitable anti-reflective materials, such as: BARC (Bottom Anti-REFLECTIVE COATING ).

The photoresist layer 113 is used as a mask for etching the fill layer 111 to form the mask opening 20. The material of the photoresist layer 113 is photoresist. The photoresist layer 113 can be formed by a photolithography process such as photoresist coating, exposure, development, and the like. In this embodiment, an anisotropic dry etching process is used, and the photoresist layer 113 is used as a mask to sequentially etch the anti-reflection coating 112 and the filling layer 111.

In this embodiment, an anisotropic dry etching process is used, and the pattern layer 130 is used as a mask to etch the bottom dielectric layer 101 with a thickness of a portion of the bottom dielectric layer 101 exposed by the mask opening 20, thereby forming the blocking trench 10. The anisotropic dry etching process has the characteristic of anisotropic etching, is beneficial to improving the accuracy of pattern transfer, and ensures that the pattern of the blocking groove 10 meets the design requirement.

In this embodiment, in the step of etching the bottom dielectric layer 101 with the pattern layer 130 as a mask and the portion of the thickness exposed by the mask opening 20, the photoresist layer 113 is gradually consumed, and thus, after the blocking trench 10 is formed, the photoresist layer 113 is removed.

Referring to fig. 9 to 11, the blocking structure 120 filled in the blocking groove 10 is formed.

The blocking structure 120 is used in conjunction with the hard mask layer 105 as a mask for subsequent etching of the bottom dielectric layer 101 to form interconnect trenches. Wherein the blocking structure 120 in the bottom dielectric layer 101 is further used to split the interconnect lines on both sides of the blocking structure 120 in the first direction.

In this embodiment, the step of forming the blocking structure 120 includes: as shown in fig. 9 and 10, a blocking film 123 filling the blocking groove 10 is formed, the blocking film 123 being further formed on the sidewalls of the mask opening 20 and the top of the pattern layer 130; as shown in fig. 11, the blocking film 123 and the pattern layer 130 higher than the hard mask layer 105 are removed, and the remaining blocking film 123 located in the blocking trench 10 serves as a blocking structure 120.

In this embodiment, the blocking structure 120 includes an etching stop layer 122 and a liner layer 121 between the etching stop layer 122 and the sidewall of the conductive functional layer. Thus, in the step of forming the blocking structure 120, the blocking structure 120 includes a liner layer 121 located at the sidewall of the blocking trench 10, and an etch stop layer 122 located on the liner layer 121 and filling the blocking trench 10.

In this embodiment, taking the blocking structure 120 including the etching stop layer 122 and the liner layer 121 as an example, the step of forming the blocking structure 120 includes: as shown in fig. 9, a pad film 1211 is formed on the bottom and side walls of the blocking groove 10, the side walls of the mask opening 20, and the top surface of the pattern layer 130; as shown in fig. 10, an etching stopper film 1221 which is provided on the pad film 1211 and fills the blocking groove 10 is formed, and the etching stopper film 1221 and the pad film 1211 are used to constitute the blocking film 123; as shown in fig. 11, the etching stopper film 1221, the spacer film 1211 and the pattern layer 130 higher than the hard mask layer 105 are removed, the remaining etching stopper film 1221 located in the blocking trench 10 serves as the etching stopper layer 122, and the remaining spacer film 1211 located in the blocking trench 10 serves as the spacer layer 121.

The spacer film 1211 is used to form the spacer layer 121. In this embodiment, the process of forming the pad film 1211 includes an atomic layer deposition process. The atomic layer deposition process has a high step coverage capability, which is advantageous in ensuring that the liner film 1211 can be formed on the bottom and side walls of the blocking groove 10, the side walls of the mask opening 20, and the top surface of the pattern layer 130, and in improving the thickness uniformity and the film deposition quality of the liner film 1211.

In this embodiment, a liner film 1211 is formed on the anti-reflective coating 112 on the graphic layer 130.

The process of forming the etching stopper film 1221 includes one or both of an atomic layer deposition process and a spin coating process. In this embodiment, the etching stopper film 1221 is formed by an atomic layer deposition process. The gap filling performance and the step coverage capability of the atomic layer deposition process are better, so that the coverage capability of the etching stop film 1221 at the bottom and the side wall of the blocking groove 10 is improved, and the atomic layer deposition process comprises multiple atomic layer deposition cycles to form a film layer with a required thickness, so that the uniformity and the compactness of the thickness of the etching stop film 1221 are improved, the thickness of the etching stop film 1221 can be accurately controlled, and meanwhile, the effect of the etching stop film 1221 for defining the etching stop position is also improved. Wherein, in the process of forming the etching stopper film 1221, as the thickness of the deposition material gradually increases, the etching stopper film 1221 on the pad film 1211 located at the sidewall of the blocking groove 10 gradually contacts, so that the etching stopper film 1221 fills in the blocking groove 10.

In other embodiments, the process of forming the etch stop film may further include a spin-on process, depending on the actual process. The spin coating process is simple to operate, and is beneficial to improving the filling capability of the etching stop film in the blocking groove.

In this embodiment, the formation of the pad film 1211 is followed by the formation of the etching stopper film 1221 as an example. In other embodiments, the step of forming the blocking structure further comprises: after forming the liner film and before forming the etching stopper film, the etching stopper film is removed at the bottom of the blocking groove and the top surface of the pattern layer. By removing the etching stop film positioned at the bottom of the blocking groove and the top surface of the pattern layer, the etching stop film can be contacted with the bottom of the blocking groove in the process of forming the etching stop film, which is beneficial to increasing the formation depth of the etching stop layer and correspondingly improving the effect of defining the etching stop position of the etching stop layer in the subsequent etching process of forming the through hole.

In this embodiment, the top surface of the hard mask layer 105 is used as a stop position to etch the etching stop film 1221, the pad film 1211 and the pattern layer 130, which is beneficial to reducing the difficulty of the process of forming the blocking structure 120.

In this embodiment, the etching stopper film 1221, the pad film 1211, and the pattern layer 130 higher than the hard mask layer 105 are removed by a dry etching process. Specifically, the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has the characteristic of anisotropic etching, and is beneficial to improving etching precision.

Referring to fig. 12 in combination, after forming the blocking structure 120 and before forming the interconnection trench, the method for forming a semiconductor structure further includes: the pattern layer 130 is removed exposing the bottom dielectric layer 101 between the hard mask layers 105.

Exposing the bottom dielectric layer 101 between the hard mask layers 105, in preparation for subsequent etching of the bottom dielectric layer 101 using the hard mask layers 105 and the blocking structures 120 as masks. In this embodiment, one or both of an ashing process and a wet photoresist removal process is used to remove the pattern layer 130.

Referring to fig. 13, a portion of the bottom dielectric layer 105 is etched to form an interconnect trench 30 in the bottom dielectric layer 101 using the hard mask layer 105 and the blocking structure 120 as masks.

The interconnect trench 30 is used to provide space for forming interconnect lines.

In this embodiment, the blocking structure 120 is formed first, then the hard mask layer 105 and the blocking structure 120 are used as masks, and the bottom dielectric layer 105 with partial thickness is etched to form the interconnection trench 30, accordingly, in the process of forming the interconnection trench 30, the blocking structure 120 is correspondingly made to divide the interconnection trench 30 located at two sides of the blocking structure along the first direction, so that the blocking structure 120 is self-aligned to the interconnection trench 30; in addition, after the interconnection line 110 is formed in the interconnection trench 30, the interconnection line 110 located at two sides of the blocking structure 120 along the first direction is divided by the blocking structure 120, so that a step of etching the interconnection line 110 is not required, the material of the interconnection line 110 is usually a metal material, the etching process of the metal material is difficult, and the step of etching the interconnection line 110 is omitted, so that the process difficulty is reduced.

In this embodiment, an anisotropic dry etching process is used to etch a portion of the bottom dielectric layer 105 to form the interconnect trench 30 in the bottom dielectric layer 101. By adopting the anisotropic dry etching process, the controllability of the etching profile is facilitated to be improved, the accuracy of pattern transfer is also facilitated to be improved, and the pattern of the interconnection trench 30 is correspondingly facilitated to meet the design requirement.

After the interconnect trench 30 is formed, the interconnect trench 30 located on both sides of the blocking structure 120 in the first direction is isolated by the blocking structure 120.

In this embodiment, the bottom of the interconnect trench 30 is flush with the bottom of the blocking structure 120 as an example. In other embodiments, the bottom of the interconnect trench may also be lower or higher than the bottom of the blocking structure. Accordingly, when the bottom of the interconnect trench is lower than the bottom of the blocking structure, the interconnect trench located on both sides of the blocking structure in the first direction is isolated by the blocking structure and the bottom dielectric layer of the bottom of the blocking structure.

In this embodiment, the method for forming a semiconductor structure further includes: the hard mask layer 105 is removed and the blocking structure 120 is higher than the bottom dielectric layer 101.

As an example, after forming the interconnect trench 30, the hard mask layer 105 and the blocking structure 120 above the bottom dielectric layer 101 are removed before forming the interconnect line in the interconnect trench 30.

By removing the hard mask layer 105 and the blocking structure 120 above the bottom dielectric layer 101 prior to forming the interconnect lines in the interconnect trench 30, the interconnect lines do not need to be formed between the hard mask layer 105 during subsequent interconnect line formation, which is advantageous in reducing the depth of the interconnect lines that need to be filled, thereby improving the filling capability and filling quality of the interconnect lines in the interconnect trench 30.

In this embodiment, one or both of dry etching and wet etching are used to remove the hard mask layer 105 and the blocking structure 120 above the bottom dielectric layer 101.

In other embodiments, the hard mask layer and the blocking structure above the bottom dielectric layer can also be removed during the formation of the interconnect lines, depending on the actual process. Specifically, the process of forming the interconnection line includes a step of removing the conductive layer higher than the bottom dielectric layer by using a planarization process (e.g., a chemical mechanical polishing process), and removing the hard mask layer and the blocking structure higher than the bottom dielectric layer during the step of removing the conductive layer higher than the bottom dielectric layer by using the planarization process.

Referring to fig. 14 and 16, fig. 14 is a top view, fig. 15 is a cross-sectional view taken along line a-a in fig. 14, and fig. 16 is a cross-sectional view taken along line b-b in fig. 14, an interconnect line 110 is formed in the interconnect trench 30.

In this embodiment, the step of forming the interconnection line 110 includes: forming a conductive layer (not shown) filled in the interconnection trench 30, the conductive layer also being formed on the bottom dielectric layer 101 and the blocking structure 120; the conductive layer above the bottom dielectric layer 101 is removed and the remaining conductive layer in the interconnect trench 30 is used as interconnect line 110.

It should be noted that the steps of forming the bottom dielectric layer 101, the interconnection line 110, and the blocking structure 120 in this embodiment are only taken as an example. The steps of forming the bottom dielectric layer, the interconnect line and the blocking structure are not limited thereto, and in other embodiments, other suitable processes may be used to form the bottom dielectric layer, the interconnect line and the blocking structure according to actual process requirements.

Referring to fig. 17, a top dielectric layer 140 is formed overlying the bottom dielectric layer 101, the conductive functional layer 110, and the blocking structure 120.

The subsequent steps further comprise: forming a via hole penetrating the top dielectric layer 140 and exposing a portion of the top and a portion of the sidewall of the conductive functional layer 110; forming a via in top dielectric layer 140; and filling the through hole interconnection structure in the through hole. The top dielectric layer 140 is used to achieve electrical isolation between the via interconnect structures.

In this embodiment, the top dielectric layer 140 is also an inter-metal dielectric (IMD) layer.

In this embodiment, the top dielectric layer 140 is the same material as the bottom dielectric layer 101.

Specifically, a deposition process is employed, such as: a chemical vapor deposition process forms top dielectric layer 140.

Referring to fig. 18, a top dielectric layer 140 located over the interface of the blocking structure 120 and the conductive feature 110, and a portion of the blocking structure 120 located on the sidewall of the conductive feature 110 are etched to form a via 40 that extends through the top dielectric layer 140 and exposes a portion of the top and a portion of the sidewall of the conductive feature 110.

Vias 40 are used to provide a spatial location for forming via interconnect structures.

In this embodiment, the top dielectric layer 140 above the junction between the blocking structure 120 and the conductive functional layer 110 is etched, so that the subsequently formed via interconnection structure can be partially located on the end of the conductive functional layer 110 near the blocking structure 120, which is beneficial to improving the degree of freedom of layout design of the via interconnection structure.

In addition, in this embodiment, the partial blocking structure 120 located on the sidewall of the conductive functional layer 110 is further etched, so that the via 40 is further exposed from the partial sidewall of the conductive functional layer 110, and thus, in the subsequent process of forming the via interconnection structure, the via interconnection structure is not only in contact with the partial top of the conductive functional layer 110, but also in contact with the partial sidewall of the conductive functional layer 110, that is, the via interconnection structure covers the corner of the conductive functional layer 110 adjacent to the blocking structure 120, which is beneficial to increasing the contact area between the via interconnection structure and the conductive functional layer 110, thereby being beneficial to reducing the contact resistance between the via interconnection structure and the conductive functional layer 110, and further being beneficial to improving the performance of the semiconductor structure.

In this embodiment, in the process of forming the via hole 40, the etching stop layer 122 can be used to define the stop position of etching, so as to reduce the probability of erroneous etching of the etching stop layer 122 caused by the etching process for forming the via hole 40, and correspondingly reduce the probability that the via hole 40 on one side of the blocking structure 120 exposes the conductive functional layer 110 on the other side of the blocking structure 120, thereby being beneficial to preventing the problem of shorting between the via hole interconnection structure and the adjacent conductive functional layer, not only being beneficial to increasing the process window for forming the via hole 40, but also being beneficial to improving the reliability of the semiconductor structure.

In the step of forming the via hole 40 in this embodiment, a portion of the via hole 40 located between the conductive functional layer 110 and the blocking structure 120 serves as a sub-via hole.

In the first direction, the opening width of the sub-via is not too small nor too large. If the opening width of the sub-via is too small, then in the subsequent step of forming the via interconnection structure filling the via 40, the difficulty of filling the via interconnection structure in the sub-via is greater; if the opening width of the sub-via is too large, it is easy to cause the remaining width of the blocking structure 120 located at the side wall of the sub-via to be too small, which tends to increase the risk of shorting or breakdown of the via interconnection structure with the adjacent conductive functional layer 110. For this reason, in the present embodiment, the opening width of the sub-via is 5nm to 50nm in the first direction.

The depth of the sub-through holes should not be too small nor too large. If the depth of the sub-via is too small, the sidewall area of the conductive functional layer 110 exposed by the via 40 is correspondingly too small, which easily results in an insignificant effect of increasing the contact area of the via interconnect structure with the conductive functional layer 110; if the depth of the sub-via is too large, the blocking structure 120 on the sidewall of the sub-via is likely to have too small a volume, and thus the risk of shorting or breakdown between the via interconnection structure and the adjacent conductive functional layer 110 is likely to be increased. For this reason, in this embodiment, the depth of the sub-via is 2nm to 50nm.

In the present embodiment, the step of forming the through hole 40 includes: etching the top dielectric layer 140 above the junction of the blocking structure 120 and the conductive functional layer 110 to form an initial via (not labeled) extending through the top dielectric layer 140, wherein a portion of the conductive functional layer 110 and the blocking structure 120 are exposed at the bottom of the initial via; the blocking structure 120 at the bottom of the initial via is etched to expose a portion of the sidewall of the conductive functional layer 110 adjacent to the blocking structure 120, thereby forming the via 40.

In this embodiment, an anisotropic dry etching process is used to etch the top dielectric layer 140 above the boundary between the blocking structure 120 and the conductive functional layer 110, so as to form an initial via.

After the initial via is formed, the blocking structure 120 at the bottom of the initial via is etched using one or both of a wet etching process and a dry etching process.

In this embodiment, in the step of forming the via hole, a portion of the pad layer 121 located on the sidewall of the conductive functional layer 110 is etched. The material of the liner layer 121 is different from that of the etching stop layer 122, and the partial liner layer 121 on the side wall of the conductive functional layer 10 is etched, so that the probability of misetching the etching stop layer 122 is reduced, the etching stop layer 122 can define the etching stop position, the blocking structure 120 is prevented from being etched through by the etching process to expose the adjacent conductive functional layer 110, the process reliability is improved, and the process risk is reduced.

In this embodiment, an etching process is used to etch a portion of the pad layer 121 on the sidewall of the conductive functional layer 110, and the etching selectivity of the etching process to the pad layer 121 and the etching stop layer 122 is at least 3:1. The etching process has larger etching selection on the liner layer 121 and the etching stop layer 122, which is beneficial to further reducing the probability of causing false etching on the etching stop layer 122, thereby ensuring that the etching stop layer 122 can play a role in defining the etching stop position.

Referring to fig. 19, a via interconnect structure 150 is filled in the via, and the via interconnect structure 150 is in contact with a portion of the top and a portion of the sidewall of the conductive functional layer 110.

The via interconnect structure 150 is used to make electrical connection between the conductive functional layer 110 and other interconnect structures or external circuits. Specifically, in the present embodiment, the via interconnection structure 150 is used to make electrical connection between the interconnection line 110 and other interconnection structures or external circuits.

In the process of forming the via interconnection structure 150, the via interconnection structure 150 is not only in contact with a portion of the top of the conductive functional layer 110, but also in contact with a portion of the sidewall of the conductive functional layer 110, that is, the via interconnection structure 150 covers the corner of the top of the conductive functional layer 110 adjacent to the blocking structure 120, which is beneficial to increasing the contact area between the via interconnection structure 150 and the conductive functional layer 110, thereby reducing the contact resistance between the via interconnection structure 150 and the conductive functional layer 110, and further improving the performance of the semiconductor structure.

In this embodiment, the via interconnect structure 150 includes: a first portion 151 located in a portion of the width blocking structure 120 of the conductive functional layer 110 sidewall and in contact with a portion of the conductive functional layer 110 sidewall, and a second portion 152 connected to the first portion 151 and located on the first portion 151, penetrating through the top dielectric layer 140 above the junction of the blocking structure 120 and the conductive functional layer 110 and in contact with a portion of the top of the conductive functional layer 110.

In this embodiment, the first portion 151 is located in the liner layer 121 on the sidewall of the conductive functional layer 110.

As can be seen from the foregoing, by forming the etching stop layer 122, the probability that the via 40 exposes the adjacent conductive functional layer 110 or that the via 40 is too close to the adjacent conductive functional layer 110 is reduced, and therefore, the probability that the via interconnect structure 150 and the adjacent conductive functional layer 110 have a short circuit or breakdown problem is low, thereby improving the degree of freedom of layout design of the via interconnect structure 150 and simultaneously being beneficial to ensuring the reliability and stability of the semiconductor structure.

In this embodiment, the material of the via interconnection structure 150 is copper, which is favorable for improving the signal delay of the back-end RC, increasing the processing speed of the chip, and reducing the power consumption. In other embodiments, the material of the via interconnection structure may also be a conductive material such as aluminum, tungsten, or cobalt.

In this embodiment, the step of forming the via interconnect structure 150 includes: forming a layer of conductive material (not shown) filled in the via 40, the layer of conductive material also covering the top dielectric layer 140; the conductive material layer is planarized with the top surface of the top dielectric layer 140 as a stop location and the remaining conductive material layer serves as a via interconnect structure 150.

The process of forming the conductive material layer includes one or more of an atomic layer deposition process, a physical vapor deposition process, a chemical vapor deposition process, and an electrochemical plating process.

In this embodiment, a chemical mechanical polishing (CHEMICALLY-MECHANICALLY POLISHING, CMP) process is used to planarize the conductive material layer, which is advantageous for improving the top surface planarity of the via interconnect structure 150.

Fig. 20 to 23 are schematic structural views corresponding to steps in another embodiment of a method for forming a semiconductor structure according to the present invention. The points of the present embodiment that are the same as those of the foregoing embodiment are not described in detail here, and the difference between the present embodiment and the foregoing embodiment is that: the conductive functional layer is a metal gate, and the bottom dielectric layer is an interlayer dielectric layer.

Referring to fig. 20, a substrate 200 is provided.

In this embodiment, the base 200 includes a substrate 21 and a plurality of fins 22 separated from the substrate 21, the fins 22 extend along the second direction, and the base 200 includes a gate partition C, and a first device unit area I and a second device unit area II respectively located at two sides of the gate partition C.

In this embodiment, the substrate 21 is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates.

In this embodiment, the material of the fin 22 is the same as the material of the substrate 21, and the material of the fin 22 is silicon.

The substrate 200 includes a first device unit area I and a second device unit area II adjacent to each other, and a gate dividing area C is located at the junction of the first device unit area I and the second device unit area II and is used for defining a dividing position of a gate, so that the gates of the different device unit areas can be separated from each other subsequently.

An isolation layer 23 is further formed on the substrate 21, the isolation layer 23 covers part of the side wall of the fin 22, and the top surface of the isolation layer 23 is lower than the top surface of the fin 22. The isolation layer 23 serves to isolate adjacent devices from each other. In this embodiment, the material of the isolation layer 23 is silicon oxide.

With continued reference to fig. 20, a plurality of conductive functional layers 210 extending in a first direction and sequentially arranged in a second direction, a bottom dielectric layer 201 on the substrate 200 between the conductive functional layers 210, and blocking structures 220 in the conductive functional layers 210 are formed on the substrate 200, the blocking structures 220 dividing the conductive functional layers 210 located on both sides of the blocking structures 220 in the first direction.

In this embodiment, the conductive functional layer 210 is a metal gate 210.

The metal gate 210 is used to control the turning on or off of the conductive channel during device operation. In this embodiment, metal gate 210 spans across the plurality of fins 22 and covers portions of the top and portions of the sidewalls of fins 22.

In the present embodiment, the metal gate 210 is formed on the isolation layer 23.

The metal gate 210 includes a high-k gate dielectric layer (not shown), a work function layer (not shown) on the high-k gate dielectric layer, and a gate electrode layer (not shown) on the work function layer.

In this embodiment, the bottom dielectric layer 201 is an interlayer dielectric layer (ILD) that is used to realize isolation between adjacent metal gates 210.

In this embodiment, a bottom dielectric layer 201 is formed on the spacer layer 23 between the metal gates 210. The material of the bottom dielectric layer 201 is an insulating material.

In this embodiment, the blocking structure 220 is formed on the gate partition C. The blocking structure 220 is used to divide the metal gate 210 of the first device cell region I and the metal gate 210 of the second device cell region II.

Specifically, the blocking structure 220 is formed on the isolation layer 23 of the gate division region C.

In this embodiment, the blocking structure 220 includes an etching stop layer 222 and a liner layer 221 between the etching stop layer 222 and the sidewall of the metal gate 210. In this embodiment, the liner layer 221 is also formed at the bottom of the etch stop layer 222. For the related descriptions of the blocking structure 220, the etch stop layer 222 and the liner layer 221, reference may be made to the corresponding descriptions in the foregoing embodiments, and the description of this embodiment is omitted here.

In this embodiment, in the first direction, a first distance d1 is between blocking structure 220 and fin 22 of first device cell region I closest to blocking structure 220, a second distance d2 is between blocking structure 220 and fin 22 of second device cell region II closest to blocking structure 220, and second distance d2 is smaller than first distance d1, that is, the distance between fin 22 of second device cell region II closest to blocking structure 220 and blocking structure 220 is smaller, the distance between the sidewall of metal gate 210 of second device cell region II and fin 22 closest to blocking structure 220 is smaller, the step of forming metal gate 210 includes the process of filling metal gate 210 in the exposed gate opening of blocking structure 220, the smaller distance between fin 22 of second device cell region II closest to blocking structure 220 and blocking structure 220 may easily result in poor filling capability of metal gate 210 in the gap between blocking structure 220 and fin 22 of second device cell region II closest to blocking structure 220 during formation of metal gate 210, poor filling quality or less filling of gate 210 in the gap between blocking structure 220 and fin 22 of second device cell region II closest to blocking structure 220, thereby causing the turn-on voltage of the device formed by fin 22 of second device cell region II closest to blocking structure 220 and metal gate 210 to be different from the turn-on voltage of the device formed by fin 22 of first device cell region I closest to blocking structure 220 and metal gate 210, for example: the turn-on voltage of the device formed by the fin of the second device cell region II closest to the blocking structure 220 and the metal gate 210 is higher, resulting in a shift in the turn-on voltage of the fin 22 of the second device cell region II closest to the blocking structure 220.

Referring to fig. 21, a top dielectric layer 230 is formed overlying the bottom dielectric layer 201, the conductive functional layer 210, and the blocking structure 220. The top dielectric layer 230 is used to achieve electrical isolation between the via interconnect structures.

For the description of the top dielectric layer 230, reference may be made to the corresponding description in the foregoing embodiments, and this embodiment will not be repeated here.

Referring to fig. 22, a top dielectric layer 230 located over the interface of the blocking structure 220 and the conductive feature 210, and a portion of the blocking structure 220 located on the sidewall of the conductive feature 210 are etched to form a via 41 that extends through the top dielectric layer 230 and exposes a portion of the top and a portion of the sidewall of the conductive feature 210.

In this embodiment, in the step of forming the via hole 41, the top dielectric layer 230 located above the junction between the gate partition region C and the second device unit region II and the partial blocking structure 220 located on the sidewall of the metal gate 210 of the second device unit region II are etched, so as to form the via hole 41 exposing a portion of the top and a portion of the sidewall of the metal gate 210 of the second device unit region II.

In the step of forming the through hole 41, the method of forming a semiconductor structure further includes: the top dielectric layer 230, which is located in the first device unit area I and is close to the blocking structure 220, is etched to form a contact hole 42, and the contact hole 42 is surrounded by the top surface of the metal gate 210 of the first device unit area I and the top dielectric layer 230.

In this embodiment, along the first direction, the second distance d2 (as shown in fig. 20) is smaller than the first distance d1 (as shown in fig. 20), the turn-on voltage of the device corresponding to the fin 22 of the second device unit area II closest to the blocking structure 220 is different from the turn-on voltage of the device corresponding to the fin 22 of the first device unit area I closest to the blocking structure 220, and the turn-on voltage of the device corresponding to the fin 22 of the second device unit area II closest to the blocking structure 220 is shifted.

In this embodiment, after the via 41 exposes a portion of the top and a portion of the sidewall of the metal gate 210 of the second device unit area II, so that the via interconnect structure is formed in the via 41, the via interconnect structure can be further contacted with a portion of the sidewall of the metal gate 210 of the second device unit area II in addition to the portion of the top of the metal gate 210 of the second device unit area II, which is beneficial to increasing the contact area between the via interconnect structure and the metal gate 210 of the second device unit area II, and the etching depth of the via 41 can be adjusted, so that the area of the top and the sidewall of the metal gate 210 exposed by the via 41 is larger than the area of the top of the metal gate 210 exposed by the contact hole 42, so that the contact area between the via interconnect structure and the metal gate 210 of the second device unit area II is larger, and the material of the via interconnect structure is generally made of a metal material having a work function.

For specific process steps of forming the through hole 41 in this embodiment, please refer to corresponding descriptions in the foregoing embodiments, and the description of this embodiment is omitted here.

Referring to fig. 23, a via interconnect structure 250 is filled in the via 41, and the via interconnect structure 250 is in contact with a portion of the top and a portion of the sidewall of the conductive functional layer 210.

In this embodiment, the via interconnect structure 250 includes: a first portion 251 located in a portion of the width blocking structure 220 of the sidewall of the conductive functional layer 210 and in contact with a portion of the sidewall of the conductive functional layer 210, and a second portion 252 connected to the first portion 251 and located on the first portion 251, extending through the top dielectric layer 230 above the junction of the blocking structure 220 and the conductive functional layer 210 and in contact with a portion of the top of the conductive functional layer 210.

In this embodiment, in the step of forming the via interconnection structure 250, the method for forming a semiconductor structure further includes: the contact hole 42 is filled with a contact hole plug 260, and the bottom of the contact hole plug 260 is in contact with the top surface of the metal gate 210 of the first device unit region I.

In this embodiment, in the step of forming the via interconnection structure 250, the via interconnection structure 250 is in contact with a portion of the sidewall and a portion of the top surface of the metal gate 210 of the second device cell region II, and the via interconnection structure 250 is used to adjust the work function of the metal gate 210 of the second device cell region II.

In this embodiment, along the first direction, the second distance d2 (as shown in fig. 20) is smaller than the first distance d1 (as shown in fig. 20), the turn-on voltage of the device corresponding to the fin 22 of the second device unit area II closest to the blocking structure 220 is different from the turn-on voltage of the device corresponding to the fin 22 of the first device unit area I closest to the blocking structure 220, and the turn-on voltage of the fin 22 of the second device unit area II closest to the blocking structure 220 is shifted.

In this embodiment, in addition to contacting the top of the portion of the metal gate 210 of the second device cell region II, the via interconnection structure 250 can also contact the side wall of the portion of the metal gate 210 of the second device cell region II, which is advantageous for increasing the contact area between the via interconnection structure 250 and the metal gate 210 of the second device cell region II, and the present embodiment can also make the area of the top and the side wall of the metal gate 210 exposed by the via 41 larger than the area of the top of the metal gate 210 exposed by the contact hole 42 by adjusting the etching depth of the via 41, so that the contact area between the via interconnection structure 250 and the metal gate 210 of the second device cell region II is larger than the contact area between the contact hole plug 260 and the metal gate 210 of the first device cell region I, and the material of the via interconnection structure 250 is usually a metal material having a larger contact area between the via interconnection structure 250 and the metal gate 210 of the second device cell region II, thereby making the via interconnection structure 250 function to adjust the work function of the fin structure 22 closest to the blocking structure 220.

For this purpose, in this embodiment, the material of the via interconnection structure 250 is a metal work function material, and the material of the via interconnection structure 250 includes one or more of Cu, taN, ta, ti, tiN, co, ru, ruN, W and Al.

In this embodiment, the material of the contact plug 260 is the same as that of the via interconnect structure 250.

For specific process steps for forming the via interconnection structure 250, reference may be made to the corresponding descriptions in the foregoing embodiments, and the description of this embodiment is omitted here.

For a specific description of the method for forming the semiconductor structure of this embodiment, reference may be made to the corresponding description in the foregoing embodiment, and this embodiment will not be repeated here.

Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 19, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown. Specifically, fig. 19 shows a cross-sectional view along the extending direction of the conductive functional layer.

The semiconductor structure includes: a substrate 100; a plurality of conductive functional layers 110 disposed on the substrate 100, extending along a first direction, and sequentially arranged along a second direction; a bottom dielectric layer 101 on the substrate 101 between the conductive functional layers 110; a blocking structure 120 in the conductive functional layer 110, the blocking structure 120 dividing the conductive functional layer 110 located at both sides of the blocking structure 120 along a first direction; a top dielectric layer 140 overlying the bottom dielectric layer 101, the conductive functional layer 110, and the blocking structure 120; the via interconnect structure 150 includes a first portion 151 located in a portion of the width blocking structure 120 of the conductive functional layer 110 sidewall and in contact with a portion of the sidewall of the conductive functional layer 110, and a second portion 152 connected to the first portion 151 and located on the first portion 151, penetrating through the top dielectric layer 140 above the junction of the blocking structure 120 and the conductive functional layer 110 and in contact with a portion of the top of the conductive functional layer 110.

The via interconnection structure 150 includes a first portion 151 located in the partial width blocking structure 120 of the sidewall of the conductive functional layer 110 and contacting a portion of the sidewall of the conductive functional layer 110, and a second portion 152 connected to the first portion 151 and located on the first portion 151, penetrating the top dielectric layer 140 above the junction of the blocking structure 120 and the conductive functional layer 110 and contacting a portion of the top of the conductive functional layer 110, that is, the via interconnection structure 150 contacts not only a portion of the top of the conductive functional layer 110 but also a portion of the sidewall of the conductive functional layer 110, that is, the via interconnection structure 150 covers a corner of the conductive functional layer 110 adjacent to the blocking structure 120, which is advantageous for increasing the contact area of the via interconnection structure 150 and the conductive functional layer 110, thereby reducing the contact resistance of the via interconnection structure 150 and the conductive functional layer 110, and thus improving the performance of the semiconductor structure.

The substrate 100 provides a process platform for a process recipe. The substrate 100 may have a semiconductor device such as a transistor or a capacitor formed therein, and the substrate 100 may have a functional structure such as a resistor structure or a conductive structure formed therein.

In this embodiment, the bottom dielectric layer 101 is an inter-metal dielectric layer, and the bottom dielectric layer 101 is used to realize electrical isolation between adjacent interconnection structures in the back-end-of-line process. As an example, the bottom dielectric layer 101 has a single-layer structure, and the material of the bottom dielectric layer 101 is an ultra-low k dielectric material.

Accordingly, in the present embodiment, the conductive functional layer 110 is an interconnection line 110, and the bottom dielectric layer 101 is used to achieve electrical isolation between adjacent interconnection lines 110. The interconnect lines 110 are used to make electrical connection between the substrate 100 and external circuitry or other interconnect structures.

As an example, the conductive functional layer 110 has a single-layer structure, and the material of the conductive functional layer 110 is copper.

The blocking structure 120 is used to divide the conductive functional layer 110 along the first direction, so that the conductive functional layer 110 is disconnected at a position where interconnection is not required, and the pattern and electrical connection performance of the conductive functional layer 110 meet the design requirements. In this embodiment, the second direction is perpendicular to the first direction.

In this embodiment, the blocking structure 120 includes an etching stop layer 122 and a liner layer 121 between the etching stop layer 122 and the sidewall of the conductive functional layer 110, and the liner layer 121 also covers the bottom of the etching stop layer 122. Accordingly, the first portion 151 is located in the liner layer 121 of the sidewall of the conductive functional layer 110.

The forming step of the via interconnect structure 150 includes: etching the top dielectric layer 140 located above the junction of the blocking structure 120 and the conductive functional layer 110, and a portion of the blocking structure 120 located on the sidewall of the conductive functional layer 110, to form a via hole penetrating the top dielectric layer 140 and exposing a portion of the top and a portion of the sidewall of the conductive functional layer 110; the via interconnect structure 150 is filled in the via.

By including the etch stop layer 122 and the pad layer 121 in the blocking structure 120, the pad layer 121 on the side wall of the conductive functional layer 110 can be etched in the process of forming the through hole, wherein the etch stop layer 122 can define an etching stop position in the process of forming the through hole, the etching selection of the top dielectric layer 140 to the etching of the top dielectric layer 140 and the etch stop layer 122 is relatively high, the etching selection of the pad layer 121 to the pad layer 121 and the etching stop layer 122 is relatively high, the etching probability of the etching of the top dielectric layer 140 and the pad layer 121 to the etching stop layer 122 is low, which is beneficial to reducing the probability that the through hole on one side of the blocking structure 120 exposes the conductive functional layer 110 on the other side of the blocking structure 120, and correspondingly, the probability that the through hole interconnection structure 150 and the adjacent conductive functional layer 110 have a short circuit or breakdown problem is relatively low, so that the through hole interconnection structure 150 can partially fall on the end of the conductive functional layer 110 close to the blocking structure 120, thereby being beneficial to improving the degree of freedom of layout design of the through hole interconnection structure 150 and improving the reliability and stability of the semiconductor structure.

In this embodiment, the material of the liner layer 121 is silicon oxide.

In other embodiments, the blocking structure can further include an etch stop layer, and a liner layer between the etch stop layer and the conductive functional layer sidewall. In this embodiment, the liner layer is located only between the etch stop layer and the sidewalls of the conductive feature layer, i.e., the etch stop layer has a greater thickness, which advantageously increases the effect of the etch stop layer in defining the etch stop location of the etch process for forming the via, and correspondingly further increases the process window for forming the via interconnect structure.

The top dielectric layer 140 is used to achieve electrical isolation between the via interconnect structures 150.

In this embodiment, the top dielectric layer 140 is also an inter-metal dielectric layer.

The via interconnect structure 150 is used to make electrical connection between the interconnect line 120 and other interconnect structures or external circuits. In this embodiment, the material of the via interconnect structure 150 is copper.

In this embodiment, the width of the first portion 151 is 5nm to 50nm in the first direction.

In this embodiment, the height of the first portion 151 is 2nm to 50nm.

The semiconductor structure may be formed by the forming method of the foregoing embodiment, or may be formed by other forming methods. For a specific description of the semiconductor structure of the present embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.

Referring to fig. 23, a schematic structural diagram of another embodiment of the semiconductor structure of the present invention is shown. The points of the present embodiment that are the same as those of the foregoing embodiments are not repeated, and the difference between the present embodiment and the foregoing embodiments is that:

The base 200 includes a substrate 21 and a plurality of fins 22 separated from the substrate 21, the fins 22 extending along a second direction, and the base 200 includes a gate partition C, and a first device unit area I and a second device unit area II respectively located at two sides of the gate partition C.

In this embodiment, the substrate 21 is a silicon substrate; the material of fin 22 is silicon.

The substrate 21 is further formed with an isolation layer 23 covering part of the sidewalls of the fin 22, the top surface of the isolation layer 23 being lower than the top surface of the fin 22. The isolation layer 23 serves to isolate adjacent devices from each other. In this embodiment, the material of the isolation layer 23 is silicon oxide.

The substrate 200 includes a first device unit area I and a second device unit area II adjacent to each other, and a gate division area C is formed at the junction of the first device unit area I and the second device unit area II and is used for defining division positions of the gate electrodes 210, so that the metal gate electrodes 210 of different device unit areas can be separated.

The conductive functional layer 210 is a metal gate 210, and the bottom dielectric layer 201 is an interlayer dielectric layer 201.

The metal gate 210 is used to control the turning on or off of the conductive channel during device operation.

Metal gate 210 spans across the plurality of fins 22 and covers portions of the top and portions of the sidewalls of fins 22.

In this embodiment, the metal gate 210 is formed on the isolation layer 23.

In this embodiment, the bottom dielectric layer 201 is an interlayer dielectric layer (ILD) for isolating adjacent metal gates 210. In this embodiment, the material of the bottom dielectric layer 201 is silicon oxide.

In this embodiment, the blocking structure 220 is located on the gate partition C. The blocking structure 220 is used to divide the metal gate 210 of the first device cell region I and the metal gate 210 of the second device cell region II.

Specifically, the blocking structure 220 is located on the isolation layer 23 of the gate division region C.

In this embodiment, the blocking structure 220 includes an etch stop layer 222 and a liner layer 221 between the etch stop layer 222 and the sidewall of the metal gate 210. In this embodiment, the pad layer 221 also covers the bottom of the etching stop layer 222. For the related descriptions of the blocking structure 220, the etch stop layer 222 and the liner layer 221, reference may be made to the corresponding descriptions in the foregoing embodiments, and the description of this embodiment is omitted here.

In this embodiment, in the first direction, blocking structure 220 has a first distance d1 (as shown in fig. 20) from fin 22 of first device cell region I closest to blocking structure 220, blocking structure 220 has a second distance d2 (as shown in fig. 20) from fin 22 of second device cell region II closest to blocking structure 220, second distance d2 being smaller than first distance d1, that is, the distance between fin 22 of second device cell region II closest to blocking structure 220 and blocking structure 220 is smaller, the distance between the sidewall of metal gate 210 of second device cell region II to fin 22 closest to blocking structure 220 is smaller, the step of forming metal gate 210 includes the process of filling metal gate 210 in the exposed gate opening of blocking structure 220, the smaller distance between fin 22 of second device cell region II closest to blocking structure 220 and blocking structure 220 may easily result in poor filling capability of metal gate 210 in the gap between blocking structure 220 and fin 22 of second device cell region II closest to blocking structure 220 during formation of gate 210, poor filling quality or less filling of metal gate 210 in the gap between blocking structure 220 and fin 22 of second device cell region II closest to blocking structure 220, and thus the turn-on voltage of the device formed by fin 22 of second device cell region II closest to blocking structure 220 and metal gate 210 may be different from the turn-on voltage of the device formed by fin 22 of first device cell region I closest to blocking structure 220 and metal gate 210, for example: the turn-on voltage of the device formed by the fin of the second device cell region II closest to the blocking structure 220 and the metal gate 210 is higher, resulting in a shift in the turn-on voltage of the fin 22 of the second device cell region II closest to the blocking structure 220.

The top dielectric layer 230 is used to achieve electrical isolation between the via interconnect structures. For the description of the top dielectric layer 230, reference may be made to the corresponding description in the foregoing embodiments, and the description is omitted here.

In this embodiment, the via interconnect structure 250 includes: a first portion 251 located in a portion of the width blocking structure 220 of the sidewall of the conductive functional layer 210 and in contact with a portion of the sidewall of the conductive functional layer 210, and a second portion 252 connected to the first portion 251 and located on the first portion 251, extends through the top dielectric layer 230 above the junction of the blocking structure 220 and the conductive functional layer 210 and in contact with a portion of the top of the conductive functional layer 210.

The semiconductor structure further includes: the contact hole plug 260 penetrates through the top dielectric layer 230 located in the first device unit area I near the blocking structure 220, and the bottom of the contact hole plug 260 contacts with the top surface of the metal gate 210 of the first device unit area I.

In this embodiment, the via interconnection structure 250 is located in the top dielectric layer 230 above the boundary position between the gate partition region C and the second device unit region II and the partial blocking structure 220 of the sidewall of the metal gate 210 of the second device unit region II, and contacts a portion of the sidewall and a portion of the top surface of the metal gate 210 of the second device unit region II, and the via interconnection structure 250 is used to adjust the work function of the metal gate 210 of the second device unit region II.

In this embodiment, along the first direction, the second distance d2 is smaller than the first distance d1, the turn-on voltage of the device formed by the fin 22 of the second device unit area II closest to the blocking structure 220 and the metal gate 210 is different from the turn-on voltage of the device formed by the fin 22 of the first device unit area I closest to the blocking structure 220 and the metal gate 210, and the turn-on voltage of the fin 22 of the second device unit area II closest to the blocking structure 220 is offset.

In this embodiment, in addition to being in contact with the top portion of the metal gate 210 of the second device cell region II, the via interconnection structure 250 can also be in contact with a portion of the sidewall of the metal gate 210 of the second device cell region II, which is advantageous for increasing the contact area of the via interconnection structure 250 with the gate 210 of the second device cell region II, and the present embodiment can also make the area of the top and sidewall of the metal gate 210 exposed by the via 41 larger than the area of the top portion of the metal gate 210 exposed by the contact hole 42 by adjusting the etching depth of the via 41, so that the contact area of the via interconnection structure 250 with the gate 210 of the metal of the second device cell region II is larger than the contact area of the contact hole plug 260 with the metal gate 210 of the first device cell region I, the material of the via interconnection structure 250 is typically a metal material having a work function that is adjusted by making the contact area of the via interconnection structure with the gate 210 of the second device cell region II larger than the work function of the fin 22 of the second device cell region II closest to the blocking structure 220.

The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein in the step of providing the substrate, the substrate comprises a substrate and a plurality of fins separated on the substrate;

Forming a plurality of conductive functional layers extending along a first direction and sequentially arranged along a second direction on the substrate, a bottom dielectric layer positioned on the substrate between the conductive functional layers, and a blocking structure positioned in the conductive functional layers, wherein the blocking structure divides the conductive functional layers positioned on two sides of the blocking structure along the first direction, the conductive functional layers are metal grids, and the metal grids span across a plurality of fin parts and cover partial top parts and partial side walls of the fin parts;

the fin part extends along a second direction, and the substrate comprises a gate division region, and a first device unit region and a second device unit region which are respectively positioned at two sides of the gate division region;

Forming a top dielectric layer covering the bottom dielectric layer, the conductive functional layer and the blocking structure;

etching a top dielectric layer positioned above the junction position of the blocking structure and the conductive functional layer and a part of the blocking structure positioned on the side wall of the conductive functional layer to form a through hole penetrating through the top dielectric layer and exposing a part of the top and a part of the side wall of the conductive functional layer; etching a top dielectric layer positioned above the junction position of the gate division region and the second device unit region and a part of the blocking structure positioned on the side wall of the metal gate of the second device unit region in the step of forming the through hole to form a through hole exposing part of the top and part of the side wall of the metal gate of the second device unit region;

filling a through hole interconnection structure in the through hole, wherein the through hole interconnection structure is contacted with part of the top and part of the side wall of the conductive functional layer; in the step of forming the via interconnection structure, the via interconnection structure is in contact with a part of a side wall and a part of a top surface of the metal gate of the second device unit region, and the via interconnection structure is used for adjusting a work function of the metal gate of the second device unit region.

2. The method of claim 1, wherein the conductive functional layer is a gate electrode and the bottom dielectric layer is an interlayer dielectric layer;

or the conductive functional layer is an interconnection line, and the bottom dielectric layer is an inter-metal dielectric layer.

3. The method of forming a semiconductor structure of claim 1, wherein the blocking structure comprises an etch stop layer and a liner layer between the etch stop layer and the conductive feature sidewall; or the blocking structure comprises an etching stop layer and a liner layer positioned between the etching stop layer and the side wall of the conductive functional layer, and the liner layer is also formed at the bottom of the etching stop layer;

And etching part of the liner layer on the side wall of the conductive functional layer in the step of forming the through hole.

4. The method of claim 3, wherein etching is performed on a portion of the pad layer on the sidewall of the conductive functional layer by an etching process, and wherein the etching process has an etching selectivity to the pad layer and the etch stop layer of at least 3:1.

5. The method of forming a semiconductor structure of claim 1, wherein the step of forming the via comprises: etching a top dielectric layer above the junction of the blocking structure and the conductive functional layer to form an initial through hole penetrating through the top dielectric layer, wherein the bottom of the initial through hole exposes part of the conductive functional layer and the blocking structure;

etching the blocking structure at the bottom of the initial through hole, and exposing a part of the side wall of the conductive functional layer adjacent to the blocking structure to form the through hole.

6. The method of claim 5, wherein the blocking structure at the bottom of the initial via is etched using one or both of a wet etch process and a dry etch process.

7. The method of forming a semiconductor structure of claim 1, wherein the bottom dielectric layer is an interlayer dielectric layer;

The blocking structure is formed on the gate partition area, a first distance is arranged between the blocking structure and a fin part, closest to the blocking structure, of the first device unit area along the first direction, a second distance is arranged between the blocking structure and a fin part, closest to the blocking structure, of the second device unit area, and the second distance is smaller than the first distance;

In the step of forming the through hole, the method for forming the semiconductor structure further includes: etching a top dielectric layer which is positioned in the first device unit area and is close to the blocking structure to form a contact hole, wherein the contact hole is formed by the top surface of a metal grid electrode of the first device unit area and the top dielectric layer in a surrounding mode;

In the step of forming the via interconnection structure, the method for forming a semiconductor structure further includes: and filling a contact hole plug in the contact hole, wherein the bottom of the contact hole plug is contacted with the top surface of the metal gate of the first device unit area.

8. The method of forming a semiconductor structure of claim 1, wherein the conductive functional layer is an interconnect line and the bottom dielectric layer is an inter-metal dielectric layer;

The step of forming the interconnection line, the bottom dielectric layer and the blocking structure comprises the following steps: forming a bottom dielectric layer on the substrate; forming a plurality of hard mask layers which extend along the first direction and are sequentially arranged along the second direction on the bottom dielectric layer; etching a part of the bottom dielectric layer between adjacent hard mask layers along the second direction to form a blocking groove surrounded by the hard mask layer and the bottom dielectric layer; forming the blocking structure filled in the blocking groove; etching the bottom dielectric layer with partial thickness by taking the hard mask layer and the blocking structure as masks, and forming an interconnection groove in the bottom dielectric layer; forming the interconnection line in the interconnection trench; and removing the hard mask layer and the blocking structure higher than the bottom dielectric layer.

9. The method of forming a semiconductor structure of claim 8, wherein the step of forming the blocking trench comprises: forming a graph layer covering the hard mask layer on the bottom dielectric layer, wherein mask openings exposing partial top surfaces of the bottom dielectric layers and side walls of the hard mask layers between adjacent hard mask layers along the second direction are formed in the graph layer; etching the bottom dielectric layer with the exposed part of the mask opening by taking the pattern layer as a mask to form the blocking groove;

the step of forming the blocking structure includes: forming a blocking film filling the blocking groove, wherein the blocking film is also formed on the side wall of the mask opening and the top of the pattern layer; removing the blocking film and the pattern layer which are higher than the hard mask layer, and taking the residual blocking film in the blocking groove as the blocking structure;

after forming the blocking structure and before forming the interconnection trench, the method for forming the semiconductor structure further comprises the following steps: and removing the graph layer to expose the bottom dielectric layer between the hard mask layers.

10. The method of forming a semiconductor structure of claim 9, wherein the blocking structure comprises an etch stop layer and a liner layer between the etch stop layer and the conductive feature sidewall;

The step of forming the blocking structure includes: forming a liner film on the bottom and side walls of the blocking groove, the side walls of the mask opening and the top surface of the pattern layer; forming an etching stop film which is positioned on the liner film and filled in the blocking groove, wherein the etching stop film and the liner film are used for forming the blocking film; and removing the etching stop film, the lining film and the pattern layer which are higher than the hard mask layer, wherein the residual etching stop film in the blocking groove is used as the etching stop layer, and the residual lining film in the blocking groove is used as the lining layer.

11. The method of forming a semiconductor structure of claim 10, wherein the step of forming the blocking structure further comprises: after forming the liner film and before forming the etching stopper film, the liner film located at the bottom of the blocking groove and the top surface of the pattern layer is removed.

12. The method of forming a semiconductor structure of claim 11, wherein the process of forming the liner film comprises an atomic layer deposition process;

The process of forming the etching stopper film includes one or both of an atomic layer deposition process and a spin-on process.

13. A semiconductor structure, comprising:

A base including a substrate and a plurality of fins discrete on the substrate;

the conductive functional layers are arranged on the substrate, extend along the first direction and are sequentially arranged along the second direction, the conductive functional layers are metal grids, and the metal grids span across the fin parts and cover part of the top and part of the side walls of the fin parts;

the bottom dielectric layer is positioned on the substrate between the conductive functional layers;

a blocking structure in the conductive functional layer, the blocking structure dividing the conductive functional layer located at both sides of the blocking structure along the first direction;

The top dielectric layer is covered on the bottom dielectric layer, the conductive functional layer and the blocking structure;

the through hole interconnection structure comprises a first part, a second part and a third part, wherein the first part is positioned in the partial width blocking structure of the side wall of the conductive functional layer and is contacted with the partial side wall of the conductive functional layer, the second part is connected with the first part and positioned on the first part, penetrates through the top dielectric layer above the junction position of the blocking structure and the conductive functional layer and is contacted with the partial top of the conductive functional layer;

The through hole interconnection structure is positioned in the blocking structure at a part of the top dielectric layer above the junction position of the gate partition region and the second device unit region and the side wall of the metal gate of the second device unit region, and is contacted with the side wall and the top surface of the part of the metal gate of the second device unit region, and the through hole interconnection structure is used for adjusting the work function of the metal gate of the second device unit region.

14. The semiconductor structure of claim 13, wherein the conductive functional layer is a gate and the bottom dielectric layer is an interlayer dielectric layer;

15. The semiconductor structure of claim 13, wherein the blocking structure comprises an etch stop layer, and a liner layer between the etch stop layer and the conductive functional layer sidewall; or the blocking structure comprises an etching stop layer and a liner layer positioned between the etching stop layer and the side wall of the conductive functional layer, and the liner layer also covers the bottom of the etching stop layer;

the first portion is located in the liner layer of the conductive feature side wall.

16. The semiconductor structure of claim 13, wherein the bottom dielectric layer is an interlayer dielectric layer;

The blocking structure is located on the gate partition area, a first distance is reserved between the blocking structure and a fin part, closest to the blocking structure, of the first device unit area along the first direction, a second distance is reserved between the blocking structure and a fin part, closest to the blocking structure, of the second device unit area, and the second distance is smaller than the first distance;

The semiconductor structure further includes: and the contact hole plug penetrates through the dielectric layer at the top of the first device unit area, which is close to the blocking structure, and the bottom of the contact hole plug is contacted with the top surface of the metal grid electrode of the first device unit area.

17. The semiconductor structure of claim 16, wherein the material of the via interconnect structure is a metal work function material, the material of the via interconnect structure comprising one or more of Cu, taN, ta, ti, tiN, co, ru, ruN, W and Al.

18. The semiconductor structure of claim 15, wherein the liner layer and etch stop layer materials comprise one or more of silicon oxide, silicon nitride, aluminum oxide, titanium oxide, nitrogen doped silicon carbide, carbon doped silicon oxide, and silicon carbide.

19. The semiconductor structure of claim 13, wherein a width of the first portion along the first direction is 5nm to 50nm.

20. The semiconductor structure of claim 13, wherein a height of the first portion is 2nm to 50nm.