CN113745329A - GaN-based thermoelectric transistor on self-supporting substrate and preparation method thereof - Google Patents

GaN-based thermoelectric transistor on self-supporting substrate and preparation method thereof Download PDF

Info

Publication number
CN113745329A
CN113745329A CN202110864585.1A CN202110864585A CN113745329A CN 113745329 A CN113745329 A CN 113745329A CN 202110864585 A CN202110864585 A CN 202110864585A CN 113745329 A CN113745329 A CN 113745329A
Authority
CN
China
Prior art keywords
gan
region
emitter
base
passivation layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110864585.1A
Other languages
Chinese (zh)
Inventor
马晓华
祝杰杰
张颖聪
王鹏飞
宓珉瀚
郝跃
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xidian University
Original Assignee
Xidian University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xidian University filed Critical Xidian University
Priority to CN202110864585.1A priority Critical patent/CN113745329A/en
Publication of CN113745329A publication Critical patent/CN113745329A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/7606—Transistor-like structures, e.g. hot electron transistor [HET]; metal base transistor [MBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66931—BJT-like unipolar transistors, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunneling transistor [RTT], bulk barrier transistor [BBT], planar doped barrier transistor [PDBT], charge injection transistor [CHINT]
    • H01L29/66939—BJT-like unipolar transistors, e.g. hot electron transistors [HET], metal base transistors [MBT], resonant tunneling transistor [RTT], bulk barrier transistor [BBT], planar doped barrier transistor [PDBT], charge injection transistor [CHINT] with an active layer made of a group 13/15 material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

The invention relates to a GaN-based thermoelectric transistor on a self-supporting substrate and a preparation method thereof, wherein the GaN-based thermoelectric transistor comprises: collector, n + GaN self-supporting substrate, and AlyGa1‑yN collector region, GaN base region, base electrode, and AlxGa1‑xN emitter region, N + GaN cap layer, emitter electrode, passivation layer, collector electrode, N + GaN self-supporting substrate, and AlyGa1‑yN collector region, GaN base region, and AlxGa1‑xSequentially laminating an N emitting region and an N + GaN cap layer, and AlxGa1‑xN emitter region and N + GaN cap layer forming tableA face structure; the passivation layer is arranged on the electric isolation structure, the GaN base region and the AlxGa1‑xThe N emitting region and the surface of the N + GaN cap layer; the upper end of the base electrode is positioned on the surface of the passivation layer on the GaN base region and is contacted with the passivation layer on the side surface of the mesa structure, and the lower end of the base electrode is positioned in the passivation layer and is contacted with the GaN base region; the upper end of the emitter is positioned on the surface of the passivation layer on the mesa structure, and the lower end of the emitter is positioned in the passivation layer and is in contact with the n + GaN cap layer. The GaN-based thermoelectric transistor has the advantages of large collector current, high breakdown field strength, low defect density of epitaxial materials and the like, and can play a better role in working performance.

Description

GaN-based thermoelectric transistor on self-supporting substrate and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a GaN-based thermoelectric transistor on a self-supporting substrate and a preparation method thereof.
Background
Because of its excellent characteristics of large forbidden band width, high breakdown field strength, high electronic saturation velocity, high thermal conductivity, etc., GaN material is an important material for the development of high-temperature high-power electronic devices and high-frequency microwave devices.
Currently, the field of high-frequency high-power devices mainly uses a High Electron Mobility Transistor (HEMT) with a transverse structure as a main component. The high-concentration two-dimensional electron gas (2DEG) generated by polarization effect at the AlGaN/GaN heterojunction interface is utilized to work, and the HEMT device obtains great development in the field of high-frequency power devices due to high carrier mobility and high current density. However, as a lateral structure device, the frequency characteristic of the HEMT is limited by the gate length and the electron saturation velocity, and when the device structure size is reduced, it must be scaled down in both the lateral and vertical directions, which makes the process difficult. In addition, the lateral GaN transistor also suffers from surface electron trap problems, and especially when the device is operated under high voltage conditions, the current collapse phenomenon caused by the problems can seriously degrade the device performance, thereby adversely affecting the device reliability and long-term stability.
While the vertical structure device can effectively overcome the problems of the lateral device, the GaN-based Heterojunction Bipolar Transistor (HBT) is one of the research focuses of the nitride-based vertical device. Compared with a GaN HEMT device, the HBT has the inherent advantages of good linearity, high current, high power density and the like, and is very suitable for manufacturing high-power and high-frequency microwave power devices. However, due to the low hole mobility and carrier concentration, this results in a very large base extension resistance in the GaN-based HBT device, which makes the GaN-based HBT device limited in application in high speed applications.
In recent years, with the continuous maturation of iii-v compound semiconductor material epitaxial fabrication technology, a Hot Electron Transistor (HET) device having a vertical structure has become an important choice in the field of high frequency devices. The basic working principle is that high-energy hot electrons are injected from an emitter and pass through a base region in a near ballistic transport mode, and finally reach a collector region to be collected. Since high-energy hot electrons have a high velocity (near ballistic transport) when passing through the base region, the device has a good frequency characteristic, and the thickness of the base region must be in the order of several nanometers to prevent elastic scattering and relaxation of the thermally injected electrons. Early HET devices mainly adopt a semiconductor-metal-semiconductor structure, but because of the serious scattering of phonons in metal to electrons, the energy of hot electrons is lost, and the thickness of metal cannot be very thin, otherwise, the leakage can be caused by the perforation effect, so the performance of the early HET devices is very unsatisfactory. To solve the problems of metal-based hot electron transistors, Levi et al first reported HET devices using semiconductor material InAs as base material and related characteristics in 1987, and the current gain is only 10.
In 2011, Sansaptak Dasgupta et al realized a HET device on a gallium nitride material, and the device structure mainly consisted of an AlGaN (24%) emitter region, a 10nmGaN base region, and an AlGaN (8%) collector region, where all epitaxial layers were grown by a radio frequency plasma molecular beam epitaxy method (RFPMBE), and after the growth was completed, HRXRD was used to perform careful calibration and measurement on the thickness. The report proves that the current injection mechanism is a thermal emission mechanism, the gain of the common base current is finally 0.97-0.98, but the common emitter work of the device cannot be realized.
In 2016, the Zhichao Yang et al manufactured HET devices on GaN substrates, and the basic structures of the HET devices are an n + + GaN emitting region, an i-GaN/i-AlN emitter-base junction barrier, an n + + GaN base region, an i-AlGaN collector-base junction barrier and an n + GaN collector region. The current leakage problem of the HET device is researched, the polarization barrier engineering is adopted to reduce the leakage current, and the device co-emission current gain is finally realized to be 14.5.
GaN-based thermoelectric transistors are an important choice in the field of future high-frequency power devices, and have certain advantages in terms of integration and reliability compared with other devices because of the quality of materials, and the related reports of the devices in the past are few, but as GaN epitaxial growth technology is mature, the devices are expected to become research hotspots in the field of high-frequency devices in the future. Therefore, it is an urgent need to design a unipolar vertical GaN hot electron transistor.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a GaN-based thermoelectric transistor on a free-standing substrate and a method for fabricating the same. The technical problem to be solved by the invention is realized by the following technical scheme:
an embodiment of the present invention provides a GaN-based thermoelectric transistor on a self-supporting substrate, including: collector, n + GaN self-supporting substrate, and AlyGa1-yN collector region, GaN base region, base electrode, and AlxGa1-xAn N emitter region, an N + GaN cap layer, an emitter, and a passivation layer, wherein,
the collector, the n + GaN self-supporting substrate, and the AlyGa1-yN collector region, GaN base region, and AlxGa1-xThe N emission region and the N + GaN cap layer are sequentially stacked, and the Al layerxGa1-xThe N emission region and the N + GaN cap layer form a mesa structure;
the passivation layer is arranged on the electric isolation structure, the GaN base region and the AlxGa1-xThe N emitting region and the surface of the N + GaN cap layer;
the upper end of the base electrode is positioned on the surface of a passivation layer on the GaN base region and is in contact with the passivation layer on the side face of the mesa structure, and the lower end of the base electrode is positioned in the passivation layer and is in contact with the GaN base region;
the upper end of the emitter is located on the surface of the passivation layer on the mesa structure, and the lower end of the emitter is located in the passivation layer and is in contact with the n + GaN cap layer.
In one embodiment of the invention, the n-type doping concentration of the n + GaN self-supporting substrate is 1e18cm-3～8e18cm-3The thickness is 300-400 μm.
In one embodiment of the present invention, the AlyGa1-yThe Al component content y of the N collector region is 5-10%, and the N-type doping concentration is 5e17cm-3～5e18cm-3The thickness is 40 nm-60 nm.
In one embodiment of the invention, the n-type doping concentration 8e of the GaN base region18cm-3～1.5e19cm-3And the thickness is 8 nm-12 nm.
In one embodiment of the present invention, the lower end of the base is located in the passivation layer and embedded in the GaN base region.
In one embodiment of the present invention, the AlxGa1-xThe Al component x of the N emission region is 25-40%, and the N-type doping concentration is 1e18cm-3～1e19cm-3And the thickness is 25 nm-40 nm.
In one embodiment of the present invention, the n-type doping concentration of the n + GaN cap layer is 5e18cm-3～1e19cm-3And the thickness is 10 nm-20 nm.
Another embodiment of the present invention provides a method of fabricating a GaN-based thermoelectric transistor on a free-standing substrate, comprising the steps of:
s1, manufacturing an electric isolation structure of the active region of the device on an epitaxial substrate, wherein the epitaxial substrate comprises an n + GaN self-supporting substrate and Al which are sequentially stackedyGa1-yN collector region, GaN base region, and AlxGa1-xAn N emitting region and an N + GaN cap layer;
s2, etching the n + GaN cap layer and the AlxGa1-xAn N emitter region forming a base region and an emitter region, wherein the emitter region is located on the N + GaN cap layer, and the base is formedThe region is positioned on the GaN base region and surrounds the emitter region;
s3, forming the electrically isolated structure, the GaN base region, and the AlxGa1-xGrowing a passivation layer medium on the N emitting region and the surface of the N + GaN cap layer to form a passivation layer;
s4, etching the passivation layer and the GaN base region of the base region, the passivation layer and the n + GaN cap layer of the emitter region to form a base opening and an emitter opening;
s5, evaporating metal in the base opening, on the passivation layer of the base region, in the emitter opening and on the passivation layer of the emitter region to form a base and an emitter;
and S6, manufacturing a collector on the bottom of the GaN self-supporting substrate.
In one embodiment of the present invention, step S4 includes:
s41, simultaneously etching the passivation layer of the base electrode region and the passivation layer of the emitter electrode region to form a first opening and a second opening;
s42, performing over-etching on the GaN base region in the first opening and the n + GaN cap layer in the second opening simultaneously to form the base opening and the emitter opening.
In one embodiment of the invention, the depth of the over-etching is 0-5 nm.
Compared with the prior art, the invention has the beneficial effects that:
the GaN-based thermoelectric transistor has the advantages of large collector current, high breakdown field strength, low epitaxial material defect density and the like, improves the current gain, common emitter output characteristics and other related electrical characteristics of the conventional thermoelectric transistor, and can exert better working performance.
Drawings
FIG. 1 is a schematic structural diagram of a GaN-based thermoelectric transistor on a free-standing substrate according to an embodiment of the invention;
FIG. 2 is a schematic structural diagram of another GaN-based thermoelectric transistor on a free-standing substrate according to an embodiment of the invention;
FIG. 3 is a schematic diagram illustrating a basic principle of a GaN hot electron transistor device with a top-mounted collector according to an embodiment of the present invention;
FIG. 4 is a schematic flow chart of a method for fabricating a GaN-based thermoelectric transistor on a free-standing substrate according to an embodiment of the invention;
FIGS. 5 a-5 g are schematic process diagrams of a method for fabricating a GaN-based thermoelectric transistor on a free-standing substrate according to an embodiment of the invention;
fig. 6 a-6 h are schematic process diagrams of another method for fabricating a GaN-based thermoelectric transistor on a free-standing substrate according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1 and fig. 2, fig. 1 is a schematic structural diagram of a GaN-based thermoelectric transistor on a free-standing substrate according to an embodiment of the present invention, and fig. 2 is a schematic structural diagram of another GaN-based thermoelectric transistor on a free-standing substrate according to an embodiment of the present invention.
The GaN-based thermoelectric transistor device is of a unipolar vertical structure and comprises a collector electrode 1, a GaN self-supporting substrate 2 and AlyGa1-yN collector region 3, GaN base region 4, base electrode 5 and AlxGa1-x N emitter region 6, N + GaN cap layer 7, emitter 8 and passivation layer 9.
Wherein, the collector 1, the GaN self-supporting substrate 2, and AlyGa1-yN collector region 3, GaN base region 4, AlxGa1-xThe N emitting region 6 and the N + GaN cap layer 7 are sequentially laminated, and AlxGa1-xThe N emitting region 6 and the N + GaN cap layer 7 form a mesa structure; the passivation layer 9 is positioned on the electric isolation structure, the GaN base region 4 and the AlxGa1-xThe N emitting region 6 and the N + GaN cap layer 7; the upper end of the base electrode 5 is positioned on the surface of a passivation layer 9 on the GaN base region 4 and surrounds the passivation layer 9 on the side surface of the mesa structure, and the lower end of the base electrode is positioned in the passivation layer 9 and is in contact with the GaN base region 4; the upper end of the emitter 8 is positioned on the mesa structureThe upper passivation layer 9 surface, the lower end is located in the passivation layer 9 and contacts the n + GaN cap layer 7.
Specifically, AlxGa1-xThe widths of the N emitting region 6 and the N + GaN cap layer 7 are equal and smaller than those of the rest epitaxial layers, so that a mesa structure is formed; wherein the emitter region is located on the mesa structure and the base region is located on the GaN base region 4 around the mesa structure.
The passivation layer 9 covers the surface of the device, i.e. the passivation layer 9 covers the surface of the electrical isolation structure, the upper surface of the GaN base region 4, and AlxGa1-xThe side surface of the N emitter region 6, the side surface of the N + GaN cap layer 7, and the upper surface.
Further, the electrical isolation structure 10a in fig. 1 is formed by etching, the electrical isolation structure 10a being such that the surface of the n + GaN free-standing substrate 2, Al, in the deviceyGa1-yThe side surface of the N collector region 3 and the side surface of the GaN base region 4 are covered with the passivation layer 9, thereby covering the surface of the N + GaN self-supporting substrate 2 and AlyGa1-ySide surface of N collector region 3, side surface and upper surface of GaN base region 4, and AlxGa1-xThe side surface of the N emitter region 6, the side surface of the N + GaN cap layer 7, and the upper surface. The electrical isolation structure 10b in FIG. 2 is an implanted isolation region formed by ion implantation and located at AlyGa1-y N collector region 3, GaN base region 4, AlxGa1-xThe side surfaces of the N emitter region 6 and the N + GaN cap layer 7, and thus, the passivation layer 9 covers the upper surface and the side surfaces of the implantation isolation region, the upper surface of the GaN base region 4, and AlxGa1-xThe side surface of the N emitter region 6, the side surface of the N + GaN cap layer 7, and the upper surface.
Further, a passivation layer 9 on the base region is provided with a first opening, and the lower end of the base 5 is located in the first opening, so that the lower end of the base 5 is in contact with the GaN base region 4; the upper end of the base electrode 5 is positioned on the passivation layer 9 of the base region and is in contact with the passivation layer 9 on the side surface of the mesa structure, and a structure surrounding the passivation layer 9 is formed. A second opening is formed in the passivation layer 9 on the emitter region, and the lower end of the emitter 8 is located in the second opening, so that the lower end of the emitter 8 is in contact with the n + GaN cap layer 7; the upper end of the emitter 8 is arranged on the passivation layer 9 on the emitter region.
Furthermore, the lower end of the base electrode 5 can be positioned on the surface of the GaN base region 4, and can also be embedded into the GaN base region 4; the lower end of the emitter 8 may be located on the surface of the n + GaN cap layer 7, or may be embedded in the n + GaN cap layer 7. Preferably, the lower end of the base electrode 5 is embedded in the GaN base region 4, so that a good current control effect can be realized; meanwhile, because the base electrode 5 and the emitter electrode 8 are simultaneously prepared, the lower end of the emitter electrode 8 is also embedded into the n + GaN cap layer 7 for the sake of simple process.
Specifically, the GaN free-standing substrate 2 has an n-type doping concentration of 1e18cm-3～8e18cm-3The thickness is 300-400 μm. Al (Al)yGa1-yThe Al component y of the N collector region 3 is 5-10%, and the N-type doping concentration is 5e17cm-3～5e18cm-3The thickness is 40 nm-60 nm. The GaN base region 4 is highly doped GaN with n-type doping concentration 8e18cm-3～1.5e19cm-3And the thickness is 8 nm-12 nm. Al (Al)xGa1-xThe Al component x of the N emitting region 6 is 25-40%, and the N-type doping concentration is 1e18cm-3～1e19cm-3And the thickness is 25 nm-40 nm. n-type doping concentration 5e of n + GaN cap layer 718cm-3～1e19cm-3And the thickness is 10 nm-20 nm.
The device of this embodiment has two important considerations in design:
1. the base region must be controlled to a thickness of several nanometers to prevent elastic scattering and relaxation of hot electrons during transport, which reduces transport efficiency. Therefore, in this embodiment, the thickness of the GaN base region 4 is set to 8nm to 12nm, and the purpose is to use a nanometer nitride semiconductor as the base region, so as to obtain a high-energy hot electron injection rate and a low base resistance, so that the injected hot electrons can transit the base region in a ballistic transport manner, thereby greatly improving the frequency characteristics and realizing the application of ultra-high frequency.
2. Base-collector barrier (phi B-C)>>25meV to prevent leakage due to base electrons entering collector region, and relaxation to base Fermi level due to the fact that injected electrons with high energy are not reflected by B-C barrierThe base barrier (φ E-B) is larger than the base-collector barrier (φ B-C). Therefore, the present embodiment sets Al according to this principlexGa1-xN emitter region 3, GaN base region 5, and AlyGa1-yThe relevant parameters of the N collector region 6.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating a basic principle of a gan hot electron transistor device with a top collector according to an embodiment of the present invention, wherein E is an emitter, B is a base, and C is a collector. Hot Electron Transistors (HETs) are devices consisting of three electrodes, an emitter E, a base B and a collector C, which are separated by two barriers as shown in fig. 3. The working principle is as follows: when the emitter-base region is forward biased, electrons are injected into the base and gain kinetic energy; as the electron passes through the base region, part of the energy is lost through the inelastic scattering process; when the energy loss is small, electrons can overcome the base-collector barrier to reach the collector, otherwise they will relax to the bottom of the base and be collected by the base; the injected electrons can almost pass through the base region like a trajectory along with the reduction of the thickness of the base electrode in the base region transition process, so that the device has high working speed; the collector acts as an energy filter at the collector edge of the base, which allows hot electrons (high-energy electrons) to pass through, but blocks cold electrons (low-energy electrons), creating an imbalance over a large range, so that electrons scattered in the base are not high enough in energy to pass through the collector and be reflected back, which eventually become part of the group of cold electrons in the base and contribute to the base current. Electrons at the edge of the base collector have sufficient energy to cause them to form a collector current through the collector.
In this embodiment, the HET belongs to the multi-and single-pole type devices, and since the electron mobility is higher than the corresponding hole mobility in most semiconductor systems, the Rb (base resistance) of the HET device is low, and the low Rb value helps to reduce the RC delay associated with the charging of the base-emitter capacitance, thereby increasing the associated frequency characteristic f of the operating transistort/fmax。
In the embodiment, the substrate is a GaN self-supporting substrate, so that the problem of high-density dislocation in the material caused by a heterogeneous substrate is greatly reduced, and the carrier mobility and the thermal conductivity of a device are ensured; a passivation layer is introduced into the device and can be used as a field plate medium at the same time, so that the breakdown voltage of the device is improved; in addition, the collector is arranged at the bottom of the GaN self-supporting substrate, so that the area of the collector is large, and high collector current can be realized compared with the traditional structure.
In summary, the gan thermionic transistor device of the present embodiment has the advantages of large collector current, high breakdown field strength, low defect density of the epitaxial material, and the like, and improves the current gain, common emitter output characteristics, and the like of the conventional thermionic transistor, so that the gan thermionic transistor device can perform better working performance.
Example two
On the basis of the first embodiment, please refer to fig. 4, and fig. 4 is a flowchart illustrating a method for fabricating a GaN-based thermoelectric transistor on a free-standing substrate according to an embodiment of the present invention.
In the embodiment, the GaN self-supporting substrate 2 and Al which are sequentially laminated from bottom to top are selectedyGa1-y N collector region 3, GaN base region 4, AlxGa1-xThe structure of the N emitting region 6 and the N + GaN cap layer 7 is used as an epitaxial substrate.
Specifically, the preparation method of the GaN-based thermoelectric transistor on the self-supporting substrate comprises the following steps:
and S1, manufacturing an electric isolation structure of the active region of the device on the epitaxial substrate.
S11, lithography of electrically isolated regions of the active region on the n + GaN cap layer 7.
S12, etching the n + GaN cap layer 7 and the Al of the electric isolation region in sequence by utilizing an inductively coupled plasma etching process ICPxGa1-xN emitter region 6, GaN base region 4, AlyGa1-yAn N collector region 3 forming an electrical isolation structure 10a of the device active region; the electrically isolating structure 10a enables the surface of the n + GaN free-standing substrate 2, Al, in the deviceyGa1-ySide surface of N collector region 3, side surface of GaN base region 4, and AlxGa1-xThe side surface of the N emitter region 6 and the side surface of the N + GaN cap layer 7 are exposed.
Alternatively, by ion implantationThe process is carried out on the n + GaN cap layer 7 and AlxGa1-xN emitter region 6, GaN base region 4, AlyGa1-yAn electric isolation structure 10b of a device active region is manufactured in the N collector region 3; the electrical isolation structure 10b is an implantation isolation region formed by ion implantation and located at AlyGa1-y N collector region 3, GaN base region 4, AlxGa1-xN emitter region 6 and N + GaN cap layer 7.
S2, etching the n + GaN cap layer 7 of the epitaxial substrate and AlxGa1-xN emitter region 6, forming base region 51 and emitter region 81.
S21, photoetching is carried out on the selected pattern area on the n + GaN cap layer 7.
S22, etching the n + GaN cap layer 7 of the selected pattern area and AlxGa1-xAnd an N emitter region 6, wherein a base region 51 and an emitter region 81 are formed, the etching depth is 35 nm-60 nm, the emitter region 81 formed by etching is positioned on the N + GaN cap layer 7, and the base region 51 is positioned on the GaN base region 4 and surrounds the emitter region 81.
And S3, growing a passivation layer medium on the surfaces of the electric isolation structure, the GaN base region 4, the AlxGa1-xN emitter region 6 and the n + GaN cap layer 7 to form a passivation layer 9.
And S31, cleaning the surface of the device after the active area etching is finished.
S32, growing a passivation layer medium on the surface of the electric isolation structure, the surface of the GaN base region 4, the surface of the AlxGa1-xN emitter region 6 and the surface of the n + GaN cap layer 7 by utilizing an atomic layer deposition ALD or plasma enhanced chemical vapor deposition PECVD process to form a passivation layer 9.
When forming the electrical isolation structure 10a by etching using the ICP process, Al is formed on the upper surface of the n + GaN self-standing substrate 2, i.e., the surface of the electrical isolation structureyGa1-ySide surface of N collector region 3, side surface and upper surface of GaN base region 4, and AlxGa1-xAnd a passivation layer medium is grown on the side surface of the N emitter region 6 and the side surface and the upper surface of the N + GaN cap layer 7 to form a passivation layer 9.
When forming the electrical isolation structure 10b by the ion implantation process, Al is formed on the upper surface and the side surface of the electrical isolation structure, the upper surface of the GaN base region 4xGa1-xN emitter regionAnd a passivation layer medium is grown on the side surface of the n + GaN cap layer 7 and the side surface and the upper surface of the n + GaN cap layer 6 to form a passivation layer 9.
Specifically, the material of the passivation layer 10 includes SiN or Al2O3。
S4, the passivation layer 9 and GaN base region 4 of base region 51, the passivation layer 9 and n + GaN cap layer 7 of emitter region 81 are etched to form base opening 53 and emitter opening 83.
S41, the passivation layer 9 of the base region 51 and the passivation layer 9 of the emitter region 81 are simultaneously etched to form the first opening 52 and the second opening 82.
S42, GaN base region 4 in first opening 52 and n + GaN cap layer 7 in second opening 82 are over-etched simultaneously to form base opening 53 and emitter opening 83.
When the over-etching depth is 0, the base opening 53 is located on the GaN base region 4, and the emitter opening 83 is located on the n + GaN cap layer 7, that is, the first opening 52 and the second opening 82 are the base opening 53 and the emitter opening 83. When the over-etch depth is greater than 0, the base opening 53 is embedded in the GaN base region 4 and the emitter opening 83 is embedded in the n + GaN cap layer 7. Preferably, the over-etching depth is greater than 0, and at this time, the lower end of the base electrode 5 is embedded into the GaN base region 4, so that a better current control effect can be achieved.
S5, metal is evaporated in the base opening 53, on the passivation layer of the base region 51, in the emitter opening 83, on the passivation layer of the emitter region 81, forming the base 5 and the emitter 8.
S51, photoetching an emitter patterning region on the surface of the passivation layer 9 on the n + GaN cap layer 7, and photoetching a base patterning region on the surface of the passivation layer 9 on the GaN base region 4.
S52, evaporating metal on the passivation layer 9 of the emitter patterning region, in the emitter opening 83, on the passivation layer 9 of the base patterning region, and in the base opening 53 by using an electron beam evaporation process to form the base 5 and the emitter 8.
S6, a collector 1 is formed on the bottom of the GaN free-standing substrate 2.
The preparation process of the gallium nitride hot electron transistor device is compatible with the existing process, has low cost and is beneficial to realizing the large-scale preparation of the gallium nitride hot electron transistor device.
EXAMPLE III
On the basis of the first embodiment and the second embodiment, the present embodiment provides a GaN-based thermoelectric transistor on a free-standing substrate and a method for fabricating the same, please refer to fig. 5a to 5g, and fig. 5a to 5g are schematic process diagrams of a method for fabricating a GaN-based thermoelectric transistor on a free-standing substrate according to an embodiment of the present invention.
The GaN-based thermionic transistor comprises a collector 1, a GaN self-supporting substrate 2, and AlyGa1-y N collector region 3, GaN base region 4, base electrode 5 and AlxGa1-xN emitter region 6, N + GaN cap layer 7, emitter 8 and passivation layer 9 as shown in fig. 5 a. For a specific structure of the device, please refer to embodiment one, which is not described in detail in this embodiment.
Specifically, the GaN-based thermionic transistor selects a collector electrode 1, a GaN self-supporting substrate 2 and Al which are sequentially laminated from bottom to topyGa1-y N collector region 3, GaN base region 4, AlxGa1-xThe N emitting region 6 and the N + GaN cap layer 7 are used as epitaxial substrates. Wherein the thickness of the n + GaN cap layer 7 is 15nm, and the doping concentration is 8e18cm-3，AlxGa1-xDoping concentration 1e of N emitter region 619cm-3The Al component x is 30 percent, the thickness is 35nm, and the doping concentration of the GaN base region 4 is 1e19cm-310nm thick, AlyGa1-yDoping concentration 3e of N collector region 318cm-3Al component of 7%, thickness of 50nm, GaN self-supporting substrate 2 doping concentration 1e18cm-3And the thickness is 300 mu m.
The preparation method of the gallium nitride hot electron transistor device comprises the following steps:
and S1, manufacturing an electric isolation structure of the active region of the device on the epitaxial substrate by utilizing an Inductively Coupled Plasma (ICP) process.
S11, lithography of electrically isolated regions of the active region on the n + GaN cap layer 7.
Firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min; then, coating photoresist and spin coating photoresist on the surface of the n + GaN cap layer 7 at a spin coating rotation speed of 3500 rpm/mim, and baking the sample on a hot plate at 90 ℃ for 1 min; and finally, putting the sample into a photoetching machine to expose the photoresist in the electric isolation area, putting the exposed sample into a developing solution to remove the photoresist in the electric isolation area, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist.
S12, etching the n + GaN cap layer 7 and the Al of the electric isolation region in sequence by utilizing an inductively coupled plasma etching process ICPxGa1-xN emitter region 6, GaN base region 4, AlyGa1-y N collector region 3 forming an electrical isolation structure 10a of the active area of the device, as shown in fig. 5 b.
Firstly, etching the n + GaN cap layer 7 and Al of the electric isolation region in sequence by utilizing an ICP (inductively coupled plasma) processxGa1-xN emitter region 6, GaN base region 4, AlyGa1-yAnd the etching depth of the N collector region 3 is 110nm so as to realize mesa isolation of the source region. Then, the sample is sequentially put into acetone solution, stripping liquid, acetone solution and ethanol solution for cleaning to remove the photoresist outside the electrical isolation region, the sample is washed by ultrapure water and dried by nitrogen gas to form an electrical isolation structure 10a of the device active region, the electrical isolation structure 10a enables the surface of the n + GaN self-supporting substrate 2 in the device to be exposed, Al and GaN are in contact with the surface of the n + GaN self-supporting substrate 2, and the electrical isolation structure 10a is in contact with the surface of the deviceyGa1-y N collector region 3, GaN base region 4, AlxGa1-xThe side surfaces of the N emitter region 6 and the N + GaN cap layer 7 are exposed.
S2, etching the n + GaN cap layer 7 of the epitaxial substrate and AlxGa1-xN emitter region 6, forming base region 51 and emitter region 81.
S21, photoetching is carried out on the selected pattern area on the n + GaN cap layer 7.
Firstly, placing an epitaxial substrate on a hot plate at 200 ℃ for baking for 5 min; then, glue coating and spin coating of the stripping glue are carried out on the n + GaN cap layer 7, the spin coating thickness is 0.35 mu m, and the sample is placed on a hot plate at 200 ℃ to be baked for 5 min; then, gluing and spinning photoresist on the stripper with the thickness of 0.77 μm, and baking the sample on a hot plate at 90 deg.C for 1 min; and finally, putting the sample subjected to glue coating and spin coating into a photoetching machine to expose the coated surface, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue, and then carrying out ultra-pure water washing and nitrogen purging on the sample to form a selected pattern area.
S22, etching the n + GaN cap layer 7 of the selected pattern area and AlxGa1-xN emitter region 6, forming a base region 51 and an emitter region 81, wherein the emitter region 81 is located on the N + GaN cap layer 7 and the base region 51 is located on the GaN base region 4 and surrounds the emitter region 81, as shown in fig. 5 c.
Firstly, etching the n + GaN cap layer 7 and Al of the selected pattern area in sequence by utilizing an ICP (inductively coupled plasma) processxGa1-xAn N emission region 6 with an etching depth of 50 nm; then, the sample is sequentially placed into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the etching area, the sample is washed by ultrapure water and dried by nitrogen gas to form a base region 51 and an emitter region 81, the base region 51 is positioned on the surface of the GaN base region 4 and surrounds the n + GaN cap layer 7 and the Al cap layerxGa1-xThe N emitter region 6 forms a mesa structure, the base region 51 surrounding the emitter region 81, seen in top view.
And S3, growing a passivation layer medium on the surfaces of the electric isolation structure, the GaN base region 4, the AlxGa1-xN emitter region 6 and the n + GaN cap layer 7 to form a passivation layer 9.
And S31, cleaning the surface of the device after the active area etching is finished.
Firstly, putting a sample into an acetone solution for ultrasonic cleaning for 3mim, wherein the ultrasonic intensity is 3.0; then, putting the sample into stripping liquid with the temperature of 60 ℃ for water bath heating for 5 min; then, the sample is sequentially placed into an acetone solution and an ethanol solution for ultrasonic cleaning for 3min, and the ultrasonic intensity is 3.0; finally, the sample was rinsed with ultra pure water and blown dry with nitrogen.
S32, growing a passivation layer medium on the surface of the electric isolation structure, the surface of the GaN base region 4, the surface of the AlxGa1-xN emitter region 6 and the surface of the n + GaN cap layer 7 by utilizing a plasma enhanced chemical vapor deposition PECVD process to form a passivation layer 9, as shown in FIG. 5 d.
In the present embodiment, the electrical isolation structure 10a is formed by etching using the ICP process, and the surface of the electrical isolation structure includes the upper surface of the n + GaN self-standing substrate 2, and therefore,on the upper surface of the n + GaN free-standing substrate 2, AlyGa1-ySide surface of N collector region 3, side surface and upper surface of GaN base region 4, and AlxGa1-xAnd a passivation layer medium is grown on the side surface of the N emitter region 6 and the side surface and the upper surface of the N + GaN cap layer 7 to form a passivation layer 9.
In one embodiment, a 30nm SiN passivation layer is grown by a PECVD process under the following process conditions: by NH3And SiH4As the reaction gas, the substrate temperature was 250 ℃, the reaction chamber pressure was 600mTorr, and the RF power was 22W.
S4, the passivation layer 9 and GaN base region 4 of base region 51, the passivation layer 9 and n + GaN cap layer 7 of emitter region 81 are etched to form base opening 53 and emitter opening 83.
S41, the passivation layer 9 of the base region 51 and the passivation layer 9 of the emitter region 81 are simultaneously etched to form the first opening 52 and the second opening 82, as shown in fig. 5 e.
First, a base opening region is lithographically etched on the surface of the passivation layer 9 on the base region 51, and an emitter opening region is lithographically etched on the surface of the passivation layer 9 on the emitter region 81. Specifically, first, the sample was baked on a hot plate at 200 ℃ for 5 min; then, photoresist coating and spin coating are carried out on the surface of the passivation layer 9 on the base region 51 and the surface of the passivation layer 9 on the emitter region 81, the spin coating rotating speed is 3500 rpm/mim, and the sample is placed on a hot plate at 90 ℃ and baked for 1 min; then, putting the sample into a photoetching machine to expose the photoresist in the metal interconnection open hole area; finally, the exposed sample is placed into a developing solution to remove the photoresist in the interconnected opening area, and the photoresist is subjected to ultra-pure water washing and nitrogen blow-drying.
Then, the passivation layer 9 of the base region 51 and the passivation layer 9 of the emitter region 81 are simultaneously etched to form the first opening 52 and the second opening 82. Specifically, the reaction gas is CF by utilizing an ICP etching process4And O2Etching the SiN protective layer 9 in the base electrode open hole region and the SiN protective layer 9 in the emitter electrode open hole region under the conditions that the pressure of the reaction chamber is 10mTorr and the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively to form a SiN protective layer penetrating through the passivation layer 9A first aperture 52 and a second aperture 82.
In this embodiment, the n + GaN cap layer 7 and the GaN base region 4 are not over-etched, that is, the over-etching depth is 0, and at this time, the first opening 52 and the second opening 82 are the base opening 53 and the emitter opening 83.
And after etching is finished, sequentially putting the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the open pore etching area, washing the sample with ultrapure water and drying with nitrogen.
S5, metal is evaporated in the base opening 53, on the passivation layer of the base region 51, in the emitter opening 83, on the passivation layer of the emitter region 81, forming the base 5 and the emitter 8.
S51, photoetching an emitter patterning region on the surface of the passivation layer 9 on the n + GaN cap layer 7, and photoetching a base patterning region on the surface of the passivation layer 9 on the GaN base region 4.
Firstly, placing a sample on a hot plate at 200 ℃ for baking for 5 min; then, glue spreading and spin coating of the stripping glue are carried out on the n + GaN cap layer 7 and the GaN base region 4, the spin coating thickness is 0.35 mu m, and the sample is placed on a hot plate at 200 ℃ to be baked for 5 min; then, gluing and spinning photoresist on the stripper with the thickness of 0.77 μm, and baking the sample on a hot plate at 90 deg.C for 1 min; then, putting the sample which is subjected to gluing and whirl coating into a photoetching machine to expose the photoresist in the emitter region and the base region; and finally, putting the exposed sample into a developing solution to remove the photoresist and the stripping glue in the emitter region and the base region, and carrying out ultra-pure water washing and nitrogen blow-drying on the photoresist and the stripping glue to form an emitter patterned region and a base patterned region.
S52, using electron beam evaporation process, metal is evaporated on the passivation layer 9 of the emitter patterned region, in the emitter opening 83, on the passivation layer 9 of the base patterned region, in the base opening 53, forming the base 5 and the emitter 8, as shown in fig. 5 f.
Firstly, putting a sample into an electron beam evaporation table, and waiting for the vacuum degree of a reaction chamber of the electron beam evaporation table to reach 2 multiplied by 10-6After Torr, the nitride layer is formed on the n + GaN cap layer 7 in the emitter patterning region,And evaporating a metal layer on the GaN base region 4 in the base patterning region and on the photoresist outside the emitter patterning region and the base patterning region, wherein the metal layer is of a stack structure sequentially consisting of three layers of Ni, Au and Ni from bottom to top.
And then, stripping the sample after the evaporation of the emitter and base metals is finished to remove the metal, the photoresist and the stripping glue outside the emitter and base regions, flushing the sample with ultrapure water and drying the sample with nitrogen to form the base 5 and the emitter 8.
S6, a collector 1 is formed on the bottom of the GaN free-standing substrate 2, as shown in fig. 5 g.
Specifically, the sample is put into an electron beam evaporation table, and the vacuum degree of a reaction chamber of the electron beam evaporation table reaches 2 x 10-6After the Torr, a metal layer is evaporated on the GaN self-supporting substrate 2 in the collector region, and the metal layer is of a stack structure consisting of three layers of Ni, Au and Ni from bottom to top in sequence. And finally, cleaning the sample subjected to collector electrode manufacturing, washing the sample with ultrapure water, and drying the sample with nitrogen to form a collector electrode 1, thereby completing device manufacturing.
Example four
On the basis of the first embodiment, the second embodiment and the third embodiment, the present embodiment provides another GaN-based thermoelectric transistor on a free-standing substrate and a method for fabricating the same, please refer to fig. 6a to 6h, and fig. 6a to 6h are schematic process diagrams of another method for fabricating a GaN-based thermoelectric transistor on a free-standing substrate according to the embodiment of the present invention.
The GaN-based thermionic transistor comprises a collector 1, a GaN self-supporting substrate 2, and AlyGa1-y N collector region 3, GaN base region 4, base electrode 5 and AlxGa1-xN emitter region 6, N + GaN cap layer 7, emitter 8 and passivation layer 9 as shown in fig. 6 a. For a specific structure of the device, please refer to embodiment one, which is not described in detail in this embodiment.
Specifically, the GaN-based thermionic transistor selects a collector electrode 1, a GaN self-supporting substrate 2 and Al which are sequentially laminated from bottom to topyGa1-y N collector region 3, GaN base region 4, AlxGa1-xThe N emitting region 6 and the N + GaN cap layer 7 are used as epitaxial substrates.Wherein the thickness of the n + GaN cap layer 7 is 15nm, and the doping concentration is 8e18cm-3，AlxGa1-xDoping concentration 1e of N emitter region 619cm-3The Al component x is 30 percent, the thickness is 35nm, and the doping concentration of the GaN base region 4 is 1e19cm-310nm thick, AlyGa1-yDoping concentration 3e of N collector region 318cm-3Al component of 7%, thickness of 50nm, GaN self-supporting substrate 2 doping concentration 1e18cm-3。
The preparation method of the gallium nitride hot electron transistor device comprises the following steps:
and S1, manufacturing an electric isolation structure of the active region of the device on the epitaxial substrate by utilizing an ion implantation process.
S11, lithography of electrically isolated regions of the active region on the n + GaN cap layer 7.
Firstly, a sample is placed on a hot plate at 200 ℃ for baking for 5min, then, photoresist coating and spin coating are carried out on the surface of the n + GaN cap layer 7, the spin coating thickness is 2 mu m, the sample is placed on the hot plate at 90 ℃ for baking for 1min, then the sample is placed in a photoetching machine for exposing the photoresist in the electric isolation area, finally, the exposed sample is placed in a developing solution for removing the photoresist in the electric isolation area, and the photoresist is washed by ultrapure water and dried by nitrogen.
S12, forming Al on the n + GaN cap layer 7 by using an ion implantation processxGa1-xN emitter region 6, GaN base region 4, AlyGa1-yAnd the electric isolation of the active region of the device is manufactured in the N collector region 3.
N ions are sequentially implanted into the N + GaN cap layer 7 and Al of the electric isolation region by using an ion implantation processxGa1-xN emitter region 6, GaN base region 4, and AlyGa1-yThe injection depth of the N collector region 3 is 120nm so as to realize the electrical isolation of the active region; then sequentially putting the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the electrical isolation region; finally the sample is rinsed with ultra pure water and blown dry with nitrogen to form the electrically isolated structures 10b of the active area of the device as shown in fig. 6 b. The electrically isolating structure 10b is located at AlyGa1-yN current collectionRegion 3, GaN base region 4, AlxGa1-xN emitter region 6 and N + GaN cap layer 7.
S2, etching the n + GaN cap layer 7 of the epitaxial substrate and AlxGa1-xN emitter region 6, forming base region 51 and emitter region 81.
S21, photoetching is carried out on the selected pattern area on the n + GaN cap layer 7.
S22, etching the n + GaN cap layer 7 of the selected pattern area and AlxGa1-xN emitter region 6, forming a base region 51 and an emitter region 81, wherein the emitter region 81 is located on the N + GaN cap layer 7 and the base region 51 is located on the GaN base region 4 and surrounds the emitter region 81, as shown in fig. 6 c. Specifically, the etching depth was 50 nm. For a detailed implementation, refer to example three.
And S3, growing a passivation layer medium on the surfaces of the electric isolation structure, the GaN base region 4, the AlxGa1-xN emitter region 6 and the n + GaN cap layer 7 to form a passivation layer 9.
And S31, cleaning the surface of the device after the active area etching is finished. For a detailed implementation, refer to example three.
S32, growing a passivation layer medium on the surface of the electric isolation structure, the surface of the GaN base region 4, the surface of the AlxGa1-xN emitter region 6 and the surface of the n + GaN cap layer 7 by utilizing an atomic layer deposition ALD process to form a passivation layer 9, as shown in FIG. 6 d.
In this embodiment, the electrical isolation structure 10b is formed by an ion implantation process, and therefore, the upper surface and the side surface of the electrical isolation structure, the upper surface of the GaN base region 4, and Al are formedxGa1-xAnd a passivation layer medium is grown on the side surface of the N emitter region 6 and the side surface and the upper surface of the N + GaN cap layer 7 to form a passivation layer 9.
In one embodiment, Al is grown to a thickness of 30nm using an ALD process2O3The passivation layer is grown under the following process conditions: using TMA and H2O as a reaction precursor, the process temperature was 300 deg.C, the radio frequency power was set at 50W, and the reaction chamber pressure was 0.3 Torr.
S4, the passivation layer 9 and GaN base region 4 of base region 51, the passivation layer 9 and n + GaN cap layer 7 of emitter region 81 are etched to form base opening 53 and emitter opening 83.
S41, the passivation layer 9 of the base region 51 and the passivation layer 9 of the emitter region 81 are simultaneously etched to form the first opening 52 and the second opening 82, as shown in fig. 6 e. For a detailed implementation, refer to example three.
S42, GaN base region 4 in first opening 52 and n + GaN cap layer 7 in second opening 82 are over-etched simultaneously to form base opening 53 and emitter opening 83, as shown in fig. 6 f.
Specifically, the ICP etching process is utilized to perform the reaction gas of Cl2And etching the n + GaN cap layer 7 and the GaN base region 4 to form a base opening 53 and an emitter opening 83 under the conditions that the pressure of the reaction chamber is 10mTorr and the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, wherein the over-etching depth is 3 nm.
In this embodiment, the over-etching depth is 3nm, and therefore, the base opening 53 is embedded in the GaN base region 4, and the emitter opening 83 is embedded in the n + GaN cap layer 7.
And after etching is finished, sequentially putting the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the open pore etching area, washing the sample with ultrapure water and drying with nitrogen.
S5, metal is evaporated in the base opening 53, on the passivation layer of the base region 51, in the emitter opening 83, on the passivation layer of the emitter region 81, forming the base 5 and the emitter 8.
S51, photoetching an emitter patterning region on the surface of the passivation layer 9 on the n + GaN cap layer 7, and photoetching a base patterning region on the surface of the passivation layer 9 on the GaN base region 4.
S52, using electron beam evaporation process, metal is evaporated on the passivation layer 9 of the emitter patterned region, in the emitter opening 83, on the passivation layer 9 of the base patterned region, in the base opening 53, forming the base 5 and the emitter 8, as shown in fig. 6 g.
For a detailed implementation, refer to example three.
S6, a collector 1 is formed on the bottom of GaN free-standing substrate 2, as shown in fig. 6 h. For a detailed implementation, refer to example three.
EXAMPLE five
Referring again to fig. 5 a-5 g, this embodiment provides yet another GaN-based thermoelectric transistor on a free-standing substrate and a method for fabricating the same based on the first, second, and third embodiments.
The GaN-based thermionic transistor comprises a collector 1, a GaN self-supporting substrate 2, and AlyGa1-y N collector region 3, GaN base region 4, base electrode 5 and AlxGa1-xN emitter region 6, N + GaN cap layer 7, emitter 8 and passivation layer 9. For a specific structure of the device, please refer to embodiment one, which is not described in detail in this embodiment.
Specifically, the GaN-based thermionic transistor selects a collector electrode 1, a GaN self-supporting substrate 2 and Al which are sequentially laminated from bottom to topyGa1-y N collector region 3, GaN base region 4, AlxGa1-xThe N emitter region 6, the N + GaN cap layer 7, serves as an epitaxial substrate as shown in fig. 5 a. Wherein the n + GaN cap layer 7 has a thickness of 20nm and a doping concentration of 1e19cm-3，AlxGa1-xDoping concentration 1e of N emitter region 619cm-3The Al component is 40%, the thickness is 40nm, and the doping concentration of the GaN base region 4 is 1.5e19cm-312nm thick, AlyGa1-yDoping concentration 5e of N collector region 318cm-3Al component of 10%, thickness of 60nm, GaN self-supporting substrate 2 doping concentration of 3e18cm-3。
The preparation method of the gallium nitride hot electron transistor device comprises the following steps:
and S1, manufacturing an electric isolation structure of the active region of the device on the epitaxial substrate by utilizing an Inductively Coupled Plasma (ICP) process.
S11, lithography of electrically isolated regions of the active region on the n + GaN cap layer 7.
S12, etching the n + GaN cap layer 7 and the Al of the electric isolation region in sequence by utilizing an inductively coupled plasma etching process ICPxGa1-xN emitter region 6, GaN base region 4, AlyGa1-y N collector region 3 forming an electrical isolation structure 10a of the active area of the device, as shown in fig. 5 b.
For a detailed implementation, refer to example three.
S2, etching the n + GaN cap layer 7 of the epitaxial substrate and AlxGa1-xN emitter region 6, forming base region 51 and emitter region 81.
S21, photoetching is carried out on the selected pattern area on the n + GaN cap layer 7.
S22, etching the n + GaN cap layer 7 of the selected pattern area and AlxGa1-xN emitter region 6, forming a base region 51 and an emitter region 81, wherein the emitter region 81 is located on the N + GaN cap layer 7 and the base region 51 is located on the GaN base region 4 and surrounds the emitter region 81, as shown in fig. 5 c.
Specifically, the etching depth was 60 nm.
For a detailed implementation, refer to example three.
And S3, growing a passivation layer medium on the surfaces of the electric isolation structure, the GaN base region 4, the AlxGa1-xN emitter region 6 and the n + GaN cap layer 7 to form a passivation layer 9.
And S31, cleaning the surface of the device after the active area etching is finished. For a detailed implementation, refer to example three.
S32, using ALD process to deposit Al on the surface of the electric isolation structure, the surface of the GaN base region 4 and the AlxGa1-xAnd (4) growing a passivation layer medium on the surface of the N emitter region 6 and the surface of the N + GaN cap layer 7 to form a passivation layer 9, as shown in FIG. 5 d.
In this embodiment, the electrical isolation structure 10a is formed by etching using the ICP process, and the surface of the electrical isolation structure includes the upper surface of the n + GaN self-standing substrate 2, and therefore, Al is formed on the upper surface of the n + GaN self-standing substrate 2yGa1-ySide surface of N collector region 3, side surface and upper surface of GaN base region 4, and AlxGa1-xAnd a passivation layer medium is grown on the side surface of the N emitter region 6 and the side surface and the upper surface of the N + GaN cap layer 7 to form a passivation layer 9.
In one embodiment, Al is grown to a thickness of 30nm using an ALD process2O3The passivation layer is grown under the following process conditions: using TMA and H2O as a reaction precursor, the process temperature was 300 deg.C, the radio frequency power was set at 50W, and the reaction chamber pressure was 0.3 Torr.
S4, the passivation layer 9 and GaN base region 4 of base region 51, the passivation layer 9 and n + GaN cap layer 7 of emitter region 81 are etched to form base opening 53 and emitter opening 83.
S41, the passivation layer 9 of the base region 51 and the passivation layer 9 of the emitter region 81 are simultaneously etched to form the first opening 52 and the second opening 82, as shown in fig. 5 e. For a detailed implementation, refer to example three.
S42, GaN base region 4 in first opening 52 and n + GaN cap layer 7 in second opening 82 are over-etched simultaneously to form base opening 53 and emitter opening 83, as shown in fig. 5 f.
Specifically, the ICP etching process is utilized to perform the reaction gas of Cl2And etching the n + GaN cap layer 7 and the GaN base region 4 to form a base opening 53 and an emitter opening 83 under the conditions that the pressure of the reaction chamber is 10mTorr and the radio frequency power of the upper electrode and the lower electrode is 100W and 10W respectively, wherein the over-etching depth is 5 nm.
In this embodiment, the over-etching depth is 5nm, and therefore, the base opening 53 is embedded in the GaN base region 4, and the emitter opening 83 is embedded in the n + GaN cap layer 7.
And after etching is finished, sequentially putting the sample into an acetone solution, a stripping solution, an acetone solution and an ethanol solution for cleaning to remove the photoresist outside the open pore etching area, washing the sample with ultrapure water and drying with nitrogen.
S5, metal is evaporated in the base opening 53, on the passivation layer of the base region 51, in the emitter opening 83, on the passivation layer of the emitter region 81, forming the base 5 and the emitter 8, as shown in fig. 5 g.
S51, photoetching an emitter patterning region on the surface of the passivation layer 9 on the n + GaN cap layer 7, and photoetching a base patterning region on the surface of the passivation layer 9 on the GaN base region 4.
S52, evaporating metal on the passivation layer 9 of the emitter patterning region, in the emitter opening 83, on the passivation layer 9 of the base patterning region, and in the base opening 53 by using an electron beam evaporation process to form the base 5 and the emitter 8.
For a detailed implementation, refer to example three.
S6, a collector 1 is formed on the bottom of the GaN free-standing substrate 2. For a detailed implementation, refer to example three.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1. A GaN-based thermoelectric transistor on a free-standing substrate, comprising: a collector (1), an n + GaN self-supporting substrate (2), AlyGa1-yN collector region (3), GaN base region (4), base electrode (5) and AlxGa1-xAn N emitter region (6), an N + GaN cap layer (7), an emitter (8) and a passivation layer (9), wherein,
the collector (1), the n + GaN self-supporting substrate (2), and the AlyGa1-yAn N collector region (3), the GaN base region (4), and the AlxGa1-xThe N emitting region (6) and the N + GaN cap layer (7) are sequentially laminated, and the AlxGa1-xThe N emission region (6) and the N + GaN cap layer (7) form a mesa structure;
the passivation layer (9) is positioned on the electric isolation structure, the GaN base region (4) and the AlxGa1-xA surface of the N emitter region (6), the N + GaN cap layer (7);
the upper end of the base electrode (5) is positioned on the surface of a passivation layer (9) on the GaN base region (4) and is in contact with the passivation layer (9) on the side surface of the mesa structure, and the lower end of the base electrode is positioned in the passivation layer (9) and is in contact with the GaN base region (4);
the upper end of the emitter (8) is located on the surface of the passivation layer (9) on the mesa structure, and the lower end of the emitter is located in the passivation layer (9) and is in contact with the n + GaN cap layer (7).
2. GaN-based thermionic transistor on a free-standing substrate according to claim 1, characterised in that the n + GaN free-standing substrate (2) has an n-type doping concentration of 1e18cm-3～8e18cm-3The thickness is 300-400 μm.
3. The GaN-based thermoelectric transistor on a free-standing substrate of claim 1, wherein the Al isyGa1-yThe Al component y of the N collector region (3) is 5-10%, and the N-type doping concentration is 5e17cm-3～5e18cm-3The thickness is 40 nm-60 nm.
4. GaN-based thermionic transistor on a free-standing substrate according to claim 1, characterised in that the n-type doping concentration 8e of the GaN-based base region (4) is18cm-3～1.5e19cm-3And the thickness is 8 nm-12 nm.
5. GaN-based thermionic transistor on a self-supporting substrate according to claim 1, characterised in that the lower end of the base (5) is located in the passivation layer (9) and embedded in the GaN-base region (4).
6. The GaN-based thermoelectric transistor on a free-standing substrate of claim 1, wherein the Al isxGa1-xThe Al component x of the N emitting region (6) is 25-40%, and the N-type doping concentration is 1e18cm-3～1e19cm-3And the thickness is 25 nm-40 nm.
7. GaN-based thermionic transistor on a free-standing substrate according to claim 1, characterised in that the n-type doping concentration 5e of the n + GaN cap layer (7)18cm-3～1e19cm-3And the thickness is 10 nm-20 nm.
8. A method of fabricating a GaN-based thermoelectric transistor on a free-standing substrate, comprising the steps of:
s1, manufacturing an electric isolation structure of the active region of the device on an epitaxial substrate, wherein the epitaxial substrate comprises an n + GaN self-supporting substrate (2) and Al which are sequentially stackedyGa1-yAn N collector region (3), a GaN base region (4), and AlxGa1-xAn N emitter region (6) and an N + GaN cap layer (7);
s2, etching the n + GaN cap layer (7) and the AlxGa1-xAn N emitter region (6) forming a base region (51) and an emitter region (81), wherein the emitter region (81) is located on the N + GaN cap layer (7), the base region (51) is located on the GaN base region (4) and surrounds the emitter region (81);
s3, forming the electrically isolated structure, the GaN base region (4), and the AlxGa1-xGrowing a passivation layer medium on the surfaces of the N emitting region (6) and the N + GaN cap layer (7) to form a passivation layer (9);
s4, etching the passivation layer (9) and the GaN base region (4) of the base region (51), the passivation layer (9) and the n + GaN cap layer (7) of the emitter region (81) and forming a base opening (53) and an emitter opening (83);
s5, evaporating metal in the base opening (53), on the passivation layer of the base region (51), in the emitter opening (83), on the passivation layer of the emitter region (81), forming a base (5) and an emitter (8);
and S6, manufacturing a collector (1) at the bottom of the GaN self-supporting substrate (2).
9. The method of claim 8, wherein step S4 includes:
s41, etching the passivation layer (9) of the base region (51) and the passivation layer (9) of the emitter region (81) simultaneously to form a first opening (52) and a second opening (82);
s42, the GaN base region (4) in the first opening (52) and the n + GaN cap layer (7) in the second opening (82) are etched at the same time to form the base opening (53) and the emitter opening (83).
10. The method of claim 8, wherein the over-etching is performed to a depth of 0-5 nm.
CN202110864585.1A 2021-07-29 2021-07-29 GaN-based thermoelectric transistor on self-supporting substrate and preparation method thereof Pending CN113745329A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110864585.1A CN113745329A (en) 2021-07-29 2021-07-29 GaN-based thermoelectric transistor on self-supporting substrate and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110864585.1A CN113745329A (en) 2021-07-29 2021-07-29 GaN-based thermoelectric transistor on self-supporting substrate and preparation method thereof

Publications (1)

Publication Number Publication Date
CN113745329A true CN113745329A (en) 2021-12-03

Family

ID=78729395

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110864585.1A Pending CN113745329A (en) 2021-07-29 2021-07-29 GaN-based thermoelectric transistor on self-supporting substrate and preparation method thereof

Country Status (1)

Country Link
CN (1) CN113745329A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6147371A (en) * 1997-12-22 2000-11-14 Nec Corporation Bipolar transistor and manufacturing method for same
JP2006019378A (en) * 2004-06-30 2006-01-19 Matsushita Electric Ind Co Ltd Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6147371A (en) * 1997-12-22 2000-11-14 Nec Corporation Bipolar transistor and manufacturing method for same
JP2006019378A (en) * 2004-06-30 2006-01-19 Matsushita Electric Ind Co Ltd Semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
SANSAPTAK DASGUPTA ET AL: "Experimental Demonstration of III-Nitride Hot-Electron Transistor With GaN Base", 《IEEE ELECTRON DEVICE LETTERS》 *

Similar Documents

Publication Publication Date Title
CN106373884B (en) Method for manufacturing composite gate dielectric GaN-based insulated gate high electron mobility transistor
JP2008004779A (en) Nitride semiconductor bipolar transistor, and its manufacturing method
CN111384171B (en) High-channel mobility vertical UMOSFET device and preparation method thereof
CN109950323B (en) Polarized superjunction III-nitride diode device and manufacturing method thereof
CN110504316B (en) GaN HEMT with segmented sub-devices and method of fabrication
CN101419982B (en) High electron mobility device for trench gate type source field board and manufacturing method therefor
CN114883407B (en) HEMT based on Fin-FET gate structure and manufacturing method thereof
CN116092935A (en) Manufacturing method of AlGaN/GaN HEMT device
CN113745329A (en) GaN-based thermoelectric transistor on self-supporting substrate and preparation method thereof
CN113257896B (en) Multi-field-plate radio frequency HEMT device and preparation method thereof
CN113745330B (en) Gallium nitride thermionic transistor device with collector electrode arranged on top and preparation method thereof
CN109830540B (en) Schottky diode based on hollow anode structure and preparation method thereof
CN113745324B (en) Radio frequency device with quasi-vertical structure and manufacturing method
CN110676166B (en) FinFET enhanced device with P-GaN cap layer and manufacturing method thereof
CN112825330A (en) GaN transistor device with high-linearity composite gate structure and preparation method thereof
CN115274845B (en) Concave Fin-MESFET gate structure HEMT and manufacturing method
CN114823850B (en) P-type mixed ohmic contact gallium nitride transistor
CN211929494U (en) GaN-based radio frequency device with II-shaped grids
CN214043676U (en) High-linearity GaN-based millimeter wave device
CN112768508B (en) Back gate full-control AlGaN/GaN heterojunction enhanced power HEMT device and preparation method thereof
CN113113478B (en) GaN-based radio frequency power device based on ohmic regrowth and preparation method thereof
CN113410285B (en) Semiconductor device and method for manufacturing the same
CN108695383B (en) Method for realizing high-frequency MIS-HEMT and MIS-HEMT device
CN115472499A (en) Semiconductor device and method for manufacturing the same
CN116960181A (en) Multi-channel heterojunction device based on quantum well self-aligned gate and manufacturing method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination