CN113745317A - 一种形成igbt场截止埋层的制备方法 - Google Patents

一种形成igbt场截止埋层的制备方法 Download PDF

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CN113745317A
CN113745317A CN202111022267.7A CN202111022267A CN113745317A CN 113745317 A CN113745317 A CN 113745317A CN 202111022267 A CN202111022267 A CN 202111022267A CN 113745317 A CN113745317 A CN 113745317A
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周倩
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66325Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333Vertical insulated gate bipolar transistors
    • H01L29/66348Vertical insulated gate bipolar transistors with a recessed gate
    • HELECTRICITY
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395Vertical transistors, e.g. vertical IGBT
    • H01L29/7396Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

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Abstract

一种形成IGBT场截止埋层的制备方法。包括以下步骤:选用FZ硅片作为N型衬底;去除N型衬底表面氧化层,在所述N型衬底的正面注入N型杂质并高温推结外延生长形成N型场截止埋层;在所述N型衬底的背面进行减薄处理;在所述N型场截止埋层上进行外延层生长;翻转所述N型衬底,在其背面进行后续常规正面工艺,栅极的生长与刻蚀,P型井和重掺杂的N型区的注入和激活,层间隔离层形成与刻蚀,以及发射极金属层的形成;将所述外延层全部去除;在所述N型场截止埋层上进行P型收集极的注入、激活和背面金属化。本发明工艺简单,实现方便。

Description

一种形成IGBT场截止埋层的制备方法
技术领域
本发明涉及一种功率半导体器件加工技术领域,尤其涉及一种形成IGBT场截止埋层的制备方法。
背景技术
IGBT全称绝缘栅双极型晶体管,是一种BJT(双极型三极管)和MOS(绝缘栅型场效应管)复合结构的栅控电压驱动型功率半导体器件,具备高输入阻抗、高速开关特性、导通状态低损耗等特点。IGBT器件是现代通用的电力半导体器件,主要应用于新能源、机车牵引、智能电网、高压变频器等领域。
常规的沟槽型IGBT器件基本结构如图1所示,包含发射极金属层,沟槽栅极,N型衬底,N型场截止埋层结构,层间隔离层,重掺杂的N型区(序号1区域),P型井和P型收集极。
常规工艺上是通过氢注入工艺来实现较深结深(5um~25um)的N型场截止埋层结构的制备。氢注入工艺的特点是可以在较低温度下(350C~400C区间)实现注入离子的激活,因此,可以在晶圆完成正面工艺和减薄工艺之后再进行工艺加工。但是,较低的激活温度对注入工艺诱发的晶格损伤的修复程度有限。因此,采用氢注入工艺方案来实现N型场截止埋层结构制备,IGBT器件的漏电表现偏高,影响和限制了器件在高温下的应用表现。
另一种常用方案是采用双外延层衬底方案。外延层作为N型衬底,内层EPI外延层作为N型场截止埋层。该方案的优点是可以通过EPI(外延层)外延生长工艺的调整,很灵活的实现N型场截止埋层的深度(厚度)和浓度的调整。但是,毕竟是采用EPI外延方案来实现的N型衬底和N型场截止埋层制备,相比传统的FZ硅片,EPI衬底的晶格缺陷很难以避免。因此,器件的鲁棒性(器件极限下的安全工作区,例如短路安全工作区和反向关断安全工作区)和一致性{器件静态参数(例如,耐压,漏电和导通压降)和动态参数(开关参数、功耗参数和波形表现)}受到很多的限制。
现有专利文献中,如2014年12月31日公开的一篇专利名称为“一种场截止型绝缘栅双极晶体管器件的制备方法”,申请号为“CN201310271615.3”的发明专利。该方法公开了:在衬底上外延生长形成重掺杂的N型外延层作为场截止层,然后外延生长形成轻掺杂的N型外延层作为耐压层,接着进行常规正面工艺,然后进行背面减薄工艺,接着在背部注入P型杂质并退火形成P型集电区,然后进行常规背面金属化工艺的技术方案。该案是采用的双层外延衬底方案。该方案的优点是可以通过外延生长工艺的调整,很灵活的实现N型场截止埋层的深度(厚度)和浓度的调整。但是,毕竟是采用外延方案来实现的N型衬底(漂移区)和N型场截止埋层制备,相比传统的FZ区熔衬底,外延衬底的晶格缺陷很难以避免。因此,器件的鲁棒性和一致性受到很多的限制。
现有专利文献中,如2012年11月28日公开的一篇专利名称为“一种FS-IGBT器件的制备方法”,申请号为“CN201210315975.4”的发明专利。该案通过使用衬底上进行N型杂质注入形成场截止层,然后生长外延层,使用外延层作为漂移区,并在外延层表面制作正面图形,然后背部减薄,背部P型集电区注入并退火,背部金属化的方法来制作场截止型晶体管,使场截止层杂质充分激活。该制备方案与申请号为“CN201310271615.3”类似,相比单纯的FZ区熔衬底,外延衬底的晶格缺陷很难以避免。因此,器件的鲁棒性和一致性受到很多的限制。
目前还有一种方案是采用先做正面结构,背面减薄后进行背面离子注入,然后激光退火的方式来制造场截止层。由于要保护正面结构,退火温度不能过高,此时杂质激活率很低,影响器件性能。而且背面离子注入方式无法使杂质深层推进,只能在背部获得一层较薄FS层,较薄的FS层会对器件性能造成影响。也有通过长时间扩散和推阱形成场截止层然后再外延生长耐压层的方法,但是此种方法生产周期较长,浓度分布不理想,浓度梯度较大,控制减薄厚度也存在难度。而且上述的背面离子注入和激光退火工艺还需要较为昂贵的高能离子注入设备和激光退火设备,开发成本较大。
发明内容
本发明针对以上问题,提供了一种加工简便、提升器件的鲁棒性与一致性的一种形成IGBT场截止埋层的制备方法。
本发明的技术方案是:一种形成IGBT场截止埋层的制备方法,包括以下步骤:
1)选用FZ硅片作为N型衬底;
2)去除N型衬底表面氧化层,在所述N型衬底的正面注入N型杂质并高温推结外延生长形成N型场截止埋层;
3)在所述N型衬底的背面进行减薄处理;
4)在所述N型场截止埋层上进行外延层生长;
5)翻转所述N型衬底,在其背面进行后续常规正面工艺,栅极的生长与刻蚀,P型井和重掺杂的N型区的注入和激活,层间隔离层形成与刻蚀,以及发射极金属层的形成;
6)将所述外延层全部去除;
7)在所述N型场截止埋层上进行P型收集极的注入、激活和背面金属化。
步骤2)中所述N型场截止埋层形成的厚度为5um~25um。
步骤2)中所述N型衬底注入N型杂质为磷或砷。
本发明中新的场截止埋层制备工艺方案,在不采用氢注入工艺的前提下,实现了FZ区熔衬底上深结深的N型场截止埋层结构,确保了器件的漏电表现。同时,也规避了采用EPI外延衬底带来的器件鲁棒性和一致性的劣化效应,工艺简单,实现方便。
附图说明
图1是常规沟槽型IGBT器件的结构示意图,
图2是步骤2)的形成深结深N型场截止埋层的结构示意图,
图3是步骤3)背面进行晶圆的减薄工艺的结构示意图,
图4是步骤4)进行EPI外延层生长的结构示意图,
图5是步骤5)的结构示意图,
图6是步骤6)对背面进行晶圆的减薄工艺,将EPI外延层全部去除的结构示意图,
图7是步骤7)的结构示意图;
图中1是重掺杂的N型区。
具体实施方式
下面详细描述本发明的实施例,所述实施例的示例在附图中示出,其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的,仅用于解释本发明,而不能理解为对本发明的限制。
本发明如图1-7所示;一种形成IGBT场截止埋层的制备方法,包括以下步骤:
1)选用FZ硅片作为N型衬底;
2)去除N型衬底表面氧化层,在所述N型衬底的正面注入N型杂质并高温推结外延生长形成N型场截止埋层,如图2所示;
3)如图3所示,在所述N型衬底的背面进行减薄处理;将晶圆减薄到所需的厚度需求;
4)如图4所示,在所述N型场截止埋层上进行外延层生长,使最终晶圆的厚度(减薄后的FZ区熔衬底+EPI外延衬底)满足设计范围;
5)如图5所示,翻转所述N型衬底,在其背面(减薄工艺面)进行后续常规正面工艺(包含沟槽刻蚀,栅氧化层生长等),栅极的生长与刻蚀,P型井和重掺杂的N型区1的注入和激活,层间隔离层形成与刻蚀,以及发射极金属层的形成;
6)如图6所示,将所述外延层全部去除;
7)如图7所示,在所述N型场截止埋层上进行P型收集极的注入、激活和背面金属化。
步骤2)中所述N型场截止埋层形成的厚度为5um~25um。N型场截止埋层大于25um会对工艺加工提出挑战,需要高温很长时间的推井工艺,现实中很难实现量产。
步骤2)中所述N型衬底注入N型杂质为磷、砷或其它带有施主能级的杂质。
本案采用FZ硅片作为N型衬底,在N型衬底的正面通过注入结合高温(1200C~1250C)炉管长时间(>10小时)的推进工艺,首先形成符合设计要求的深结深N型场截止埋层(15um~25um)。然后在背面进行晶圆的减薄工艺,将晶圆减薄到最终的厚度需求(650V产品的最终厚度需求60um~70um;1200V产品的最终厚度需求120um~130um;1700V产品的最终厚度需求190um~200um;)。然后在正面(N型场截止埋层表面)进行EPI外延层生长,使最终厚度(减薄后的N型衬底+EPI外延衬底)能满足工厂可以接受的范围。EPI外延层生长不仅可以起到陪衬载片的作用,而且可以根据加工设备规格需求制备相应厚度的外延层,提高加工的灵活性,在完成器件正面加工工艺后,再进行晶圆减薄工艺,将EPI外延层全部去除。
对于本案所公开的内容,还有以下几点需要说明:
(1)、本案所公开的实施例附图只涉及到与本案所公开实施例所涉及到的结构,其他结构可参考通常设计;
(2)、在不冲突的情况下,本案所公开的实施例及实施例中的特征可以相互组合以得到新的实施例;
以上,仅为本案所公开的具体实施方式,但本公开的保护范围并不局限于此,本案所公开的保护范围应以权利要求的保护范围为准。

Claims (3)

1.一种形成IGBT场截止埋层的制备方法,其特征在于,包括以下步骤:
1)选用FZ硅片作为N型衬底;
2)去除N型衬底表面氧化层,在所述N型衬底的正面注入N型杂质并高温推结外延生长形成N型场截止埋层;
3)在所述N型衬底的背面进行减薄处理;
4)在所述N型场截止埋层上进行外延层生长;
5)翻转所述N型衬底,在其背面进行后续常规正面工艺,栅极的生长与刻蚀,P型井和重掺杂的N型区的注入和激活,层间隔离层形成与刻蚀,以及发射极金属层的形成;
6)将所述外延层全部去除;
7)在所述N型场截止埋层上进行P型收集极的注入、激活和背面金属化。
2.根据权利要求1所述的一种形成IGBT场截止埋层的制备方法,其特征在于,步骤2)中所述N型场截止埋层形成的厚度为5um~25um。
3.根据权利要求1所述的一种形成IGBT场截止埋层的制备方法,其特征在于,步骤2)中所述N型衬底注入N型杂质为磷或砷。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070120215A1 (en) * 2005-11-30 2007-05-31 Chong-Man Yun Power semiconductor device using silicon substrate as field stop layer and method of manufacturing the same
CN104576533A (zh) * 2013-10-24 2015-04-29 无锡华润上华半导体有限公司 具有反向导通结构的Trench IGBT的制备方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070120215A1 (en) * 2005-11-30 2007-05-31 Chong-Man Yun Power semiconductor device using silicon substrate as field stop layer and method of manufacturing the same
CN104576533A (zh) * 2013-10-24 2015-04-29 无锡华润上华半导体有限公司 具有反向导通结构的Trench IGBT的制备方法

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