CN113745262A - Display panel and preparation method thereof - Google Patents
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- CN113745262A CN113745262A CN202110948042.8A CN202110948042A CN113745262A CN 113745262 A CN113745262 A CN 113745262A CN 202110948042 A CN202110948042 A CN 202110948042A CN 113745262 A CN113745262 A CN 113745262A
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- 238000005240 physical vapour deposition Methods 0.000 claims description 5
- 238000003466 welding Methods 0.000 claims description 4
- 238000003825 pressing Methods 0.000 claims description 2
- 239000000463 material Substances 0.000 description 13
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
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- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract
The application discloses a display panel and a preparation method thereof. The array substrate comprises an array substrate and an opposite substrate, wherein a first VDD wire and a first VSS wire are formed on the surface of the array substrate in a patterning mode, and a second VDD wire and a second VSS wire are formed on the surface of the opposite substrate in a patterning mode. The first VDD wire is connected to the second VDD wire through the first conductive layer, the first VSS wire is connected to the second VSS wire through the second conductive layer, and therefore resistance of the in-plane wire of the display panel is greatly reduced, and brightness of each position of the display panel is uniform.
Description
Technical Field
The application relates to the technical field of display, in particular to a display panel and a preparation method thereof.
Background
Micro light emitting diode Display (Micro LED Display) is a new generation of Display technology, Micro LED inherits the characteristics of LED, and has the advantages of small size, light weight, high brightness, long service life, low power consumption, fast response time and strong controllability, the color gamut of the Micro LED is more than 120%, and PPI (pixel density) can reach 1500%. Therefore, more panel manufacturers participate in the development of Micro LED technology.
However, the micro LED display has many technical difficulties to be overcome, for example, in a region far from the VDD/VSS input terminal on the large-size display, the voltage drop of VDD and the voltage rise of VSS occur due to the wiring resistance, which causes the voltage difference between two ends of the LED chip (i.e., the light emitting device) to be reduced, the brightness to be reduced, and the brightness to be uneven on the whole surface.
Therefore, improvement of the current drop due to the resistance is important for the large-scale production of the micro LED.
Disclosure of Invention
The invention aims to provide a display panel and a preparation method thereof, and aims to solve the technical problems that voltage drop of VDD and voltage rise of VSS are caused by wiring resistance, and the voltage difference between two ends of a light-emitting device is reduced, so that the brightness of the display panel is uneven.
To achieve the above object, the present invention provides a display panel including: the array substrate is provided with a first VDD wire and a first VSS wire in a patterned manner; the opposite substrate is arranged opposite to the array substrate, and a second VDD wire and a second VSS wire are formed on the surface of the opposite substrate in a patterning mode; the light emitting device is arranged between the array substrate and the opposite substrate and is arranged in a staggered mode with the second VDD wiring and the second VSS wiring; the first VDD wire is connected to the second VDD wire through a first conductive layer, and the first VSS wire is connected to the second VSS wire through a second conductive layer.
Further, the first conducting layer and the second conducting layer are both metal connecting blocks; alternatively, the first conductive layer and the second conductive layer are both anisotropic conductive layers.
Further, the counter substrate includes: the cover plate, wherein the second VDD trace and the second VSS trace are arranged on one side surface of the cover plate in a patterning mode; and the protective layer is arranged on the cover plate and is provided with a first opening and a second opening, wherein the first opening is used for exposing the second VDD wiring, and the second opening is used for exposing the second VSS wiring.
Further, the array substrate includes: a glass substrate; a light shielding layer disposed on the glass substrate; the buffer layer is arranged on the glass substrate and covers the light shielding layer; the thin film transistor layer is arranged on the buffer layer and comprises an active layer, a gate layer and a source drain layer, wherein an interlayer insulating layer is arranged between the active layer and the gate layer as well as between the active layer and the source drain layer; the wiring layer is arranged on the same layer with the source drain layer; the passivation layer is arranged on the thin film transistor layer and covers a part of the source drain layer and a part of the routing layer; the conductive connecting layer penetrates through the passivation layer and is connected to part of the source drain layer and the routing layer; and the common connection layer is arranged on the conductive connection layer and is patterned to form a first electrode, a second electrode, the first VDD wire and the first VSS wire.
Further, a first connection portion of the light emitting device is connected to the first electrode, and a second connection portion of the light emitting device is connected to the second electrode; one side of the first conductive layer is connected to the first VDD trace, and the other side of the first conductive layer is connected to the second VDD trace through the first opening; one side of the second conductive layer is connected to the first VSS trace, and the other side of the second conductive layer is connected to the second VSS trace through the second opening.
In order to achieve the above object, the present invention further provides a method for manufacturing a display panel, comprising the following steps: forming an array substrate, wherein a first VDD wire and a first VSS wire are patterned on the surface of the array substrate; mounting a light emitting device on the array substrate; arranging a first conductive layer on the first VDD trace and a second conductive layer on the first VSS trace; forming an opposite substrate, wherein a second VDD wire and a second VSS wire are formed on the surface of the opposite substrate in a patterning mode, and the light-emitting device, the second VDD wire and the second VSS wire are arranged in a staggered mode; aligning and combining the array substrate and the opposite substrate; the first conducting layer and the second conducting layer are arranged between the array substrate and the opposite substrate; a pressing method or a welding method is adopted, so that the first VDD routing is fixedly connected to the second VDD routing through the first conductive layer; the first VSS trace is fixedly connected to the second VSS trace through the second conductive layer.
Further, the step of forming the counter substrate includes: patterning the second VDD wire and the second VSS wire on the cover plate; and forming a protective layer on the cover plate, covering a part of the second VDD trace and the second VSS trace, wherein the protective layer is provided with a first opening and a second opening, the first opening is used for exposing the second VDD trace, and the second opening is used for exposing the second VSS trace.
Further, the second VDD trace and the second VSS trace are formed on the cover plate by one of a printing method, and a physical vapor deposition method.
Further, in the step of forming an array substrate, the method includes: forming a light shielding layer on the glass substrate; forming a buffer layer on the glass substrate and covering the light-shielding layer; forming a thin film transistor layer on the buffer layer, wherein the thin film transistor layer is formed with an active layer, a gate layer, a source drain layer and a routing layer, an interlayer insulating layer is arranged between the active layer and the gate layer as well as between the source drain layer, and the routing layer and the source drain layer are arranged in the same layer; forming a passivation layer on the thin film transistor layer, wherein the passivation layer covers part of the source drain layer and part of the routing layer; carrying out hole digging treatment on the passivation layer to form a first via hole and a second via hole, wherein the first via hole is communicated to the surface of the source drain electrode layer, and the second via hole is communicated to the surface of the wiring layer; forming a conductive connecting layer on the passivation layer, wherein the conductive connecting layer is connected to a part of the source drain layer through the first via hole, and the conductive connecting layer is connected to the routing layer through the second via hole; and forming a common connection layer on the conductive connection layer, the common connection layer including a first electrode, a second electrode, the first VDD trace, and the first VSS trace.
Further, in the step of mounting the light emitting device on the array substrate, a first connection portion of the light emitting device is connected to the first electrode, and a second connection portion of the light emitting device is connected to the second electrode; in the step of performing alignment combination on the array substrate and the opposite substrate, one side of the first conductive layer is connected to the first VDD trace, and the other side of the first conductive layer is connected to the second VDD trace through the first opening; one side of the second conductive layer is connected to the first VSS trace, and the other side of the second conductive layer is connected to the second VSS trace through the second opening.
The display panel comprises an array substrate, an opposite substrate and a light-emitting device, wherein the array substrate and the opposite substrate are oppositely arranged, and the light-emitting device is mounted on the array substrate. The array substrate comprises an array substrate and an opposite substrate, wherein a first VDD wire and a first VSS wire are formed on the surface of the array substrate in a patterning mode, and a second VDD wire and a second VSS wire are formed on the surface of the opposite substrate in a patterning mode. The first VDD wire is connected to the second VDD wire through the first conductive layer, the first VSS wire is connected to the second VSS wire through the second conductive layer, and therefore resistance of the in-plane wire of the display panel is greatly reduced, and brightness of each position of the display panel is uniform.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a cross-sectional view of a display panel provided in embodiment 1 of the present application.
Fig. 2 is a schematic structural diagram of a display panel having a connection point provided in embodiment 1 of the present application.
Fig. 3 is a flowchart of a method for manufacturing a display panel provided in embodiment 1 of the present application.
Fig. 4 is a flowchart of forming an array substrate according to embodiment 1 of the present application.
Fig. 5 is a schematic cross-sectional view of forming an array substrate according to embodiment 1 of the present application.
Fig. 6 is a flowchart of forming a thin-film transistor layer according to embodiment 1 of the present application.
Fig. 7 is a schematic structural diagram of a light emitting device mounted on an array substrate according to embodiment 1 of the present application.
Fig. 8 is a schematic cross-sectional view of forming a counter substrate according to embodiment 1 of the present application.
Fig. 9 is a cross-sectional view of a display panel provided in embodiment 2 of the present application.
The components of the drawings are identified as follows:
1. an array substrate; 2. An opposing substrate;
3. a light emitting device; 41. A first metal connecting block;
42. a second metal connecting block; 43. A first anisotropic conductive layer;
44. a second anisotropic conductive layer; 11. A glass substrate;
12. a light-shielding layer; 13. A buffer layer;
14. a thin film transistor layer; 15. A wiring layer;
16. a passivation layer; 17. A conductive connection layer;
18. a common connection layer; 141. An active layer;
142. a gate layer; 143. A source drain layer;
144. an interlayer insulating layer; 441. A gate insulating layer;
442. a dielectric layer; 4420. Connecting holes;
161. a first via hole; 162. A second via hole;
181. a first electrode; 182. A second electrode;
183. a first VDD trace; 184. A first VSS line;
21. a cover plate; 22. A second VDD trace;
23. a second VSS line; 24. A protective layer;
241. a first opening; 242. A second opening;
31. a substrate layer; 32. An N-type semiconductor layer;
33. a P-type semiconductor layer; 34. A first connection portion;
35. a second connecting portion; 10. And connecting points.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. In the description of the present application, it is to be understood that the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
The embodiment of the application provides a display panel and a preparation method thereof, wherein the display panel comprises an array substrate, an opposite substrate and a light-emitting device, wherein the array substrate and the opposite substrate are oppositely arranged, and the light-emitting device is installed on the array substrate. A first VDD wire and a first VSS wire are formed on the surface of the array substrate in a patterning mode, and a second VDD wire and a second VSS wire are formed on the surface of the opposite substrate in a patterning mode. The first VDD wire is connected to the second VDD wire through a first conductive layer, and the first VSS wire is connected to the second VSS wire through a second conductive layer. The first conducting layer and the second conducting layer are both metal connecting blocks; alternatively, the first conductive layer and the second conductive layer are both anisotropic conductive layers. The structure of the display panel and the manufacturing method will be described in detail below by way of example.
Example 1
As shown in fig. 1, the present embodiment provides a display panel 100, which is a Micro LED display panel, including an array substrate 1 and a counter substrate 2 oppositely disposed, and a light emitting device 3 mounted on the array substrate 1. The surface of the array substrate 1 is patterned to form a first VDD trace 183 and a first VSS trace 184, and the surface of the opposite substrate 2 is patterned to form a second VDD trace 22 and a second VSS trace 23. The first VDD trace 183 is connected to the second VDD trace 22 through the first metal connection block 41, and the first VSS trace 184 is connected to the second VSS trace 23 through the second metal connection block 42, so that traces can be disposed in other regions (for example, a region where a thin film transistor and a capacitor are located) except for a light emitting region corresponding to the light emitting device 3, thereby greatly reducing the resistance of the in-plane traces of the display panel.
Specifically, the array substrate 1 includes a glass substrate 11, a light-shielding layer 12, a buffer layer 13, a thin-film transistor layer 14, a routing layer 15, a passivation layer 16, a conductive connection layer 17, and a common connection layer 18.
The light-shielding layer 12 is provided on the glass substrate 11, and the material used for the light-shielding layer 12 may be a metal material or another light-shielding material, which is not particularly limited herein.
The buffer layer 13 is provided on the glass substrate 11 and covers the light-shielding layer 12. The material used for the buffer layer 13 includes, but is not limited to, silicon nitride and silicon oxide.
The thin film transistor layer 14 is disposed on the buffer layer 13 and includes an active layer 141, a gate layer 142, a source drain layer 143, and an interlayer insulating layer 144 disposed between the active layer 141 and the gate layer 142 and between the source drain layer 143. The interlayer insulating layer 144 includes a gate insulating layer 441 and a dielectric layer 442.
Specifically, the active layer 141 is disposed on the buffer layer 13 and faces the light-shielding layer 12. The material used for the active layer 141 includes Indium-Gallium-Zinc Oxide (IGZO), Zinc Oxide (ZnO), Tin Oxide (SnO), Indium-Zinc Oxide (IZO), Gallium-Zinc Oxide (GaZnO), Zinc-Tin Oxide (ZTO), Indium-Tin Oxide (ITO), and a mixture thereof.
The gate insulating layer 441 is disposed on the active layer 141, and the material used for the gate insulating layer includes, but is not limited to, silicon nitride and silicon oxide.
The gate layer 142 is patterned on the gate insulating layer 441.
The dielectric layer 442 is disposed on the buffer layer 13 and covers the gate layer 142 and the active layer 141. The material used for the dielectric layer 442 includes, but is not limited to, silicon nitride, silicon oxide. The dielectric layer 442 is provided with two connection holes 4420 for exposing the active layer 141.
The same layer of source drain layer 143 and routing layer 15 are disposed on dielectric layer 442. The source/drain layer 143 fills the two connection holes 4420 and is connected to the active layer 141.
The passivation layer 16 is disposed on the thin film transistor layer 14, and covers a portion of the source/drain layer 143 and a portion of the routing layer 15. Materials used for the passivation layer 16 include, but are not limited to, silicon nitride, silicon oxide. The passivation layer 16 is provided with a first via 161 and a second via 162, the first via 161 is used for exposing the source drain layer 143, and the second via 162 is used for exposing the routing layer 15.
The conductive connection layer 17 passes through the passivation layer 16 and is connected to a portion of the source/drain layer 143 and the routing layer 15. One part of the conductive connecting layer 17 fills the first via 161, and the other part of the conductive connecting layer 17 connected to part of the source/drain layer 143 fills the second via 162 and is connected to the wiring layer 15. The conductive connection layer 17 is made of a material including, but not limited to, Indium Tin Oxide (ITO).
The common connection layer 18 is disposed on the conductive connection layer 17, and is patterned to form a first electrode 181, a second electrode 182, a first VDD trace 183, and a first VSS trace 184.
The light emitting device 3 is disposed between the array substrate 1 and the opposite substrate 2, and is disposed to be offset from the second VDD trace 22 and the second VSS trace 23. The light emitting device 3 is a Micro LED device, and includes a substrate layer 31, an N-type semiconductor layer 32, a P-type semiconductor layer 33, a first connection portion 34, and a second connection portion 35. The first connection portion 34 is an N-type electrode and is connected to the first electrode 181. The second connection portion 35 is a P-type electrode and is connected to the second electrode 182.
In the present embodiment, the opposite substrate 2 includes a cover plate 21, a second VDD trace 22, a second VSS trace 23 and a protection layer 24.
The cover 21 is a transparent cover 21, and the second VDD trace 22 and the second VSS trace 23 are patterned on a surface of one side of the cover 21.
The passivation layer 24 is disposed on the cover plate 21, wherein the passivation layer 24 has a first opening 241 for exposing the second VDD trace 22, and the passivation layer 24 has a second opening 242 for exposing the second VSS trace 23.
In this embodiment, one end of the first metal connection block 41 is connected to the second VDD trace 22 through the first opening 241, and the other end is directly connected to the first VDD trace 183; one end of the second metal block is connected to the second VSS trace 23 through the second opening 242, and the other end is directly connected to the first VSS trace 184, so as to implement signal connection between the array substrate 1 and the opposite substrate 2.
As shown in fig. 2, it can be seen from the cover 21 that the display panel 100 has a plurality of connection points 10 arranged in a matrix, where the connection points 10 are connection positions where the first VDD trace 183 is connected to the second VDD trace 22 through the first metal blocks, and the first VSS trace 184 is connected to the second VSS trace 23 through the second metal blocks. Wherein the number of connection points 10 may be increased or decreased according to the user's needs. That is, the user can realize the connection between the first VDD trace 183 and the second VDD trace 22 and the connection between the first VSS trace 184 and the second VSS trace 23 according to actual requirements.
In the display panel 100 provided in this embodiment, the wires can be disposed in other regions (for example, regions where the thin film transistor and the capacitor are located) except for the light emitting region corresponding to the light emitting device 3, which is beneficial to greatly reduce the resistance of the wires in the plane of the display panel, so that the brightness of each position of the display panel is uniform. In addition, in the embodiment, the second VDD trace 22 and the second VSS trace 23 are formed on the cover plate 21 by one of a printing method, and a physical vapor deposition method, so as to increase a line width, a film thickness, and the like, thereby implementing a resistor design without causing a negative effect on the array substrate 1 disposed under the opposite substrate 2. As shown in fig. 3, the present embodiment further provides a method for manufacturing a display panel, including the following manufacturing steps S11) -S15).
S11) forming an array substrate 1, wherein the surface of the array substrate 1 is patterned to form a first VDD trace 183 and a first VSS trace 184.
Specifically, as shown in fig. 4, in the step of forming the array substrate 1, the following preparation steps S111) to S118) are included.
S111) forming the light-shielding layer 12 on the glass substrate 11, see fig. 5. The material used for the light shielding layer 12 may be a metal material or another light shielding material, and is not particularly limited herein.
S112) forming a buffer layer 13 on the glass substrate 11 and covering the light-shielding layer 12, see fig. 5. The material used for the buffer layer 13 includes, but is not limited to, silicon nitride and silicon oxide.
S113) forming a thin film transistor layer 14 on the buffer layer 13, where the thin film transistor layer is formed with an active layer 141, a gate layer 142, a source/drain layer 143, and a routing layer 15, where an interlayer insulating layer 144 is disposed between the active layer 141 and the gate layer 142, and between the source/drain layers 143, and the routing layer 15 and the source/drain layer 143 are disposed on the same layer, as shown in fig. 5.
Specifically, as shown in fig. 6, the step of forming the thin-film transistor layer 14 on the buffer layer 13 includes the following preparation steps S1131) to S1136).
S1131) forming the active layer 141 on the buffer layer 13 and opposite to the light-shielding layer 12, refer to fig. 5. Specifically, the active layer 141 is formed by depositing one of a group consisting of Indium-Gallium-Zinc Oxide (IGZO), Zinc Oxide (ZnO), Tin Oxide (SnO), Indium-Zinc Oxide (IZO), Gallium-Zinc Oxide (GaZnO), Zinc-Tin Oxide (ZTO), Indium-Tin Oxide (ITO), and a mixture thereof on the buffer layer 13.
S1132) forming the gate insulating layer 441 on the active layer 141, referring to fig. 5. Specifically, an inorganic material (e.g., silicon nitride, silicon oxide) is deposited on the active layer 141 to form the gate insulating layer 441.
S1133) forming the gate electrode layer 142 on the gate insulating layer 441, referring to fig. 5. Specifically, a gate electrode layer 142 is formed by depositing a metal material on the gate insulating layer 441.
S1134) forming the dielectric layer 442 on the buffer layer 13 and covering the gate layer 142 and the active layer 141, referring to fig. 5. Specifically, an inorganic material (e.g., silicon nitride, silicon oxide) is deposited over dielectric layer 442 to form dielectric layer 442.
S1135) performing a hole digging process on the dielectric layer 442 to form two connection holes 4420 for exposing the active layer 141, wherein the two connection holes 4420 are respectively located at two sides of the active layer 141, as shown in fig. 5.
S1136) forming the source drain layer 143 and the routing layer 15 on the dielectric layer 442, wherein the source drain layer 143 fills the two connection holes 4420 and is connected to the active layer 141, as shown in fig. 5. Specifically, a metal material is deposited on the dielectric layer 442 to form a metal layer, and the metal layer is patterned to form the source/drain layer 143 and the routing layer 15.
S114) forming a passivation layer 16 on the thin film transistor layer 14, and covering a portion of the source/drain layer 143 and a portion of the routing layer 15, as shown in fig. 5. Specifically, an inorganic material (e.g., silicon nitride, silicon oxide) is deposited on thin-film-transistor layer 14 to form passivation layer 16.
S115) performing hole digging processing on the passivation layer 16 to form a first via hole 161 and a second via hole 162, where the first via hole 161 is communicated with the surface of the source/drain layer 143, and the second via hole 162 is communicated with the surface of the routing layer 15, as shown in fig. 5.
S116) forming a conductive connection layer 17 on the passivation layer 16, wherein a portion of the conductive connection layer 17 fills the first via hole 161 and is connected to a portion of the source/drain layer 143, and another portion of the conductive connection layer 17 fills the second via hole 162 and is connected to the routing layer 15, as shown in fig. 5. The conductive connection layer 17 is made of a material including, but not limited to, Indium Tin Oxide (ITO).
S117) forming a common connection layer 18 on the conductive connection layer 17, where the common connection layer 18 includes a first electrode 181, a second electrode 182, the first VDD routing 183, and the first VSS routing 184, as shown in fig. 5. Specifically, a metal material is deposited on the conductive connection layer 17 to form a metal layer, and the metal layer is patterned to form a first electrode 181, a second electrode 182, a first VDD trace 183, and a first VSS trace 184.
S12) mounting the light emitting device 3 on the array substrate 1, referring to fig. 7. Specifically, the light emitting device 3 is a Micro light emitting diode (Micro LED) having a first connection portion 34 and a second connection portion 35, the first connection portion 34 being connected to the first electrode 181, and the second connection portion 35 being connected to the second electrode 182.
S13) disposing a first conductive layer on the first VDD trace and a second conductive layer on the first VSS trace. The first conductive layer is a first metal connection block 41, and the second conductive layer is a second metal connection block 42.
S14) forming an opposite substrate 2, patterning the surface of the opposite substrate 2 to form a second VDD trace 22 and a second VSS trace 23, and arranging the light emitting device 3 in a staggered manner with respect to the second VDD trace 22 and the second VSS trace 23, with reference to fig. 8. Specifically, the second VDD trace 22 and the second VSS trace 23 are formed on the cover plate 21 by one of a printing method, and a physical vapor deposition method, so as to increase the line width, the film thickness, and the like, thereby implementing the resistor design.
S15) aligning and combining the array substrate 1 and the counter substrate 2, wherein the first conductive layer and the second conductive layer are provided between the array substrate 1 and the counter substrate 2, as shown in fig. 1. One side of the first metal connecting block 41 is connected to the first VDD routing line 183, and the other side is connected to the second VDD routing line 22 through the first opening 241; one side of the second metal connection block 42 is connected to the first VSS trace 184, and the other side is connected to the second VSS trace 23 through the second opening 242.
S16) using a soldering method, such that the first VDD trace 183 is fixedly connected to the second VDD trace 22 through the first conductive layer, and the first VSS trace 184 is fixedly connected to the second VSS trace 23 through the second conductive layer.
Specifically, as shown in fig. 1, a welding method is adopted, so that the first VDD trace 183 of the array substrate 1 is connected to the second VDD trace 22 of the opposite substrate 2 through the first metal connection block 41, and the first VSS trace 184 of the array substrate 1 is connected to the second VSS trace 23 of the opposite substrate 2 through the second metal connection block 42, so that traces can be disposed in other regions (for example, a region where a thin film transistor and a capacitor are disposed) except for a light emitting region corresponding to the light emitting device 3, thereby being beneficial to greatly reducing the resistance of the in-plane traces of the display panel. In addition, the counter substrate 2 does not adversely affect the array substrate 1 located therebelow.
Example 2
The present embodiment provides a display panel, which includes most of the technical features of embodiment 1, and is different in that the first VDD trace is connected to the second VDD trace through a first anisotropic conductive layer, and the first VSS trace is connected to the second VSS trace through a second anisotropic conductive layer.
Specifically, as shown in fig. 9, in the present embodiment, a display panel 200 is provided, in which a first VDD trace 183 is connected to a second VDD trace 22 through a first anisotropic conductive layer 43, and a first VSS trace 184 is connected to a second VSS trace 23 through a second anisotropic conductive layer 44, so as to implement signal connection between the array substrate 1 and the opposite substrate 2.
In the display panel 200 provided in this embodiment, the wires can be disposed in other regions (for example, regions where the thin film transistors and the capacitors are located) except for the light emitting region corresponding to the light emitting device 3, which is beneficial to greatly reduce the resistance of the wires in the plane of the display panel, so that the brightness of each position of the display panel is uniform. In addition, in the embodiment, the second VDD trace 22 and the second VSS trace 23 are formed on the cover plate 21 by one of a printing method, a printing method and a physical vapor deposition method, so as to implement a resistor design, and at the same time, the array substrate 1 disposed below the opposite substrate 2 is not adversely affected.
The present embodiment further provides a method for manufacturing a display panel, which includes most technical features of the method for manufacturing a display panel of embodiment 1, and the difference is that in the step of disposing the first Conductive layer on the first VDD routing line 22 and the second Conductive layer on the first VSS routing line 23, the material used for the first Conductive layer and the second Conductive layer is an Anisotropic Conductive Film (ACF). That is, the first anisotropic conductive layer 43 is formed by coating an anisotropic conductive paste on the first VDD routing 22 such that the first VDD routing 183 is connected to the second VDD routing 22 through the first anisotropic conductive layer 43; and coating the anisotropic conductive adhesive on the first VSS wiring 23 to form the second VSS wiring 23, so that the first VSS wiring 184 is connected to the second VSS wiring 23 through the second anisotropic conductive layer 44, as shown in fig. 9. In this embodiment, the first VDD trace 183 and the second VDD trace 22 are connected to each other through the anisotropic conductive layer, and the first VSS trace 184 and the second VSS trace 23 are connected to each other, so that after the step of aligning and assembling the array substrate 1 and the opposite substrate 2, the first VDD trace 183 is fixedly connected to the second VDD trace 22 through the first conductive layer, and the first VSS trace 184 is fixedly connected to the second VSS trace 23 through the second conductive layer by using a heating and pressurizing method or other methods instead of a welding method.
The display panel comprises an array substrate, an opposite substrate and a light-emitting device, wherein the array substrate and the opposite substrate are oppositely arranged, and the light-emitting device is mounted on the array substrate. The array substrate comprises an array substrate and an opposite substrate, wherein a first VDD wire and a first VSS wire are formed on the surface of the array substrate in a patterning mode, and a second VDD wire and a second VSS wire are formed on the surface of the opposite substrate in a patterning mode. The first VDD wire is connected to the second VDD wire through the first conductive layer, the first VSS wire is connected to the second VSS wire through the second conductive layer, and therefore resistance of the in-plane wire of the display panel is greatly reduced, and brightness of each position of the display panel is uniform.
The display panel and the manufacturing method thereof provided by the embodiments of the present application are described in detail above, and the principle and the implementation manner of the present application are explained by applying specific examples herein, and the description of the embodiments above is only used to help understanding the technical scheme and the core idea of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A display panel, comprising:
the array substrate is provided with a first VDD wire and a first VSS wire in a patterned manner;
the opposite substrate is arranged opposite to the array substrate, and a second VDD wire and a second VSS wire are formed on the surface of the opposite substrate in a patterning mode; and
the light-emitting device is arranged between the array substrate and the opposite substrate and is arranged in a staggered mode with the second VDD wiring and the second VSS wiring;
the first VDD wire is connected to the second VDD wire through a first conductive layer, and the first VSS wire is connected to the second VSS wire through a second conductive layer.
2. The display panel according to claim 1,
the first conducting layer and the second conducting layer are both metal connecting blocks; alternatively, the first and second electrodes may be,
the first conductive layer and the second conductive layer are both anisotropic conductive layers.
3. The display panel according to claim 1, wherein the counter substrate comprises:
the cover plate, wherein the second VDD trace and the second VSS trace are arranged on one side surface of the cover plate in a patterning mode; and
and the protective layer is arranged on the cover plate and provided with a first opening and a second opening, wherein the first opening is used for exposing the second VDD wiring, and the second opening is used for exposing the second VSS wiring.
4. The display panel according to claim 3, wherein the array substrate comprises:
a glass substrate;
a light shielding layer disposed on the glass substrate;
the buffer layer is arranged on the glass substrate and covers the light shielding layer;
the thin film transistor layer is arranged on the buffer layer and comprises an active layer, a gate layer and a source drain layer, wherein an interlayer insulating layer is arranged between the active layer and the gate layer as well as between the active layer and the source drain layer;
the wiring layer is arranged on the same layer with the source drain layer;
the passivation layer is arranged on the thin film transistor layer and covers a part of the source drain layer and a part of the routing layer;
the conductive connecting layer penetrates through the passivation layer and is connected to part of the source drain layer and the routing layer; and
and the common connection layer is arranged on the conductive connection layer and is patterned to form a first electrode, a second electrode, the first VDD wire and the first VSS wire.
5. The display panel according to claim 4,
a first connection portion of the light emitting device is connected to the first electrode, and a second connection portion of the light emitting device is connected to the second electrode;
one side of the first conductive layer is connected to the first VDD trace, and the other side of the first conductive layer is connected to the second VDD trace through the first opening; one side of the second conductive layer is connected to the first VSS trace, and the other side of the second conductive layer is connected to the second VSS trace through the second opening.
6. The preparation method of the display panel is characterized by comprising the following preparation steps of:
forming an array substrate, wherein a first VDD wire and a first VSS wire are patterned on the surface of the array substrate; mounting a light emitting device on the array substrate;
arranging a first conductive layer on the first VDD trace and a second conductive layer on the first VSS trace;
forming an opposite substrate, wherein a second VDD wire and a second VSS wire are formed on the surface of the opposite substrate in a patterning mode, and the light-emitting device, the second VDD wire and the second VSS wire are arranged in a staggered mode;
aligning and combining the array substrate and the opposite substrate; the first conducting layer and the second conducting layer are arranged between the array substrate and the opposite substrate;
a pressing method or a welding method is adopted, so that the first VDD routing is fixedly connected to the second VDD routing through the first conductive layer; the first VSS trace is fixedly connected to the second VSS trace through the second conductive layer.
7. The method for manufacturing a display panel according to claim 6,
the step of forming the counter substrate includes:
patterning the second VDD wire and the second VSS wire on a cover plate; and
and forming a protective layer on the cover plate and covering a part of the second VDD wiring and the second VSS wiring, wherein the protective layer is provided with a first opening and a second opening, the first opening is used for exposing the second VDD wiring, and the second opening is used for exposing the second VSS wiring.
8. The method as claimed in claim 7, wherein the second VDD trace and the second VSS trace are formed on the cover plate by one of a printing method, a printing method and a physical vapor deposition method.
9. The method for manufacturing a display panel according to claim 6,
in the step of forming the array substrate, the method includes:
forming a light shielding layer on the glass substrate;
forming a buffer layer on the glass substrate and covering the light-shielding layer;
forming a thin film transistor layer on the buffer layer, wherein the thin film transistor layer is formed with an active layer, a gate layer, a source drain layer and a routing layer, an interlayer insulating layer is arranged between the active layer and the gate layer as well as between the source drain layer, and the routing layer and the source drain layer are arranged in the same layer;
forming a passivation layer on the thin film transistor layer, wherein the passivation layer covers part of the source drain layer and part of the routing layer;
carrying out hole digging treatment on the passivation layer to form a first via hole and a second via hole, wherein the first via hole is communicated to the surface of the source drain electrode layer, and the second via hole is communicated to the surface of the wiring layer;
forming a conductive connecting layer on the passivation layer, wherein the conductive connecting layer is connected to a part of the source drain layer through the first via hole, and the conductive connecting layer is connected to the routing layer through the second via hole; and
forming a common connection layer on the conductive connection layer, wherein the common connection layer includes a first electrode, a second electrode, the first VDD trace and the first VSS trace.
10. The method for manufacturing a display panel according to claim 9,
in the step of mounting the light emitting device on the array substrate,
a first connection portion of the light emitting device is connected to the first electrode, and a second connection portion of the light emitting device is connected to the second electrode;
in the step of aligning and combining the array substrate and the counter substrate,
one side of the first conductive layer is connected to the first VDD trace, and the other side of the first conductive layer is connected to the second VDD trace through the first opening; one side of the second conductive layer is connected to the first VSS trace, and the other side of the second conductive layer is connected to the second VSS trace through the second opening.
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| CN108511507A (en) * | 2018-06-07 | 2018-09-07 | 京东方科技集团股份有限公司 | A kind of display panel and display device |
| CN109300430A (en) * | 2018-07-18 | 2019-02-01 | 友达光电股份有限公司 | Light emitting device and method for manufacturing the same |
| CN109935618A (en) * | 2019-03-06 | 2019-06-25 | 深圳市华星光电半导体显示技术有限公司 | A kind of OLED display panel and preparation method thereof |
| CN110061147A (en) * | 2019-04-24 | 2019-07-26 | 昆山国显光电有限公司 | Display panel and preparation method thereof, display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108511507A (en) * | 2018-06-07 | 2018-09-07 | 京东方科技集团股份有限公司 | A kind of display panel and display device |
| CN109300430A (en) * | 2018-07-18 | 2019-02-01 | 友达光电股份有限公司 | Light emitting device and method for manufacturing the same |
| CN109935618A (en) * | 2019-03-06 | 2019-06-25 | 深圳市华星光电半导体显示技术有限公司 | A kind of OLED display panel and preparation method thereof |
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