CN113744690A

CN113744690A - Level conversion circuit, display driving circuit and silicon-based organic light emitting display device

Info

Publication number: CN113744690A
Application number: CN202110991006.XA
Authority: CN
Inventors: 钱栋; 周志伟
Original assignee: Hefei Shiya Technology Co ltd
Current assignee: Hefei Shiya Technology Co ltd
Priority date: 2021-08-26
Filing date: 2021-08-26
Publication date: 2021-12-03
Anticipated expiration: 2041-08-26
Also published as: CN113744690B

Abstract

The invention provides a level conversion circuit, a display driving circuit and a silicon-based organic light-emitting display device, which comprise a first input module and a first capacitor; the control end of the first input module is electrically connected with a first input signal end of the level conversion circuit, the first input end of the first input module is electrically connected with a first power supply voltage end, the second input end of the first input module is electrically connected with a second power supply voltage end, and the output end of the first input module is electrically connected with a first electrode plate of the first capacitor; the second polar plate of the first capacitor is electrically connected with the first output signal end of the level switching circuit; in a first time period, a first input signal end inputs a first input voltage, a first input module is controlled to conduct and electrically connect a second power supply voltage end with a first pole plate of a first capacitor, and in a second time period, a second input voltage is input into the first input signal end, and the first input module is controlled to conduct and electrically connect the first power supply voltage end with the first pole plate of the first capacitor. The invention reduces the complexity of the circuit.

Description

Level conversion circuit, display driving circuit and silicon-based organic light emitting display device

Technical Field

The invention relates to the technical field of display, in particular to a level conversion circuit, a display driving circuit and a silicon-based organic light-emitting display device.

Background

Generally, when a display displays a picture, a data signal represented by a digital signal needs to be subjected to digital-to-analog conversion and then supplied to a display panel so that the display panel displays the picture. In order to improve the driving capability of the data signal, the data signal is generally subjected to a boost conversion by a level shift circuit to improve the driving capability and then subjected to a digital-to-analog conversion. However, the voltage signal input to the level shift circuit easily causes the voltage across the two terminals of the transistor in the level shift circuit to exceed the tolerance range.

Disclosure of Invention

The invention provides a level conversion circuit, a display driving circuit and a silicon-based organic light-emitting display device, which are used for realizing the conversion of a voltage signal input to a level shift circuit, and do not need to introduce a negative power supply, thereby reducing the complexity of the circuit.

In a first aspect, an embodiment of the present invention provides a level shift circuit, including a first input module and a first capacitor;

the control end of the first input module is electrically connected with the first input signal end of the level conversion circuit, the first input end of the first input module is electrically connected with the first power supply voltage end, the second input end of the first input module is electrically connected with the second power supply voltage end, and the output end of the first input module is electrically connected with the first polar plate of the first capacitor;

the second polar plate of the first capacitor is electrically connected with the first output signal end of the level switching circuit;

in a first period, inputting a first input voltage into the first input signal end, controlling the first input module to electrically connect the second power supply voltage end with the first pole plate of the first capacitor, and in a second period, inputting the second input voltage into the first input signal end, controlling the first input module to electrically connect the first power supply voltage end with the first pole plate of the first capacitor;

wherein a voltage of the first power supply voltage terminal is not equal to a voltage of the second power supply voltage terminal.

In a second aspect, an embodiment of the present invention provides a display driving circuit, including the level shift circuit of the first aspect, and a level shift circuit;

and a first output signal end of the level conversion circuit is electrically connected with a first end of the level shift circuit, and a second output signal end of the level conversion circuit is electrically connected with a second end of the level shift circuit.

In a third aspect, embodiments of the present invention provide a silicon-based organic light emitting display device, including the display driving circuit according to the second aspect, where the display driving circuit is integrated on a silicon-based substrate of the silicon-based organic light emitting display device.

In the embodiment of the invention, in the first period, the first input signal end inputs the first input voltage, and the voltage of the second power supply voltage end is applied to the first plate of the first capacitor. Since the voltage difference across the first capacitor remains constant, the voltage at the first output signal terminal corresponds to the voltage variation at the second supply voltage terminal. In a second period, the first input signal terminal inputs a second input voltage, and a voltage of the first power supply voltage terminal is applied to the first plate of the first capacitor. Since the voltage difference across the first capacitor remains constant, the voltage at the first output signal terminal corresponds to the voltage variation at the first power supply voltage terminal. It can be seen that the first input voltage is converted into a voltage corresponding to the second power supply voltage terminal by the level conversion circuit, and the second input voltage is converted into a voltage corresponding to the first power supply voltage terminal by the level conversion circuit. The level shift circuit provided by the embodiment of the invention converts the voltage signal input to the level shift circuit without introducing a negative power supply, thereby reducing the complexity of the circuit.

Drawings

Fig. 1 is a circuit diagram of a level shift circuit according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of another level shifter according to an embodiment of the present invention;

FIG. 3 is a circuit diagram of another level shifter according to an embodiment of the present invention;

FIG. 4 is a timing diagram of a level shift circuit according to an embodiment of the present invention;

FIG. 5 is a circuit diagram of another level shifter according to an embodiment of the present invention;

FIG. 6 is a timing diagram of another level shifting circuit according to an embodiment of the present invention;

FIG. 7 is a circuit diagram of another level shifter according to an embodiment of the present invention;

FIG. 8 is a circuit diagram of another level shifter circuit according to an embodiment of the present invention;

FIG. 9 is a circuit diagram of another level shifter according to an embodiment of the present invention;

FIG. 10 is a circuit diagram of another level shifter according to an embodiment of the present invention;

FIG. 11 is a timing diagram of another level shift circuit according to an embodiment of the present invention;

FIG. 12 is a circuit diagram of another level shifter circuit according to an embodiment of the present invention;

FIG. 13 is a timing diagram of another level shifting circuit according to an embodiment of the present invention;

FIG. 14 is a circuit diagram of another level shifter circuit according to an embodiment of the present invention;

FIG. 15 is a circuit diagram of another level shifter according to an embodiment of the present invention;

FIG. 16 is a circuit diagram of a display driver circuit according to an embodiment of the present invention;

fig. 17 is a schematic diagram of a silicon-based organic light emitting display device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a circuit schematic diagram of a level shift circuit according to an embodiment of the present invention, and referring to fig. 1, the level shift circuit includes a first input module 10 and a first capacitor C1. The control terminal of the first input module 10 is electrically connected to the first input signal terminal IN1 of the level shifter circuit, the first input terminal of the first input module 10 is electrically connected to the first power voltage terminal VSS, the second input terminal of the first input module 10 is electrically connected to the second power voltage terminal DVDD, and the output terminal of the first input module 10 is electrically connected to the first plate of the first capacitor C1. The second plate of the first capacitor C1 is electrically connected to the first output signal terminal L1 of the level shifter circuit. IN the first period, the first input signal terminal IN1 inputs the first input voltage, and controls the first input module 10 to electrically connect the second power voltage terminal DVDD to the first plate of the first capacitor C1, and the voltage of the second power voltage terminal DVDD is applied to the first plate of the first capacitor C1. IN the second period, the first input signal terminal IN1 inputs the second input voltage, and controls the first input module 10 to electrically connect the first power voltage terminal VSS with the first plate of the first capacitor C1, and the voltage of the first power voltage terminal VSS is applied to the first plate of the first capacitor C1. The voltage of the first power voltage terminal VSS is not equal to the voltage of the second power voltage terminal DVDD.

IN the embodiment of the present invention, the first input signal terminal IN1 inputs the first input voltage and the voltage of the second power voltage terminal DVDD is applied to the first plate of the first capacitor C1 during the first period. Since the voltage difference across the first capacitor C1 remains constant, the voltage of the first output signal terminal L1 corresponds to the voltage variation of the second power voltage terminal DVDD. IN the second period, the first input signal terminal IN1 inputs the second input voltage, and the voltage of the first power supply voltage terminal VSS is applied to the first plate of the first capacitor C1. Since the voltage difference across the first capacitor C1 remains unchanged, the voltage of the first output signal terminal L1 corresponds to the voltage variation of the first power supply voltage terminal VSS. It can be seen that the first input voltage is converted into a voltage corresponding to the second power voltage terminal DVDD by the level conversion circuit, and the second input voltage is converted into a voltage corresponding to the first power voltage terminal VSS by the level conversion circuit. The level shift circuit provided by the embodiment of the invention converts the voltage signal input to the level shift circuit without introducing a negative power supply, thereby reducing the complexity of the circuit.

Fig. 2 is a circuit schematic diagram of another level shift circuit according to an embodiment of the present invention, and referring to fig. 2, the first input module 10 includes a first switch unit 11 and a second switch unit 12. The control terminal of the first switch unit 11 is electrically connected to the first input signal terminal IN1, the first terminal of the first switch unit 11 is electrically connected to the first power voltage terminal VSS, and the second terminal of the first switch unit 11 is electrically connected to the first plate of the first capacitor C1. A control terminal of the second switch unit 12 is electrically connected to the first input signal terminal IN1, a first terminal of the second switch unit 12 is electrically connected to the second power voltage terminal DVDD, and a second terminal of the second switch unit 12 is electrically connected to the first plate of the first capacitor C1. IN the first period, the first input signal terminal IN1 inputs the first input voltage, controls the first switching unit 11 to be turned off, and controls the second switching unit 12 to be turned on, electrically connects the second power voltage terminal DVDD to the first plate of the first capacitor C1, and the voltage of the second power voltage terminal DVDD is applied to the first plate of the first capacitor C1. IN the second period, the first input signal terminal IN1 inputs the second input voltage, controls the second switching unit 12 to be turned off, and the first switching unit 11 to be turned on to electrically connect the first power supply voltage terminal VSS with the first plate of the first capacitor C1, the voltage of the first power supply voltage terminal VSS being applied to the first plate of the first capacitor C1.

Referring to fig. 3, the first switch unit 11 includes a first transistor M1, a gate of the first transistor M1 is electrically connected to the first input signal terminal IN1, a first pole of the first transistor M1 is electrically connected to the first power voltage terminal VSS, and a second pole of the first transistor M1 is electrically connected to the first plate of the first capacitor C1. The second switching unit 12 includes a second transistor M2, a gate of the second transistor M2 is electrically connected to the first input signal terminal IN1, a first pole of the second transistor M2 is electrically connected to the second power voltage terminal DVDD, and a second pole of the second transistor M2 is electrically connected to the first plate of the first capacitor C1.

Fig. 4 is a timing diagram of a level shift circuit according to an embodiment of the invention, and referring to fig. 3 and 4, the first transistor M1 is an N-type transistor, and the second transistor M2 is a P-type transistor. The first input voltage is less than the second input voltage. The voltage of the first power voltage terminal VSS is less than the voltage of the second power voltage terminal DVDD. IN the first period, the first input signal terminal IN1 inputs the first input voltage, which is lower than the second input voltage, and the first input voltage is low, controlling the first transistor M1 to be turned off, the second transistor M2 to be turned on, electrically connecting the second power voltage terminal DVDD to the first plate of the first capacitor C1, and the voltage of the second power voltage terminal DVDD is applied to the first plate of the first capacitor C1. IN the second period, the first input signal terminal IN1 receives the second input voltage, the first input voltage is lower than the second input voltage, the second input voltage is high, the second transistor M2 is controlled to be turned off, the first transistor M1 is controlled to be turned on, the first power supply voltage terminal VSS is electrically connected to the first plate of the first capacitor C1, and the voltage of the first power supply voltage terminal VSS is applied to the first plate of the first capacitor C1.

Illustratively, the voltage of the first power voltage terminal VSS is 0V, and the voltage of the second power voltage terminal DVDD is 1.2V. IN the first period, the first input signal terminal IN1 inputs the first input voltage, the second transistor M2 is turned on, the first plate of the first capacitor C1 is raised from 0V to 1.2V, and the voltage of the first output signal terminal L1 is correspondingly raised to 1.2V, for example, from-1.2V to 0V, because the voltage difference across the first capacitor C1 remains unchanged. IN the second period, the first input signal terminal IN1 inputs the second input voltage, the first transistor M1 is turned on, the first plate of the first capacitor C1 is decreased from 1.2V to 0V, and the voltage of the first output signal terminal L1 is correspondingly decreased by 1.2V, for example, from 0V to-1.2V, because the voltage difference between the two ends of the first capacitor C1 remains unchanged.

Fig. 5 is a circuit schematic diagram of another level shift circuit according to an embodiment of the present invention, and fig. 6 is a timing diagram of another level shift circuit according to an embodiment of the present invention, referring to fig. 5 and fig. 6, the first transistor M1 is a P-type transistor, and the second transistor M2 is an N-type transistor. The first input voltage is greater than the second input voltage. The voltage of the first power voltage terminal VSS is greater than the voltage of the second power voltage terminal DVDD. IN the first period, the first input signal terminal IN1 inputs the first input voltage, which is greater than the second input voltage, the first input voltage is high, the first transistor M1 is controlled to be turned off, the second transistor M2 is controlled to be turned on, the second power voltage terminal DVDD is electrically connected to the first plate of the first capacitor C1, and the voltage of the second power voltage terminal DVDD is applied to the first plate of the first capacitor C1. IN the second period, the first input signal terminal IN1 receives the second input voltage, the first input voltage is greater than the second input voltage, the second input voltage is low, the second transistor M2 is controlled to be turned off, the first transistor M1 is controlled to be turned on, the first power supply voltage terminal VSS is electrically connected to the first plate of the first capacitor C1, and the voltage of the first power supply voltage terminal VSS is applied to the first plate of the first capacitor C1.

Illustratively, the voltage of the first power voltage terminal VSS is 0V, and the voltage of the second power voltage terminal DVDD is-1.2V. IN the first period, the first input signal terminal IN1 inputs the first input voltage, the second transistor M2 is turned on, the first plate of the first capacitor C1 is decreased from 0V to-1.2V, and the voltage of the first output signal terminal L1 is correspondingly decreased by 1.2V, for example, from 1.2V to 0V, because the voltage difference between the two ends of the first capacitor C1 remains unchanged. IN the second period, the first input signal terminal IN1 inputs the second input voltage, the first transistor M1 is turned on, the first plate of the first capacitor C1 is raised from-1.2V to 0V, and the voltage of the first output signal terminal L1 is correspondingly raised to 1.2V, for example, from 0V to 1.2V, because the voltage difference across the first capacitor C1 remains unchanged.

Fig. 7 is a circuit schematic diagram of another level shift circuit according to an embodiment of the present invention, and referring to fig. 7, the level shift circuit further includes a third switching unit 13, a first terminal of the third switching unit 13 is electrically connected to the first power voltage terminal VSS, and a second terminal of the third switching unit 13 is electrically connected to the second plate of the first capacitor C1. In the first period, the third switching unit 13 is turned on to conductively electrically connect the second plate of the first capacitor C1 with the first power supply voltage terminal VSS. In the second period, the third switching unit 13 is turned off. In the embodiment of the present invention, the level shift circuit further includes a third switching unit 13. In the first period, the voltage of the second power voltage terminal DVDD is applied to the first plate of the first capacitor C1, the third switching unit 13 is turned on, the voltage of the first power voltage terminal VSS is applied to the second plate of the first capacitor C1, and the voltage difference across the first capacitor C1 is the difference between the voltages of the first and second power voltage terminals VSS and DVDD. In the second period, the voltage of the first power voltage terminal VSS is applied to the first plate of the first capacitor C1, and the voltage of the first output signal terminal L1 becomes VSS-Dvdd since the voltage difference across the first capacitor remains unchanged. Wherein Vss is a voltage of the first power voltage terminal Vss, and Dvdd is a voltage of the second power voltage terminal Dvdd.

It should be noted that the third switching unit 13 is beneficial to ensure the operation stability of the level conversion circuit. The third switching unit 13 may employ an N-type transistor and/or a P-type transistor. If the third switching unit 13 employs an N-type transistor, the third switching unit 13 is applied with a high level and the third switching unit 13 is turned on in the first period, and the third switching unit 13 is applied with a low level and the third switching unit 13 is turned off in the second period. If the third switching unit 13 employs a P-type transistor, the third switching unit 13 is applied with a low level and the third switching unit 13 is turned on in the first period, and the third switching unit 13 is applied with a high level and the third switching unit 13 is turned off in the second period.

Fig. 8 is a circuit schematic diagram of another level shift circuit according to an embodiment of the present invention, and referring to fig. 8, the level shift circuit further includes a second input module 20 and a second capacitor C2. The control terminal of the second input module 20 is electrically connected to the second input signal terminal IN2 of the level shifter, the first input terminal of the second input module 20 is electrically connected to the first power voltage terminal VSS, the second input terminal of the second input module 20 is electrically connected to the second power voltage terminal DVDD, and the output terminal of the second input module 20 is electrically connected to the first plate of the second capacitor C2. The second plate of the second capacitor C2 is electrically connected to the second output signal terminal L2 of the level shifter circuit. IN the first period, the second input signal terminal IN2 inputs the second input voltage, and controls the second input module 20 to electrically connect the first power voltage terminal VSS with the first plate of the second capacitor C2. The voltage of the first power supply voltage terminal VSS is applied to the first plate of the second capacitor C2. IN the second period, the second input signal terminal IN2 inputs the first input voltage, and controls the second input module 20 to electrically connect the second power voltage terminal DVDD to the first plate of the second capacitor C2. The voltage of the second power voltage terminal DVDD is applied to the first plate of the second capacitor C2. In the embodiment of the present invention, when the first plate of the first capacitor C1 inputs the voltage of the second power voltage terminal DVDD, the first plate of the second capacitor C2 inputs the voltage of the first power voltage terminal VSS. When the first plate of the first capacitor C1 receives the voltage of the first power voltage terminal VSS, the first plate of the second capacitor C2 receives the voltage of the second power voltage terminal DVDD. That is to say, the embodiment of the present invention implements voltage conversion by cross-coupling the first capacitor C1 and the second capacitor C2.

Fig. 9 is a circuit schematic diagram of another level shift circuit according to an embodiment of the present invention, and referring to fig. 9, the second input module 20 includes a fourth switching unit 21 and a fifth switching unit 22. The control terminal of the fourth switch unit 21 is electrically connected to the second input signal terminal IN2, the first terminal of the fourth switch unit 21 is electrically connected to the first power voltage terminal VSS, and the second terminal of the fourth switch unit 21 is electrically connected to the first plate of the second capacitor C2. A control terminal of the fifth switching unit 22 is electrically connected to the second input signal terminal IN2, a first terminal of the fifth switching unit 22 is electrically connected to the second power voltage terminal DVDD, and a second terminal of the fifth switching unit 22 is electrically connected to the first plate of the second capacitor C2.

Referring to fig. 10, the fourth switching unit 21 includes a fourth transistor M4, a gate of the fourth transistor M4 is electrically connected to the second input signal terminal IN2, a first pole of the fourth transistor M4 is electrically connected to the first power voltage terminal VSS, and a second pole of the fourth transistor M4 is electrically connected to the first pole of the second capacitor C2. The fifth switching unit 22 includes a fifth transistor M5, a gate of the fifth transistor M5 is electrically connected to the second input signal terminal IN2, a first pole of the fifth transistor M5 is electrically connected to the second power voltage terminal DVDD, and a second pole of the fifth transistor M5 is electrically connected to the first plate of the second capacitor C2.

Fig. 11 is a timing diagram of another level shift circuit according to an embodiment of the invention, and referring to fig. 10 and 11, the fourth transistor M4 is an N-type transistor, and the fifth transistor M5 is a P-type transistor. The first input voltage is less than the second input voltage. The voltage of the first power voltage terminal VSS is less than the voltage of the second power voltage terminal DVDD. IN the first period, the second input signal terminal IN2 receives the second input voltage, the first input voltage is lower than the second input voltage, the second input voltage is high, the fifth transistor M5 is controlled to be turned off, the fourth transistor M4 is controlled to be turned on, the first power voltage terminal VSS is electrically connected to the first plate of the second capacitor C2 IN a turned-on manner, and the voltage of the first power voltage terminal VSS is applied to the first plate of the second capacitor C2. IN the second period, the second input signal terminal IN2 inputs the first input voltage, which is lower than the second input voltage, the first input voltage is low, the fourth transistor M4 is controlled to be turned off, the fifth transistor M5 is controlled to be turned on, the second power voltage terminal DVDD is electrically connected to the first plate of the second capacitor C2, and the voltage of the second power voltage terminal DVDD is applied to the first plate of the second capacitor C2.

For example, the voltage of the first power voltage terminal VSS is 0V, the voltage of the second power voltage terminal DVDD is 1.2V, the first input voltage is equal to 0V, and the second input voltage is equal to 1.2V. IN the first period, the first input signal terminal IN1 inputs 0V, the second pole voltage of the second transistor M2 is 1.2V, the gate-source voltage difference of the second transistor M2 is 1.2V, the gate-source voltage difference of the second transistor M2 is greater than the threshold voltage thereof, the second transistor M2 is turned on, the first plate of the first capacitor C1 is raised from 0V to 1.2V, and since the voltage difference across the first capacitor C1 remains unchanged, the voltage of the first output signal terminal L1 is correspondingly raised to 1.2V and raised from-1.2V to 0V. The voltage of the second input signal terminal IN2 is 1.2V, the voltage of the first electrode of the fourth transistor M4 is 0V, the voltage difference of the gate source of the fourth transistor M4 is 1.2V, the voltage difference of the gate source of the fourth transistor M4 is greater than the threshold voltage thereof, the fourth transistor M4 is turned on, the first plate of the second capacitor C2 is reduced from 1.2V to 0V, and the voltage difference of the two ends of the second capacitor C2 remains unchanged, so the voltage of the second output signal terminal L2 is correspondingly reduced by 1.2V, and is reduced from 0V to-1.2V. IN the second period, the first input signal terminal IN1 inputs 1.2V, the gate-source voltage difference of the first transistor M1 is 1.2V, the gate-source voltage difference of the first transistor M1 is greater than the threshold voltage thereof, the first transistor M1 is turned on, the first plate of the first capacitor C1 is reduced from 1.2V to 0V, and since the voltage difference across the first capacitor C1 remains unchanged, the voltage of the first output signal terminal L1 is correspondingly reduced by 1.2V, from 0V to-1.2V. The second input signal terminal IN2 inputs 0V, the gate-source voltage difference of the fifth transistor M5 is 1.2V, the gate-source voltage difference of the fifth transistor M5 is greater than the threshold voltage thereof, the fifth transistor M5 is turned on, the first plate of the second capacitor C2 is raised from 0V to 1.2V, and since the voltage difference between the two ends of the second capacitor C2 remains unchanged, the voltage of the second output signal terminal L2 is correspondingly raised from 1.2V to 0V from-1.2V.

Fig. 12 is a circuit schematic diagram of another level shift circuit according to an embodiment of the present invention, fig. 13 is a timing diagram of another level shift circuit according to an embodiment of the present invention, the fourth transistor M4 is a P-type transistor, and the fifth transistor M5 is an N-type transistor. The first input voltage is greater than the second input voltage. The voltage of the first power voltage terminal VSS is greater than the voltage of the second power voltage terminal DVDD. IN the first period, the second input signal terminal IN2 receives the second input voltage, the first input voltage is greater than the second input voltage, the second input voltage is low, the fifth transistor M5 is controlled to be turned off, the fourth transistor M4 is controlled to be turned on, the first power voltage terminal VSS is electrically connected to the first plate of the second capacitor C2 IN a conductive manner, and the voltage of the first power voltage terminal VSS is applied to the first plate of the second capacitor C2. IN the second period, the second input signal terminal IN2 inputs the first input voltage, which is greater than the second input voltage, the first input voltage is high, the fourth transistor M4 is controlled to be turned off, the fifth transistor M5 is controlled to be turned on, the second power voltage terminal DVDD is electrically connected to the first plate of the second capacitor C2, and the voltage of the second power voltage terminal DVDD is applied to the first plate of the second capacitor C2.

Illustratively, the first power voltage terminal VSS is 0V, the second power voltage terminal DVDD is-1.2V, the first input voltage is equal to 0V, and the second input voltage is equal to-1.2V. IN the first period, the first input signal terminal IN1 inputs 0V, the gate-source voltage difference of the second transistor M2 is 1.2V, the gate-source voltage difference of the second transistor M2 is greater than the threshold voltage thereof, the second transistor M2 is turned on, the first plate of the first capacitor C1 is decreased from 0V to-1.2V, and since the voltage difference across the first capacitor C1 remains unchanged, the voltage of the first output signal terminal L1 is correspondingly decreased by 1.2V, and is decreased from 1.2V to 0V. The second input signal terminal IN2 receives a voltage of-1.2V, the gate-source voltage difference of the fourth transistor M4 is 1.2V, the gate-source voltage difference of the fourth transistor M4 is greater than the threshold voltage thereof, the fourth transistor M4 is turned on, the first plate of the second capacitor C2 is raised from-1.2V to 0V, and the voltage difference between the two ends of the second capacitor C2 remains unchanged, so the voltage of the second output signal terminal L2 is correspondingly raised to 1.2V, and is raised from 0V to 1.2V. IN the second period, the first input signal terminal IN1 is inputted with-1.2V, the gate-source voltage difference of the first transistor M1 is 1.2V, the gate-source voltage difference of the first transistor M1 is greater than the threshold voltage thereof, the first transistor M1 is turned on, the first plate of the first capacitor C1 is raised from-1.2V to 0V, and since the voltage difference across the first capacitor C1 remains unchanged, the voltage of the first output signal terminal L1 is correspondingly raised from 0V to 1.2V. The second input signal terminal IN2 receives 0V, the gate-source voltage difference of the fifth transistor M5 is 1.2V, the gate-source voltage difference of the fifth transistor M5 is greater than the threshold voltage thereof, the fifth transistor M5 is turned on, the first plate of the second capacitor C2 is decreased from 0V to-1.2V, and the voltage difference between the two ends of the second capacitor C2 remains unchanged, so the voltage of the second output signal terminal L2 is correspondingly decreased by 1.2V, and is decreased from 1.2V to 0V.

Fig. 14 is a circuit schematic diagram of another level shift circuit according to an embodiment of the present invention, and referring to fig. 14, the level shift circuit further includes a third switching unit 13 and a sixth switching unit 23. A first terminal of the third switching unit 13 is electrically connected to the first power supply voltage terminal VSS, a second terminal of the third switching unit 13 is electrically connected to the second plate of the first capacitor C1, and a control terminal of the third switching unit 13 is electrically connected to the second plate of the second capacitor C2. A first terminal of the sixth switching unit 23 is electrically connected to the first power supply voltage terminal VSS, a second terminal of the sixth switching unit 23 is electrically connected to the second plate of the second capacitor C2, and a control terminal of the sixth switching unit 23 is electrically connected to the second plate of the first capacitor C1. In the first period, the third switching unit 13 is turned on to conductively electrically connect the second plate of the first capacitor C1 with the first power supply voltage terminal VSS. The voltage of the first power voltage terminal VSS is applied to the second plate of the first capacitor C1, and since the control terminal of the sixth switching unit 23 is electrically connected to the second plate of the first capacitor C1, the voltage of the first power voltage terminal VSS controls the sixth switching unit 23 to be turned off. In the second period, the sixth switching unit 23 is turned on to conductively electrically connect the second plate of the second capacitor C2 with the first power supply voltage terminal VSS. The voltage of the first power voltage terminal VSS is applied to the second plate of the second capacitor C2, and the voltage of the first power voltage terminal VSS controls the third switching unit 13 to be turned off since the control terminal of the third switching unit 13 is electrically connected to the second plate of the second capacitor C2.

Alternatively, referring to fig. 14, the third switching unit 13 includes a third transistor M3, a first pole of the third transistor M3 is electrically connected to the first power supply voltage terminal VSS, a second pole of the third transistor M3 is electrically connected to the second pole of the first capacitor C1, and a gate of the third transistor M3 is electrically connected to the second pole of the second capacitor C2. The sixth switching unit 23 includes a sixth transistor M6, a first pole of the sixth transistor M6 is electrically connected to the first power supply voltage terminal VSS, a second pole of the sixth transistor M6 is electrically connected to the second plate of the second capacitor C2, and a gate of the sixth transistor M6 is electrically connected to the second plate of the first capacitor C1.

Exemplarily, referring to fig. 14, the first transistor M1 and the fourth transistor M4 are N-type transistors, and the second transistor M2 and the fifth transistor M5 are P-type transistors. The third transistor M3 and the sixth transistor M6 are P-type transistors. The first input voltage is less than the second input voltage. The voltage of the first power voltage terminal VSS is less than the voltage of the second power voltage terminal DVDD.

For example, the voltage of the first power voltage terminal VSS is 0V, the voltage of the second power voltage terminal DVDD is 1.2V, the first input voltage is 0V, and the second input voltage is 1.2V. In the first period, the first output signal terminal L1 is 0V, and the second output signal terminal L2 is-1.2V. The gate-source voltage difference of the third transistor M3 is greater than its threshold voltage, and the third transistor M3 is turned on. The gate-source voltage difference of the sixth transistor M6 is 0V, the gate-source voltage difference of the sixth transistor M6 is less than the threshold voltage thereof, and the sixth transistor M6 is turned off. In the second period, the first output signal terminal L1 is-1.2V, and the second output signal terminal L2 is 0V. The gate-source voltage difference of the sixth transistor M6 is greater than its threshold voltage, and the sixth transistor M6 is turned on. The voltage difference between the gate and the source of the third transistor M3 is 0V, the voltage difference between the gate and the source of the third transistor M3 is less than the threshold voltage thereof, and the third transistor M3 is turned off.

Fig. 15 is a circuit schematic diagram of another level shift circuit according to an embodiment of the invention, and referring to fig. 15, the first transistor M1 and the fourth transistor M4 are P-type transistors, and the second transistor M2 and the fifth transistor M5 are N-type transistors. The third transistor M3 and the sixth transistor M6 are N-type transistors. The first input voltage is greater than the second input voltage. The voltage of the first power voltage terminal VSS is greater than the voltage of the second power voltage terminal DVDD.

Illustratively, the voltage of the first power voltage terminal VSS is 0V, the voltage of the second power voltage terminal DVDD is-1.2V, the first input voltage is 0V, and the second input voltage is-1.2V. In the first period, the first output signal terminal L1 is 0V, and the second output signal terminal L2 is 1.2V. The gate-source voltage difference of the third transistor M3 is greater than its threshold voltage, and the third transistor M3 is turned on. The gate-source voltage difference of the sixth transistor M6 is 0V, the gate-source voltage difference of the sixth transistor M6 is less than the threshold voltage thereof, and the sixth transistor M6 is turned off. In the second period, the first output signal terminal L1 is 1.2V, and the second output signal terminal L2 is 0V. The gate-source voltage difference of the sixth transistor M6 is greater than its threshold voltage, and the sixth transistor M6 is turned on. The voltage difference between the gate and the source of the third transistor M3 is 0V, the voltage difference between the gate and the source of the third transistor M3 is less than the threshold voltage thereof, and the third transistor M3 is turned off.

Alternatively, the voltage of the first power voltage terminal VSS is equal to the first input voltage, and the voltage of the second power voltage terminal DVDD is equal to the second input voltage.

Exemplarily, referring to fig. 14, the voltage of the first power voltage terminal VSS and the first input voltage are both 0V, and the voltage of the second power voltage terminal DVDD and the second input voltage are both 1.2V. In the first period, the first output signal terminal L1 is 0V, and the second output signal terminal L2 is-1.2V. In the second period, the first output signal terminal L1 is-1.2V, and the second output signal terminal L2 is 0V. Therefore, the level conversion circuit converts the voltage of 1.2V into-1.2V and outputs the voltage.

Illustratively, referring to fig. 15, the voltage of the first power voltage terminal VSS and the first input voltage are both 0V, and the voltage of the second power voltage terminal DVDD and the second input voltage are both-1.2V. In the first period, the first output signal terminal L1 is 0V, and the second output signal terminal L2 is 1.2V. In the second period, the first output signal terminal L1 is 1.2V, and the second output signal terminal L2 is 0V. Therefore, the level conversion circuit converts the voltage of-1.2V into 1.2V and outputs the voltage.

Fig. 16 is a circuit diagram of a display driving circuit according to an embodiment of the invention, and referring to fig. 16, the display driving circuit includes a level shifter 100 and a level shifter 200. The first output signal terminal L1 of the level shifter 100 is electrically connected to the first terminal of the level shifter 200, and the second output signal terminal L2 of the level shifter 100 is electrically connected to the second terminal of the level shifter 200. The display driving circuit provided by the embodiment of the invention comprises the level shift circuit 100 in the above embodiment, and can convert the voltage signal input to the level shift circuit 200, so that the voltage across two ends of the transistor in the level shift circuit 200 does not exceed the bearing range, and the service life of the level shift circuit 200 is ensured.

Exemplarily, referring to fig. 16, the display driving circuit may further include an input circuit 300 and an output circuit 400. The first input signal terminal IN1 and the second input signal terminal IN2 are electrically connected to the input circuit 300. The level shift circuit 200 is electrically connected to the output circuit 400. The display driving circuit may further include a digital-to-analog converter, a data latch, a sampling register, a holding register, and the like. The level shift circuit 200 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a twelfth transistor M12. A gate of the seventh transistor M7 and a gate of the ninth transistor M9 are both electrically connected to the first output signal terminal L1 of the level shift circuit 100. A gate of the eighth transistor M8 and a gate of the tenth transistor M10 are both electrically connected to the second output signal terminal L2 of the level shift circuit 100. A first pole of the seventh transistor M7 is electrically connected to a first pole of the eighth transistor M8. A first pole of the seventh transistor M7 is electrically connected to the first power supply voltage terminal VSS. The second pole of the seventh transistor M7 is electrically connected to the first pole of the ninth transistor M9. A second pole of the eighth transistor M8 is electrically connected to the first pole of the tenth transistor M10. A second pole of the ninth transistor M9 is electrically connected to the first pole of the eleventh transistor M11. The second pole of the tenth transistor M10 is electrically connected to the first pole of the twelfth transistor M12. A gate of the eleventh transistor M11 is electrically connected to the second pole of the eighth transistor M8. A gate of the twelfth transistor M12 is electrically connected to the second pole of the seventh transistor M7. A second pole of the eleventh transistor M11 is electrically connected to a second pole of the twelfth transistor M12. The second pole of the eleventh transistor M11 is electrically connected to the connection terminal AVEE. The second pole of the eighth transistor M8 is electrically connected to the output circuit 400.

Fig. 17 is a schematic diagram of a silicon-based organic light emitting display device according to an embodiment of the present invention, and referring to fig. 17, the silicon-based organic light emitting display device includes the display driving circuit 600 in the above embodiment, and the display driving circuit 600 is integrated on a silicon-based substrate of the silicon-based organic light emitting display device. The silicon-based organic light emitting display device may be an AR display device or a VR display device, or other silicon-based organic light emitting display devices with smaller size and smaller integration level.

Exemplarily, referring to fig. 17, the silicon-based organic light emitting display device includes a display area AA and a non-display area NAA. The display driving circuit 600 is located in the non-display area NAA.

Exemplarily, referring to fig. 17, in another embodiment, the silicon-based organic light emitting display device may further include a driving chip 500. The driving chip 500 is located in the non-display area NAA. The display driving circuit 600 may also be integrated in the driving chip 500. The driving chip 500 may be used to drive data lines (not shown in fig. 17) in the display area AA. In yet another embodiment, the driving chip 500 may also be used to drive scan lines (not shown in fig. 17) in the display area AA.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious modifications, rearrangements, combinations and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A level conversion circuit is characterized by comprising a first input module and a first capacitor;

2. The level shift circuit according to claim 1, wherein the first input module comprises a first switch unit and a second switch unit;

the control end of the first switch unit is electrically connected with the first input signal end, the first end of the first switch unit is electrically connected with the first power supply voltage end, and the second end of the first switch unit is electrically connected with the first pole plate of the first capacitor;

the control end of the second switch unit is electrically connected with the first input signal end, the first end of the second switch unit is electrically connected with the second power supply voltage end, and the second end of the second switch unit is electrically connected with the first pole plate of the first capacitor.

3. The level shift circuit of claim 2, wherein the first switching unit comprises a first transistor,

the grid electrode of the first transistor is electrically connected with the first input signal end, the first electrode of the first transistor is electrically connected with the first power supply voltage end, and the second electrode of the first transistor is electrically connected with the first polar plate of the first capacitor;

the second switch unit comprises a second transistor, a grid electrode of the second transistor is electrically connected with the first input signal end, a first electrode of the second transistor is electrically connected with the second power supply voltage end, and a second electrode of the second transistor is electrically connected with a first electrode plate of the first capacitor.

4. The circuit of claim 3, wherein the first transistor is an N-type transistor and the second transistor is a P-type transistor;

the first input voltage is less than the second input voltage;

the voltage of the first power supply voltage terminal is less than the voltage of the second power supply voltage terminal.

5. The circuit of claim 3, wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor;

the first input voltage is greater than the second input voltage;

the voltage of the first power supply voltage terminal is greater than the voltage of the second power supply voltage terminal.

6. The level shift circuit according to claim 1, further comprising a third switching unit, a first terminal of the third switching unit being electrically connected to the first power supply voltage terminal, and a second terminal of the third switching unit being electrically connected to the second plate of the first capacitor;

in the first period, the third switch unit is turned on to electrically connect the second plate of the first capacitor with the first power supply voltage end; the third switching unit is turned off during the second period.

7. The level shift circuit of claim 1, further comprising a second input block and a second capacitor;

the control end of the second input module is electrically connected with the second input signal end of the level conversion circuit, the first input end of the second input module is electrically connected with the first power supply voltage end, the second input end of the second input module is electrically connected with the second power supply voltage end, and the output end of the second input module is electrically connected with the first polar plate of the second capacitor;

the second electrode plate of the second capacitor is electrically connected with the second output signal end of the level switching circuit;

in the first period, the second input signal end inputs the second input voltage, and the second input module is controlled to electrically connect the first power supply voltage end with the first pole plate of the second capacitor;

and in a second time interval, the first input voltage is input into the second input signal end, and the second input module is controlled to electrically connect the second power supply voltage end with the first pole plate of the second capacitor.

8. The circuit of claim 7, wherein the second input module comprises a fourth switching unit and a fifth switching unit;

the control end of the fourth switching unit is electrically connected with the second input signal end, the first end of the fourth switching unit is electrically connected with the first power supply voltage end, and the second end of the fourth switching unit is electrically connected with the first pole plate of the second capacitor;

the control end of the fifth switch unit is electrically connected with the second input signal end, the first end of the fifth switch unit is electrically connected with the second power supply voltage end, and the second end of the fifth switch unit is electrically connected with the first pole plate of the second capacitor.

9. The circuit according to claim 8, wherein the fourth switching unit comprises a fourth transistor, a gate of the fourth transistor is electrically connected to the second input signal terminal, a first electrode of the fourth transistor is electrically connected to the first power voltage terminal, and a second electrode of the fourth transistor is electrically connected to the first plate of the second capacitor;

the fifth switching unit comprises a fifth transistor, a grid electrode of the fifth transistor is electrically connected with the second input signal end, a first electrode of the fifth transistor is electrically connected with the second power voltage end, and a second electrode of the fifth transistor is electrically connected with the first electrode plate of the second capacitor.

10. The circuit of claim 9, wherein the fourth transistor is an N-type transistor and the fifth transistor is a P-type transistor;

the first input voltage is less than the second input voltage;

11. The circuit of claim 9, wherein the fourth transistor is a P-type transistor and the fifth transistor is an N-type transistor;

the first input voltage is greater than the second input voltage;

12. The level shift circuit according to claim 7, further comprising a third switching unit and a sixth switching unit;

a first end of the third switching unit is electrically connected to the first power supply voltage terminal, a second end of the third switching unit is electrically connected to the second plate of the first capacitor, and a control end of the third switching unit is electrically connected to the second plate of the second capacitor;

a first end of the sixth switching unit is electrically connected to the first power voltage end, a second end of the sixth switching unit is electrically connected to the second electrode plate of the second capacitor, and a control end of the sixth switching unit is electrically connected to the second electrode plate of the first capacitor.

13. The level shift circuit according to claim 12, wherein the third switching unit includes a third transistor, a first electrode of which is electrically connected to the first power supply voltage terminal, a second electrode of which is electrically connected to the second plate of the first capacitor, and a gate electrode of which is electrically connected to the second plate of the second capacitor;

the sixth switching unit includes a sixth transistor, a first electrode of the sixth transistor is electrically connected to the first power supply voltage terminal, a second electrode of the sixth transistor is electrically connected to the second plate of the second capacitor, and a gate of the sixth transistor is electrically connected to the second plate of the first capacitor.

14. The circuit of claim 1, wherein the voltage of the first power supply voltage terminal is equal to the first input voltage and the voltage of the second power supply voltage terminal is equal to the second input voltage.

15. A display driver circuit comprising the level shifter circuit according to any one of claims 1 to 14, and a level shifter circuit;

16. A silicon-based organic light emitting display device comprising the display driver circuit of claim 15 integrated on a silicon-based substrate of the silicon-based organic light emitting display device.